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@ -63,7 +63,7 @@ enum {
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};
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enum {
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OHCI_CONTROL_CONTROL_BULK_RATIO = 3,
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OHCI_CONTROL_CONTROL_BULK_RATIO = 3, ///< This specifies the service ratio between Control and Bulk EDs. 0 = 1:1, 3 = 4:1
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OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK = BIT_(2),
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OHCI_CONTROL_LIST_ISOCHRONOUS_ENABLE_MASK = BIT_(3),
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OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK = BIT_(4),
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@ -135,7 +135,7 @@ enum {
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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ohci_data_t ohci_data TUSB_CFG_ATTR_USBRAM;
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STATIC_VAR ohci_data_t ohci_data TUSB_CFG_ATTR_USBRAM;
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static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
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@ -177,7 +177,7 @@ tusb_error_t hcd_init(void)
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OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
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OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; // clear current set bits
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OHCI_REG->interrupt_enable = OHCI_INT_WRITEBACK_DONEHEAD_MASK | OHCI_INT_RESUME_DETECTED_MASK |
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OHCI_INT_UNRECOVERABLE_ERROR_MASK | OHCI_INT_FRAME_OVERFLOW_MASK | OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
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OHCI_INT_UNRECOVERABLE_ERROR_MASK | /*OHCI_INT_FRAME_OVERFLOW_MASK |*/ OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
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OHCI_INT_MASTER_ENABLE_MASK;
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return TUSB_ERROR_NONE;
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@ -214,6 +214,14 @@ void hcd_port_unplug(uint8_t hostid)
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//--------------------------------------------------------------------+
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// CONTROL PIPE API
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//--------------------------------------------------------------------+
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
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{
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return (p_ed->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
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(p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
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(p_ed->is_interrupt_xfer ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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}
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static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
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{
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// address 0 is used as async head, which always on the list --> cannot be cleared
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@ -222,14 +230,15 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size,
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memclr_(p_ed, sizeof(ohci_ed_t));
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}
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p_ed->device_address = dev_addr;
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p_ed->endpoint_number = endpoint_addr & 0x0F;
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p_ed->direction = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
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p_ed->speed = usbh_devices[dev_addr].speed;
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p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
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p_ed->max_package_size = max_packet_size;
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p_ed->device_address = dev_addr;
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p_ed->endpoint_number = endpoint_addr & 0x0F;
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p_ed->direction = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
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p_ed->speed = usbh_devices[dev_addr].speed;
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p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
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p_ed->max_package_size = max_packet_size;
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p_ed->used = 1;
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p_ed->used = 1;
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p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
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}
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static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
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@ -276,8 +285,8 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
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gtd_init(p_setup, p_request, 8);
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p_setup->index = dev_addr;
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p_setup->pid = OHCI_PID_SETUP;
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p_setup->next_td = (uint32_t) p_data;
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p_setup->data_toggle = BIN8(10); // DATA0
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p_setup->next_td = (uint32_t) p_data;
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//------------- DATA Phase -------------//
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if (p_request->wLength > 0)
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@ -301,7 +310,6 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
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//------------- Attach TDs list to Control Endpoint -------------//
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p_ed->td_head = (uint32_t) p_setup;
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p_ed->td_tail = 0;
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OHCI_REG->command_status_bit.control_list_filled = 1;
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@ -310,13 +318,36 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
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tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
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{
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// TODO OHCI return TUSB_ERROR_NONE;
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ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
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if ( dev_addr == 0 )
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{ // addr0 serves as static head --> only set skip bitx
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p_ed->skip = 1;
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}else
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{
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return TUSB_ERROR_FAILED;
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}
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return TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// BULK/INT/ISO PIPE API
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//--------------------------------------------------------------------+
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static ohci_ed_t * ed_find_free(uint8_t dev_addr)
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static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline uint8_t ed_get_index(ohci_ed_t const * const p_ed)
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{
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return p_ed - ohci_data.device[p_ed->device_address-1].ed;
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}
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static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline ohci_ed_t * ed_from_pipe_handle(pipe_handle_t pipe_hdl)
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{
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return &ohci_data.device[pipe_hdl.dev_addr-1].ed[pipe_hdl.index];
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}
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static inline ohci_ed_t * ed_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline ohci_ed_t * ed_find_free(uint8_t dev_addr)
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{
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for(uint8_t i = 0; i < OHCI_MAX_QHD; i++)
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{
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@ -331,8 +362,8 @@ static ohci_ed_t * ed_find_free(uint8_t dev_addr)
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static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
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{
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p_ed->next_ed = p_pre->next_ed;
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p_pre->next_ed = (uint32_t) p_ed;
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p_ed->next_ed |= p_pre->next_ed; // to reserve 4 lsb bits
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p_pre->next_ed = (p_pre->next_ed & 0x0FUL) | ((uint32_t) p_ed);
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}
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pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
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@ -348,7 +379,7 @@ pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const *
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ed_init( p_ed, dev_addr, p_endpoint_desc->wMaxPacketSize.size, p_endpoint_desc->bEndpointAddress,
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p_endpoint_desc->bmAttributes.xfer, p_endpoint_desc->bInterval );
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p_ed->class_code = class_code;
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p_ed->td_tail.class_code = class_code;
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switch(p_endpoint_desc->bmAttributes.xfer)
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{
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@ -363,7 +394,7 @@ pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const *
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{
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.dev_addr = dev_addr,
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.xfer_type = p_endpoint_desc->bmAttributes.xfer,
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.index = p_ed - ohci_data.device[dev_addr-1].ed // TODO may refractor
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.index = ed_get_index(p_ed)
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};
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}
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@ -393,10 +424,9 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
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}
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}
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static tusb_error_t pipe_queue_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
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{
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ohci_ed_t* const p_ed = &ohci_data.device[pipe_hdl.dev_addr-1].ed[pipe_hdl.index];
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ohci_ed_t* const p_ed = ed_from_pipe_handle(pipe_hdl);
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if ( !p_ed->is_iso )
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{
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@ -425,7 +455,12 @@ tusb_error_t hcd_pipe_xfer(pipe_handle_t pipe_hdl, uint8_t buffer[], uint16_t t
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{
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ASSERT_STATUS( pipe_queue_xfer(pipe_hdl, buffer, total_bytes, true) );
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OHCI_REG->command_status_bit.bulk_list_filled = 1;
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tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_pipe_handle(pipe_hdl) );
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if (TUSB_XFER_BULK == xfer_type)
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{
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OHCI_REG->command_status_bit.bulk_list_filled = 1;
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}
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return TUSB_ERROR_NONE;
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}
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@ -438,27 +473,41 @@ tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl)
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bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)
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{
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// TODO OHCI
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ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
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return align16(p_ed->td_head) != align16(p_ed->td_tail.address);
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}
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bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)
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{
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// TODO OHCI
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ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
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return p_ed->halted;
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}
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bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)
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{
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// TODO OHCI
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ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
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return p_ed->halted && p_ed->is_stalled;
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}
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uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)
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{
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// TODO OHCI
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ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
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return p_ed->endpoint_number | (p_ed->direction == OHCI_PID_IN ? TUSB_DIR_DEV_TO_HOST_MASK : 0 );
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}
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tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
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{
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// TODO OHCI return TUSB_ERROR_NONE;
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ohci_ed_t * const p_ed = ed_from_pipe_handle(pipe_hdl);
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p_ed->is_stalled = 0;
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p_ed->td_tail.address &= 0x0Ful; // set tail pointer back to NULL
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p_ed->toggle = 0; // reset data toggle
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p_ed->halted = 0;
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if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;
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return TUSB_ERROR_NONE;
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}
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@ -492,7 +541,15 @@ static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
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static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
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{
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return gtd_is_control(p_qtd) ? &ohci_data.control[p_qtd->index].ed : NULL;
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if ( gtd_is_control(p_qtd) )
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{
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return &ohci_data.control[p_qtd->index].ed;
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}else
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{
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uint8_t dev_addr_idx = (((uint32_t)p_qtd) - ((uint32_t)ohci_data.device)) / sizeof(ohci_data.device[0]);
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return &ohci_data.device[dev_addr_idx].ed[p_qtd->index];
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}
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}
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static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
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@ -502,9 +559,9 @@ static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_
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offset4k(buffer_end) - offset4k(current_buffer) + 1;
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}
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static void done_queue_isr(hostid)
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static void done_queue_isr(uint8_t hostid)
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{
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uint8_t max_loop = (TUSB_CFG_HOST_DEVICE_MAX+1)*OHCI_MAX_QTD;
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uint8_t max_loop = (TUSB_CFG_HOST_DEVICE_MAX+1)*(OHCI_MAX_QTD+OHCI_MAX_ITD);
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// done head is written in reversed order of completion --> need to reverse the done queue first
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ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) align16(ohci_data.hcca.done_head) );
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@ -514,25 +571,39 @@ static void done_queue_isr(hostid)
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// TODO check if td_head is iso td
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//------------- Non ISO transfer -------------//
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ohci_gtd_t * const p_qtd = (ohci_gtd_t * const) td_head;
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tusb_event_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? TUSB_EVENT_XFER_COMPLETE :
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(p_qtd->condition_code == OHCI_CCODE_STALL) ? TUSB_EVENT_XFER_STALLED : TUSB_EVENT_XFER_ERROR;
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p_qtd->used = 0; // free TD
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if ( p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES)
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if ( (p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != TUSB_EVENT_XFER_COMPLETE) )
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{
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ohci_ed_t * const p_ed = gtd_get_ed(p_qtd);
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uint32_t const xferred_bytes = p_qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) p_qtd->buffer_end, (uint32_t) p_qtd->current_buffer_pointer);
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tusb_event_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? TUSB_EVENT_XFER_COMPLETE :
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(p_qtd->condition_code == OHCI_CCODE_STALL) ? TUSB_EVENT_XFER_STALLED : TUSB_EVENT_XFER_ERROR;
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// NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
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// When there is a error resulting this ED is halted, and this EP still has other queued TD
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// --> the Bulk list only has this halted EP queueing TDs (remaining)
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// --> Bulk list will be considered as not empty by HC !!! while there is no attempt transaction on this list
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// --> HC will not process Control list (due to service ratio when Bulk list not empty)
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// To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt
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// the TailP must be set back to NULL for processing remaining TDs
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if ((event != TUSB_EVENT_XFER_COMPLETE))
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{
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p_ed->td_tail.address &= 0x0Ful;
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p_ed->td_tail.address |= align16(p_ed->td_head); // mark halted EP as empty queue
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if ( event == TUSB_EVENT_XFER_STALLED ) p_ed->is_stalled = 1;
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}
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pipe_handle_t pipe_hdl =
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{
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.dev_addr = p_ed->device_address,
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.xfer_type = TUSB_XFER_CONTROL, // TODO other type
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.index = 0 // TODO other type
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.xfer_type = ed_get_xfer_type(p_ed),
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};
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usbh_xfer_isr(pipe_hdl, 0, // TODO class code
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event, xferred_bytes);
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if ( pipe_hdl.xfer_type != TUSB_XFER_CONTROL) pipe_hdl.index = ed_get_index(p_ed);
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usbh_xfer_isr(pipe_hdl, p_ed->td_tail.class_code, event, xferred_bytes);
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}
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td_head = (ohci_td_item_t*) td_head->next_td;
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