rename to hal_dcd_pipe_clear_stall()
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792f51a927
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@ -378,15 +378,13 @@ void hal_dcd_pipe_stall(endpoint_handle_t edpt_hdl)
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(*reg_control) |= ENDPTCTRL_MASK_STALL << (edpt_hdl.index & 0x01 ? 16 : 0);
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(*reg_control) |= ENDPTCTRL_MASK_STALL << (edpt_hdl.index & 0x01 ? 16 : 0);
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}
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}
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tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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void hal_dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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{
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{
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volatile uint32_t * reg_control = get_reg_control_addr(coreid, edpt_addr2phy(edpt_addr));
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volatile uint32_t * reg_control = get_reg_control_addr(coreid, edpt_addr2phy(edpt_addr));
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// data toggle also need to be reset
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// data toggle also need to be reset
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(*reg_control) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0);
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(*reg_control) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0);
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(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0));
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(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0));
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return TUSB_ERROR_NONE;
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}
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}
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bool hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, endpoint_handle_t* eh)
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bool hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, endpoint_handle_t* eh)
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@ -91,12 +91,12 @@ bool hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endp
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tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes); // only queue, not transferring yet
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tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes); // only queue, not transferring yet
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tusb_error_t hal_dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete);
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tusb_error_t hal_dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete);
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void hal_dcd_pipe_stall(endpoint_handle_t edpt_hdl);
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bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl);
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bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl);
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// TODO coreid + endpoint address are part of endpoint handle, not endpoint handle, data toggle also need to be reset
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// TODO coreid + endpoint address are part of endpoint handle, not endpoint handle, data toggle also need to be reset
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tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr);
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void hal_dcd_pipe_stall(endpoint_handle_t edpt_hdl);
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void hal_dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -458,13 +458,11 @@ void hal_dcd_pipe_stall(endpoint_handle_t edpt_hdl)
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+edpt_hdl.index, 1, SIE_SET_ENDPOINT_STALLED_MASK);
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+edpt_hdl.index, 1, SIE_SET_ENDPOINT_STALLED_MASK);
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}
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}
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tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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void hal_dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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{
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{
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uint8_t ep_id = edpt_addr2phy(edpt_addr);
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uint8_t ep_id = edpt_addr2phy(edpt_addr);
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0);
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sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0);
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return TUSB_ERROR_FAILED;
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}
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}
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void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes)
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void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes)
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@ -438,7 +438,7 @@ bool dcd_pipe_is_stalled(endpoint_handle_t edpt_hdl)
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return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
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return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
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}
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}
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tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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void hal_dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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{
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{
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uint8_t ep_id = edpt_addr2phy(edpt_addr);
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uint8_t ep_id = edpt_addr2phy(edpt_addr);
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// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
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// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
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@ -454,8 +454,6 @@ tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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{
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{
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queue_xfer_in_next_td(ep_id);
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queue_xfer_in_next_td(ep_id);
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}
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}
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return TUSB_ERROR_NONE;
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}
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}
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endpoint_handle_t hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
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endpoint_handle_t hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code)
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@ -297,7 +297,7 @@ tusb_error_t usbd_control_request_subtask(uint8_t coreid, tusb_control_request_t
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TUSB_REQUEST_TYPE_STANDARD == p_request->bmRequestType_bit.type &&
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TUSB_REQUEST_TYPE_STANDARD == p_request->bmRequestType_bit.type &&
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TUSB_REQUEST_CLEAR_FEATURE == p_request->bRequest )
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TUSB_REQUEST_CLEAR_FEATURE == p_request->bRequest )
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{
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{
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dcd_pipe_clear_stall(coreid, u16_low_u8(p_request->wIndex) );
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hal_dcd_pipe_clear_stall(coreid, u16_low_u8(p_request->wIndex) );
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} else
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} else
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{
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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