add semaphore post in usbh_isr for control pipe

add osal_queue_send in usbh_device_plugged
add macro for placing breakpoint macros
fix ehci init:
- regs->cmd or (add run_stop)
- enable port power in portsc
add tusb_task_runner in main loop
This commit is contained in:
hathach 2013-03-12 20:04:29 +07:00
parent 60c2caf84a
commit d2bd80109e
10 changed files with 39 additions and 12 deletions

View File

@ -47,5 +47,6 @@ void SysTick_Handler (void)
void check_failed(uint8_t *file, uint32_t line)
{
(void) file;
(void) line;
}

View File

@ -24,6 +24,8 @@ int main(void)
printf("reset\n");
while (1)
{
tusb_task_runner();
if (current_tick + 30*1000 < system_ticks)
{
current_tick += 30*1000;

View File

@ -83,6 +83,12 @@
//--------------------------------------------------------------------+
// MACROS
//--------------------------------------------------------------------+
#ifndef _TEST_
#define ASM_BREAKPOINT __asm("BKPT #0\n") // Place breakpoint to stop the debugger at desire
#else
#define ASM_BREAKPOINT
#endif
#define STRING_(x) #x // stringify without expand
#define XSTRING_(x) STRING_(x) // expand then stringify
#define STRING_CONCAT_(a, b) a##b // concat without expand

View File

@ -111,10 +111,10 @@ typedef ATTR_PREPACKED struct ATTR_PACKED {
uint8_t bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint.
ATTR_PREPACKED struct ATTR_PACKED {
uint8_t xfer : 2;
uint8_t sync : 2;
uint8_t xfer : 2;
uint8_t sync : 2;
uint8_t usage : 2;
uint8_t : 2;
uint8_t : 2;
} bmAttributes ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host.
uint16_t wMaxPacketSize ; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero.

View File

@ -62,7 +62,7 @@ tusb_error_t hal_init()
LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
//------------- reset controller & set role -------------//
hcd_controller_reset(0);
hcd_controller_reset(0); // TODO where to place prototype
LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
hal_interrupt_enable();

View File

@ -232,6 +232,7 @@ void hcd_isr(uint8_t hostid)
if (int_status & EHCI_INT_MASK_ERROR)
{
// TODO something going wrong
ASM_BREAKPOINT;
}
//------------- some QTD/SITD/ITD with IOC set is completed -------------//
@ -247,10 +248,8 @@ void hcd_isr(uint8_t hostid)
if (int_status & EHCI_INT_MASK_PORT_CHANGE)
{
printf("%s %d\n", __PRETTY_FUNCTION__, __LINE__);
if (regs->portsc_bit.connect_status_change)
{
printf("%s %d\n", __PRETTY_FUNCTION__, __LINE__);
port_connect_status_isr(hostid);
}
@ -278,11 +277,10 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
regs->usb_int_enable =
EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE
| EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_ASYNC
#if EHCI_PERIODIC_LIST
| EHCI_INT_MASK_NXP_PERIODIC
#endif
;
| EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_ASYNC;
//------------- Asynchronous List -------------//
ehci_qhd_t * const async_head = get_async_head(hostid);
@ -292,6 +290,7 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
async_head->head_list_flag = 1;
async_head->qtd_overlay.halted = 1; // inactive most of time
async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
regs->async_list_base = (uint32_t) async_head;
@ -321,7 +320,7 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
//------------- USB CMD Register -------------//
regs->usb_cmd = BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
regs->usb_cmd |= BIT_(EHCI_USBCMD_POS_RUN_STOP) | BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
#if EHCI_PERIODIC_LIST
| BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE)
#endif
@ -330,6 +329,8 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
//------------- ConfigFlag Register (skip) -------------//
regs->portsc_bit.port_power = 1; // enable port power
return TUSB_ERROR_NONE;
}

View File

@ -320,6 +320,7 @@ enum ehci_interrupt_mask_{
};
enum ehci_usbcmd_pos_ {
EHCI_USBCMD_POS_RUN_STOP = 0,
EHCI_USBCMD_POS_FRAMELIST_SZIE = 2,
EHCI_USBCMD_POS_PERIOD_ENABLE = 4,
EHCI_USBCMD_POS_ASYNC_ENABLE = 5,

View File

@ -171,7 +171,7 @@ void usbh_isr(pipe_handle_t pipe_hdl, uint8_t class_code)
{
if (class_code == 0) // Control transfer
{
// TODO some semaphore posting
osal_semaphore_post( usbh_device_info_pool[ pipe_hdl.dev_addr ].sem_hdl );
}else if (usbh_class_drivers[class_code].isr)
{
usbh_class_drivers[class_code].isr(pipe_hdl);
@ -183,7 +183,9 @@ void usbh_isr(pipe_handle_t pipe_hdl, uint8_t class_code)
void usbh_device_plugged_isr(uint8_t hostid, tusb_speed_t speed)
{
osal_queue_send(enum_queue_hdl,
*( (uint32_t*) ( &(usbh_enumerate_t){ .core_id = hostid, .speed = speed} ) )
);
}
void usbh_device_unplugged_isr(uint8_t hostid)

View File

@ -66,3 +66,13 @@ void tusb_isr(uint8_t controller_id)
#endif
}
#if TUSB_CFG_OS == TUSB_OS_NONE
// periodically/continuously called in the main loop
void tusb_task_runner(void)
{
#if MODE_HOST_SUPPORTED
usbh_enumeration_task(); // TODO prototype
#endif
}
#endif

View File

@ -83,6 +83,10 @@
tusb_error_t tusb_init(void);
#if TUSB_CFG_OS == TUSB_OS_NONE
void tusb_task_runner(void);
#endif
#ifdef __cplusplus
}
#endif