clean up
This commit is contained in:
hathach
parent
b34724215b
commit
cf0a475a2e
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@ -52,22 +52,23 @@
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static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
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// Host mode uses one shared endpoint register for non-interrupt endpoint
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struct hw_endpoint eps[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
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#define epx (eps[0])
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static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
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#define epx (ep_pool[0])
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#define usb_hw_set hw_set_alias(usb_hw)
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#define usb_hw_set hw_set_alias(usb_hw)
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#define usb_hw_clear hw_clear_alias(usb_hw)
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// Used for hcd pipe busy.
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// todo still a bit wasteful
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// top bit set if valid
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uint8_t dev_ep_map[CFG_TUSB_HOST_DEVICE_MAX][1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS][2];
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// Flags we set by default in sie_ctrl (we add other bits on top)
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static uint32_t sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS |
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USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
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USB_SIE_CTRL_PULLDOWN_EN_BITS |
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USB_SIE_CTRL_EP0_INT_1BUF_BITS;
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enum {
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sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS |
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USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
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USB_SIE_CTRL_PULLDOWN_EN_BITS |
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USB_SIE_CTRL_EP0_INT_1BUF_BITS
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};
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static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
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{
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@ -78,19 +79,22 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
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uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
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uint mapping = dev_ep_map[dev_addr-1][num][in];
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pico_trace("Get dev addr %d ep %d = %d\n", dev_addr, ep_addr, mapping);
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return mapping >= 128 ? eps + (mapping & 0x7fu) : NULL;
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return mapping >= 128 ? ep_pool + (mapping & 0x7fu) : NULL;
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}
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static void set_dev_ep(uint8_t dev_addr, uint8_t ep_addr, struct hw_endpoint *ep)
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{
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uint8_t num = tu_edpt_number(ep_addr);
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uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
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uint32_t index = ep - eps;
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hard_assert(index < TU_ARRAY_SIZE(eps));
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uint8_t in = (uint8_t) tu_edpt_dir(ep_addr);
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uint32_t index = ep - ep_pool;
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hard_assert(index < TU_ARRAY_SIZE(ep_pool));
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// todo revisit why dev_addr can be 0 here
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if (dev_addr) {
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dev_ep_map[dev_addr-1][num][in] = 128u | index;
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}
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pico_trace("Set dev addr %d ep %d = %d\n", dev_addr, ep_addr, index);
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}
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@ -153,7 +157,7 @@ static void hw_handle_buff_status(void)
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if (remaining_buffers & bit)
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{
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remaining_buffers &= ~bit;
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_handle_buff_status_bit(bit, &eps[i]);
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_handle_buff_status_bit(bit, &ep_pool[i]);
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}
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}
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@ -206,13 +210,15 @@ static void hcd_rp2040_irq(void)
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{
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handled |= USB_INTS_TRANS_COMPLETE_BITS;
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usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
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TU_LOG(2, "Transfer complete\n");
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hw_trans_complete();
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}
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if (status & USB_INTS_BUFF_STATUS_BITS)
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{
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handled |= USB_INTS_BUFF_STATUS_BITS;
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// print_bufctrl32(*epx.buffer_control);
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TU_LOG(2, "Buffer complete\n");
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print_bufctrl32(*epx.buffer_control);
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hw_handle_buff_status();
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}
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@ -234,7 +240,7 @@ static void hcd_rp2040_irq(void)
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if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
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{
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usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
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// print_bufctrl32(*epx.buffer_control);
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print_bufctrl32(*epx.buffer_control);
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panic("Data Seq Error \n");
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}
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@ -247,9 +253,9 @@ static void hcd_rp2040_irq(void)
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static struct hw_endpoint *_next_free_interrupt_ep(void)
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{
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struct hw_endpoint *ep = NULL;
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for (uint i = 1; i < TU_ARRAY_SIZE(eps); i++)
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for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
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{
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ep = &eps[i];
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ep = &ep_pool[i];
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if (!ep->configured)
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{
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// Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
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@ -263,6 +269,7 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
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static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
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{
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struct hw_endpoint *ep = NULL;
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if (transfer_type == TUSB_XFER_INTERRUPT)
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{
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ep = _next_free_interrupt_ep();
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@ -283,6 +290,7 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
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ep->endpoint_control = &usbh_dpram->epx_ctrl;
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ep->hw_data_buf = &usbh_dpram->epx_data[0];
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}
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return ep;
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}
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@ -345,24 +353,9 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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// If it's an interrupt endpoint we need to set up the buffer control
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// register
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}
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}
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static void hw_endpoint_init(uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc)
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{
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// Allocated differently based on if it's an interrupt endpoint or not
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struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
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_hw_endpoint_init(ep,
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dev_addr,
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ep_desc->bEndpointAddress,
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ep_desc->wMaxPacketSize.size,
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ep_desc->bmAttributes.xfer,
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ep_desc->bInterval);
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// Map this struct to ep@device address
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set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
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}
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//--------------------------------------------------------------------+
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// HCD API
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//--------------------------------------------------------------------+
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@ -377,7 +370,7 @@ bool hcd_init(uint8_t rhport)
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irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
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// clear epx and interrupt eps
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memset(&eps, 0, sizeof(eps));
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memset(&ep_pool, 0, sizeof(ep_pool));
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// Enable in host mode with SOF / Keep alive on
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usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
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@ -420,6 +413,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
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return TUSB_SPEED_FULL;
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default:
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panic("Invalid speed\n");
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return TUSB_SPEED_INVALID;
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}
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}
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@ -444,7 +438,7 @@ void hcd_int_disable(uint8_t rhport)
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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pico_info("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
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pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
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// Get appropriate ep. Either EPX or interrupt endpoint
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struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
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@ -452,13 +446,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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if (ep_addr != ep->ep_addr)
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{
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// Direction has flipped so re init it but with same properties
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// TODO treat IN and OUT as invidual endpoints
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// Direction has flipped on endpoint control so re init it but with same properties
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_hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
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}
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// True indicates this is the start of the transfer
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_hw_endpoint_xfer(ep, buffer, buflen, true);
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_hw_endpoint_xfer_start(ep, buffer, buflen);
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// If a normal transfer (non-interrupt) then initiate using
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// sie ctrl registers. Otherwise interrupt ep registers should
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@ -479,27 +472,30 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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pico_info("hcd_setup_send dev_addr %d\n", dev_addr);
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// Copy data into setup packet buffer
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memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
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// Configure EP0 struct with setup info for the trans complete
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struct hw_endpoint *ep = _hw_endpoint_allocate(0);
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// EP0 out
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_hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
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assert(ep->configured);
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ep->total_len = 8;
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ep->total_len = 8;
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ep->transfer_size = 8;
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ep->active = true;
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ep->sent_setup = true;
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ep->active = true;
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ep->sent_setup = true;
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// Set device address
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usb_hw->dev_addr_ctrl = dev_addr;
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// Set pre if we are a low speed device on full speed hub
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uint32_t flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS;
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flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
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uint32_t const flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
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(need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
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usb_hw->sie_ctrl = flags;
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return true;
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}
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@ -510,8 +506,23 @@ uint32_t hcd_frame_number(uint8_t rhport)
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
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hw_endpoint_init(dev_addr, ep_desc);
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// Allocated differently based on if it's an interrupt endpoint or not
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struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
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_hw_endpoint_init(ep,
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dev_addr,
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ep_desc->bEndpointAddress,
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ep_desc->wMaxPacketSize.size,
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ep_desc->bmAttributes.xfer,
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ep_desc->bInterval);
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// Map this struct to ep@device address
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set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
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return true;
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}
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