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Fix resume, always init FS clock. 

Signed-off-by: MasterPhi <admin@hifiphile.com>
This commit is contained in:
MasterPhi 2021-06-15 17:53:09 +02:00
parent 85fc423569
commit ca8e8041ef
3 changed files with 5 additions and 6 deletions
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4
examples/device/hid_composite/src/tusb_config.h
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@ -48,7 +48,7 @@
// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
#ifndef BOARD_DEVICE_RHPORT_SPEED #ifndef BOARD_DEVICE_RHPORT_SPEED
#if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56) CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
#define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED
#else #else
#define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED
@ -69,7 +69,7 @@
#endif #endif
// CFG_TUSB_DEBUG is defined by compiler in DEBUG build // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
// #define CFG_TUSB_DEBUG 0 #define CFG_TUSB_DEBUG 0
/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
* Tinyusb use follows macros to declare transferring memory so that they can be put * Tinyusb use follows macros to declare transferring memory so that they can be put

5
src/portable/microchip/samx7x/dcd_samx7x.c
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@ -49,7 +49,7 @@
# if TUD_OPT_HIGH_SPEED # if TUD_OPT_HIGH_SPEED
# define USE_DUAL_BANK 0 # define USE_DUAL_BANK 0
# else # else
# define USE_DUAL_BANK 1 # define USE_DUAL_BANK 0
# endif # endif
#endif #endif
@ -108,12 +108,10 @@ void dcd_init (uint8_t rhport)
PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU); PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
// Wait until USB UTMI stabilize // Wait until USB UTMI stabilize
while (!(PMC->PMC_SR & PMC_SR_LOCKU)); while (!(PMC->PMC_SR & PMC_SR_LOCKU));
#if !TUD_OPT_HIGH_SPEED
// Enable USB FS clk // Enable USB FS clk
PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2; PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1); PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
PMC->PMC_SCER = PMC_SCER_USBCLK; PMC->PMC_SCER = PMC_SCER_USBCLK;
#endif
dcd_connect(rhport); dcd_connect(rhport);
} }
@ -346,6 +344,7 @@ void dcd_int_handler(uint8_t rhport)
{ {
(void) rhport; (void) rhport;
uint32_t int_status = USBHS->USBHS_DEVISR; uint32_t int_status = USBHS->USBHS_DEVISR;
int_status &= USBHS->USBHS_DEVIMR;
// End of reset interrupt // End of reset interrupt
if (int_status & USBHS_DEVISR_EORST) if (int_status & USBHS_DEVISR_EORST)
{ {

2
src/tusb_option.h
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@ -61,7 +61,7 @@
#define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x #define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x
#define OPT_MCU_SAMD11 204 ///< MicroChip SAMD11 #define OPT_MCU_SAMD11 204 ///< MicroChip SAMD11
#define OPT_MCU_SAML22 205 ///< MicroChip SAML22 #define OPT_MCU_SAML22 205 ///< MicroChip SAML22
#define OPT_MCU_SAMX7X 206 ///< MicroChip SAME70, S70, V70, V71 family #define OPT_MCU_SAMX7X 206 ///< MicroChip SAME70, S70, V70, V71 family
// STM32 // STM32