stm32f4: Refactor IN and OUT endpoint interrupt handling into their own functions.
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f43161353c
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c95ad426c6
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@ -553,40 +553,7 @@ static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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}
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}
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}
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}
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void OTG_FS_IRQHandler(void) {
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static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTSTS_USBRST) {
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// USBRST is start of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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bus_reset();
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}
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if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
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// ENUMDNE detects speed of the link. For full-speed, we
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// always expect the same value. This interrupt is considered
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// the end of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
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end_of_reset();
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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}
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if(int_status & USB_OTG_GINTSTS_SOF) {
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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if(int_status & USB_OTG_GINTSTS_RXFLVL) {
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read_rx_fifo(out_ep);
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}
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// OUT endpoint interrupt handling.
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if(int_status & USB_OTG_GINTSTS_OEPINT) {
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// DAINT for a given EP clears when DOEPINTx is cleared.
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// DAINT for a given EP clears when DOEPINTx is cleared.
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// OEPINT will be cleared when DAINT's out bits are cleared.
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// OEPINT will be cleared when DAINT's out bits are cleared.
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for(int n = 0; n < 4; n++) {
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for(int n = 0; n < 4; n++) {
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@ -621,9 +588,7 @@ void OTG_FS_IRQHandler(void) {
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}
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}
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}
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}
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// IN endpoint interrupt handling.
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static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
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if(int_status & USB_OTG_GINTSTS_IEPINT) {
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// DAINT for a given EP clears when DIEPINTx is cleared.
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// DAINT for a given EP clears when DIEPINTx is cleared.
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// IEPINT will be cleared when DAINT's out bits are cleared.
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// IEPINT will be cleared when DAINT's out bits are cleared.
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for(uint8_t n = 0; n < 4; n++) {
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for(uint8_t n = 0; n < 4; n++) {
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@ -645,6 +610,47 @@ void OTG_FS_IRQHandler(void) {
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}
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}
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}
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}
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}
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}
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void OTG_FS_IRQHandler(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTSTS_USBRST) {
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// USBRST is start of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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bus_reset();
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}
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if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
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// ENUMDNE detects speed of the link. For full-speed, we
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// always expect the same value. This interrupt is considered
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// the end of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
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end_of_reset();
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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}
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if(int_status & USB_OTG_GINTSTS_SOF) {
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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if(int_status & USB_OTG_GINTSTS_RXFLVL) {
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read_rx_fifo(out_ep);
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}
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// OUT endpoint interrupt handling.
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if(int_status & USB_OTG_GINTSTS_OEPINT) {
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handle_epout_ints(dev, out_ep);
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}
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// IN endpoint interrupt handling.
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if(int_status & USB_OTG_GINTSTS_IEPINT) {
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handle_epin_ints(dev, in_ep);
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}
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}
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}
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#endif
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#endif
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