Implement dynamic FIFO RAM allocation according to configuration desc.
This commit is contained in:
Reinhard Panhuber
parent
01903a4a6d
commit
c557bf7b2e
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@ -137,6 +137,15 @@ typedef struct {
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uint16_t max_size;
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} xfer_ctl_t;
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// EP size and transfer type report
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typedef struct TU_ATTR_PACKED {
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// The following format may look complicated but it is the most elegant way of addressing the required fields: EP number, EP direction, and EP transfer type.
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// The codes assigned to those fields, according to the USB specification, can be neatly used as indices.
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uint16_t ep_size[EP_MAX][2]; ///< dim 1: EP number, dim 2: EP direction denoted by TUSB_DIR_OUT (= 0) and TUSB_DIR_IN (= 1)
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bool ep_transfer_type[EP_MAX][2][4]; ///< dim 1: EP number, dim 2: EP direction, dim 3: transfer type, where 0 = Control, 1 = Isochronous, 2 = Bulk, and 3 = Interrupt
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///< I know very well that EP0 can only be used as control EP and we waste space here but for the sake of simplicity we accept that. It is used in a non-persistent way anyway!
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} ep_sz_tt_report_t;
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typedef volatile uint32_t * usb_fifo_t;
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xfer_ctl_t xfer_status[EP_MAX][2];
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@ -569,7 +578,7 @@ void dcd_disconnect(uint8_t rhport)
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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{
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USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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// USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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@ -579,8 +588,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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TU_ASSERT(epnum < EP_MAX);
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// TODO ISO endpoint can be up to 1024 bytes
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TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 512 : 64));
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if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS)
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{
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TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 512 : 64));
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}
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else
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{
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TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 1024 : 1023));
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}
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xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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xfer->max_size = desc_edpt->wMaxPacketSize.size;
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@ -595,6 +610,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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}
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else
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{
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// FIFO allocation done in dcd_alloc_mem_for_conf()
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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@ -620,29 +637,29 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// - Interrupt is EPSize
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// - Bulk/ISO is max(EPSize, remaining-fifo / non-opened-EPIN)
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uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
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uint16_t fifo_size = desc_edpt->wMaxPacketSize.size / 4;
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if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
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{
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uint8_t opened = 0;
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for(uint8_t i = 0; i < EP_MAX; i++)
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{
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if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
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}
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// EP Size or equally divided of remaining whichever is larger
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fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
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}
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// FIFO overflows, we probably need a better allocating scheme
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TU_ASSERT(fifo_size <= fifo_remaining);
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// DIEPTXF starts at FIFO #1.
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// Both TXFD and TXSA are in unit of 32-bit words.
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += fifo_size;
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// uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
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// uint16_t fifo_size = desc_edpt->wMaxPacketSize.size / 4;
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//
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// if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
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// {
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// uint8_t opened = 0;
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// for(uint8_t i = 0; i < EP_MAX; i++)
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// {
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// if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
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// }
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//
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// // EP Size or equally divided of remaining whichever is larger
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// fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
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// }
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//
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// // FIFO overflows, we probably need a better allocating scheme
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// TU_ASSERT(fifo_size <= fifo_remaining);
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//
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// // DIEPTXF starts at FIFO #1.
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// // Both TXFD and TXSA are in unit of 32-bit words.
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// usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
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//
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// _allocated_fifo_words += fifo_size;
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
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(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
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@ -1071,6 +1088,53 @@ void dcd_int_handler(uint8_t rhport)
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}
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}
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// Helper function which parses through the current configuration descriptors to find the biggest EPs in size.
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static bool get_ep_size_report(uint8_t rhport, tusb_desc_configuration_t const * desc_cfg, ep_sz_tt_report_t * p_report)
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{
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(void) rhport;
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// tu_memclr(p_report, sizeof(ep_sz_tt_report_t)); // This does not initialize the first two entries ... i do not know why!
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// EP0 sizes and usages are fixed
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p_report->ep_size[0][TUSB_DIR_OUT] = p_report->ep_size[0][TUSB_DIR_IN] = CFG_TUD_ENDPOINT0_SIZE;
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p_report->ep_transfer_type[0][TUSB_DIR_OUT][TUSB_XFER_CONTROL] = p_report->ep_transfer_type[0][TUSB_DIR_IN][TUSB_XFER_CONTROL] = true;
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// Parse interface descriptor
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uint8_t const * p_desc = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t);
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uint8_t const * desc_end = ((uint8_t const*) desc_cfg) + desc_cfg->wTotalLength;
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uint8_t addr;
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while( p_desc < desc_end )
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{
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if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc))
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{
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addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
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// Verify values - this checks may be omitted in case we trust the descriptors to be okay
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TU_VERIFY(tu_edpt_number(addr) < EP_MAX);
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TU_VERIFY(tu_edpt_dir(addr) <= TUSB_DIR_IN);
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TU_VERIFY(((tusb_desc_endpoint_t const*) p_desc)->bmAttributes.xfer <= TUSB_XFER_INTERRUPT);
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p_report->ep_size[tu_edpt_number(addr)][tu_edpt_dir(addr)] = tu_max16(p_report->ep_size[tu_edpt_number(addr)][tu_edpt_dir(addr)], ((tusb_desc_endpoint_t const*) p_desc)->wMaxPacketSize.size);
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p_report->ep_transfer_type[tu_edpt_number(addr)][tu_edpt_dir(addr)][((tusb_desc_endpoint_t const*) p_desc)->bmAttributes.xfer] = true;
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}
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p_desc = tu_desc_next(p_desc); // Proceed
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}
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return true;
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}
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// Setup FIFO buffers at configuration time.
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// The idea is to use this information such that the FIFOs need to be configured only once
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// at configuration time and no more later. This makes it easy in case you want to close and open EPs for different
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// purposes at any time (without taking care of other active EPs). You also avoid the nasty need of defragmenting
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// the TX buffers, which is likely to happen.
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// Certainly, this function does not allow for the highest possible flexibility as it only works in the worst case
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// (all biggest EPs can be active at the same time). However, this should not be a problem for almost all applications.
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// Spare space is assigned equally divided to bulk and interrupt EPs.
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// Pure isochronous EPs do not get any spare space as it does not make any sense.
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TU_ATTR_WEAK bool dcd_alloc_mem_for_conf(uint8_t rhport, tusb_desc_configuration_t const * desc_cfg)
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{
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(void) rhport;
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@ -1079,9 +1143,9 @@ TU_ATTR_WEAK bool dcd_alloc_mem_for_conf(uint8_t rhport, tusb_desc_configuration
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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// for(uint8_t n = 0; n < EP_MAX; n++) {
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// out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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// }
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// for(uint8_t n = 0; n < EP_MAX; n++) {
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// out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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// }
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out_ep[0].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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@ -1092,17 +1156,112 @@ TU_ATTR_WEAK bool dcd_alloc_mem_for_conf(uint8_t rhport, tusb_desc_configuration
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// usb_otg->GINTMSK &= ~(USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT);
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// Reconfigure RX buffer and EP0 TX buffer
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_allocated_fifo_words = 47 + 2*EP_MAX;
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// Determine maximum required spaces for individual EPs and what kind of usage (control, bulk, etc.) they are used for
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ep_sz_tt_report_t report = {0}; // dim 1: EP number, dim 2: EP direction, dim 3: transfer type
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TU_VERIFY(get_ep_size_report(rhport, desc_cfg, &report));
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// With that information, set the following up:
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// The RX buffer size (as it is a shared buffer here) is set to the sum of the two biggest out EPs plus all the required extra words used for setup packets etc.
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// This should work well for all kinds of applications
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// Determine number of used out EPs of current configuration and size of two biggest out EPs
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uint8_t nUsedOutEPs = 0, cnt_ep, cnt_tt;
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bool tmp;
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uint16_t sz[2] = {0, 0};
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for (cnt_ep = 0; cnt_ep < EP_MAX; cnt_ep++)
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{
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tmp = false;
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for (cnt_tt = 0; cnt_tt <= TUSB_XFER_INTERRUPT; cnt_tt++)
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{
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tmp |= report.ep_transfer_type[cnt_ep][TUSB_DIR_OUT][cnt_tt];
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}
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nUsedOutEPs += tmp;
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if (sz[0] < report.ep_size[cnt_ep][TUSB_DIR_OUT])
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{
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sz[1] = sz[0];
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sz[0] = report.ep_size[cnt_ep][TUSB_DIR_OUT];
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}
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}
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// For configuration use the approach as explained in bus_reset()
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_allocated_fifo_words = 15 + 2*nUsedOutEPs + (sz[0] / 4) + (sz[0] % 4 > 0 ? 1 : 0) + (sz[1] / 4) + (sz[1] % 4 > 0 ? 1 : 0) + 2; // again, i do not really know why we need + 2 but otherwise it does not work
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usb_otg->GRXFSIZ = _allocated_fifo_words;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
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// Control IN uses FIFO 0 with report.ep_size[0][TUSB_DIR_IN] bytes ( report.ep_size[0][TUSB_DIR_IN]/4 32-bit word )
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usb_otg->DIEPTXF0_HNPTXFSIZ = (report.ep_size[0][TUSB_DIR_IN]/4 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += 16;
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_allocated_fifo_words += report.ep_size[0][TUSB_DIR_IN]/4; // Since EP0 size MUST be a power of two we do not need to take care of remainders
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// usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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// For configuration of remaining in EPs use the approach as explained in dcd_edpt_open() except that:
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// - ISO EPs only get EP size as FIFO size. More makes no sense since within one frame precisely EP size bytes are transfered and not more.
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// Furthermore, double buffering is not possible (for this silicon) since once FIFO was written to and transmit bit was set you are
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// not allowed to write to the FIFO any more until transmit was done. So you can not send something and buffer the next frame in the
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// meantime into the buffer. TODO: check for high speed and uC types which can do this!
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// - Interrupt EPs only get EP size as FIFO size
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// - Bulk and control (other than EP0 - this is possible) get spare space equally divided - those profit the most from extra space
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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// --------------- 320 or 1024 ( 1280 or 4096 bytes )
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// | IN FIFO MAX |
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// ---------------
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// | ... |
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// --------------- y + x + w + GRXFSIZ
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// | IN FIFO 2 |
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// --------------- x + w + GRXFSIZ
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// | IN FIFO 1 |
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// --------------- w + GRXFSIZ
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// | IN FIFO 0 |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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// --------------- 0
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//
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// In FIFO is allocated by following rules:
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// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
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// - Offset: allocated so far
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// - Size - as described above
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// Determine required numbers
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// Remaining space available in bytes
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uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
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// Required space by EPs in words, number of bulk and control EPs
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uint16_t ep_sz_total = 0;
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uint8_t nbc = 0;
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// EP0 is already taken care of so exclude that here
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for (cnt_ep = 1; cnt_ep < EP_MAX; cnt_ep++)
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{
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ep_sz_total += report.ep_size[cnt_ep][TUSB_DIR_IN] / 4 + (report.ep_size[cnt_ep][TUSB_DIR_IN] % 4 > 0 ? 1 : 0); // Since we need full words take care of remainders!
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nbc += (report.ep_transfer_type[cnt_ep][TUSB_DIR_IN][TUSB_XFER_BULK] | report.ep_transfer_type[cnt_ep][TUSB_DIR_IN][TUSB_XFER_CONTROL]);
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}
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if (ep_sz_total > fifo_remaining)
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{
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// Too less space available to apply this allocation scheme - return false and set a flag such that a different approach may be used TODO: introduce flag
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return false;
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}
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uint16_t extra_space = nbc > 0 ? fifo_remaining / nbc : 0; // If no bulk or control EPs are used we just leave the rest of the memory unused
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uint16_t fifo_size;
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// Setup FIFOs
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for (cnt_ep = 1; cnt_ep < EP_MAX; cnt_ep++)
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{
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// If EP is used
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if (report.ep_size[cnt_ep][TUSB_DIR_IN] > 0)
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{
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fifo_size = report.ep_size[cnt_ep][TUSB_DIR_IN] / 4 + (report.ep_size[cnt_ep][TUSB_DIR_IN] % 4 > 0 ? 1 : 0) + ((report.ep_transfer_type[cnt_ep][TUSB_DIR_IN][TUSB_XFER_BULK] || report.ep_transfer_type[cnt_ep][TUSB_DIR_IN][TUSB_XFER_CONTROL]) ? extra_space : 0);
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usb_otg->DIEPTXF[cnt_ep - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += fifo_size;
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}
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}
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// usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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// Enable interrupts
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dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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@ -1111,6 +1270,8 @@ TU_ATTR_WEAK bool dcd_alloc_mem_for_conf(uint8_t rhport, tusb_desc_configuration
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// USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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out_ep[0].DOEPCTL |= USB_OTG_DOEPCTL_CNAK;
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return true;
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}
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