Add hcd_musb.c
This commit is contained in:
kkitayam
parent
7413b6b020
commit
b50cf856b3
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@ -0,0 +1,858 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Koji KITAYAMA
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if TUSB_OPT_HOST_ENABLED && \
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TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
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#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
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/* GCC warns that an address may be unaligned, even though
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* the target CPU has the capability for unaligned memory access. */
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_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
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#endif
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#include "host/hcd.h"
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#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
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#include "musb_msp432e.h"
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#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
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#include "musb_tm4c.h"
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// HACK generalize later
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#include "musb_type.h"
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#define FIFO0_WORD FIFO0
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#else
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#error "Unsupported MCUs"
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#endif
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#ifndef HCD_ATTR_ENDPOINT_MAX
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# define HCD_ATTR_ENDPOINT_MAX 8
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#endif
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/*------------------------------------------------------------------
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* MACRO TYPEDEF CONSTANT ENUM DECLARATION
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*------------------------------------------------------------------*/
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#define REQUEST_TYPE_INVALID (0xFFu)
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typedef struct {
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uint_fast16_t beg; /* offset of including first element */
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uint_fast16_t end; /* offset of excluding the last element */
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} free_block_t;
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typedef struct TU_ATTR_PACKED {
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uint8_t TXFUNCADDR;
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uint8_t RESERVED0;
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uint8_t TXHUBADDR;
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uint8_t TXHUBPORT;
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uint8_t RXFUNCADDR;
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uint8_t RESERVED1;
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uint8_t RXHUBADDR;
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uint8_t RXHUBPORT;
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} hw_addr_t;
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typedef struct TU_ATTR_PACKED {
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uint16_t TXMAXP;
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uint8_t TXCSRL;
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uint8_t TXCSRH;
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uint16_t RXMAXP;
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uint8_t RXCSRL;
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uint8_t RXCSRH;
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uint16_t RXCOUNT;
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uint8_t TXTYPE;
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uint8_t TXINTERVAL;
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uint8_t RXTYPE;
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uint8_t RXINTERVAL;
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uint16_t RESERVED;
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} hw_endpoint_t;
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typedef union {
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uint8_t u8;
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uint16_t u16;
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uint32_t u32;
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} hw_fifo_t;
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typedef struct TU_ATTR_PACKED
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{
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void *buf; /* the start address of a transfer data buffer */
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uint16_t length; /* the number of bytes in the buffer */
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uint16_t remaining; /* the number of bytes remaining in the buffer */
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} pipe_state_t;
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typedef struct TU_ATTR_PACKED
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{
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uint8_t dev;
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uint8_t ep;
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} pipe_addr_t;
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typedef struct
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{
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bool need_reset; /* The device has not been reset after connection. */
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uint8_t bmRequestType;
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uint8_t ctl_mps[7]; /* EP0 max packet size for each device */
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pipe_state_t pipe0;
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pipe_state_t pipe[7][2]; /* pipe[pipe number - 1][direction 0:RX 1:TX] */
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pipe_addr_t addr[7][2]; /* addr[pipe number - 1][direction 0:RX 1:TX] */
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} hcd_data_t;
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/*------------------------------------------------------------------
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* INTERNAL OBJECT & FUNCTION DECLARATION
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*------------------------------------------------------------------*/
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static hcd_data_t _hcd;
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static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
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{
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free_block_t *cur = beg;
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for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
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return cur;
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}
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static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
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{
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free_block_t *p = find_containing_block(blks, blks + num, addr);
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TU_ASSERT(p != blks + num, -2);
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if (p->beg == addr) {
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/* Shrink block */
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p->beg = addr + size;
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if (p->beg != p->end) return 0;
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/* remove block */
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free_block_t *end = blks + num;
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while (p + 1 < end) {
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*p = *(p + 1);
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++p;
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}
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return -1;
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} else {
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/* Split into 2 blocks */
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free_block_t tmp = {
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.beg = addr + size,
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.end = p->end
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};
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p->end = addr;
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if (p->beg == p->end) {
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if (tmp.beg != tmp.end) {
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*p = tmp;
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return 0;
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}
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/* remove block */
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free_block_t *end = blks + num;
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while (p + 1 < end) {
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*p = *(p + 1);
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++p;
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}
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return -1;
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}
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if (tmp.beg == tmp.end) return 0;
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blks[num] = tmp;
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return 1;
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}
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}
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static inline unsigned free_block_size(free_block_t const *blk)
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{
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return blk->end - blk->beg;
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}
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static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
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{
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free_block_t free_blocks[2 * (HCD_ATTR_ENDPOINT_MAX - 1)];
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unsigned num_blocks = 1;
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/* Initialize free memory block list */
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free_blocks[0].beg = 64 / 8;
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free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
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for (int i = 1; i < HCD_ATTR_ENDPOINT_MAX; ++i) {
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uint_fast16_t addr;
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int num;
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USB0->EPIDX = i;
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addr = USB0->TXFIFOADD;
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if (addr) {
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unsigned sz = USB0->TXFIFOSZ;
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unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
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num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
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TU_ASSERT(-2 < num, 0);
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num_blocks += num;
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}
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addr = USB0->RXFIFOADD;
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if (addr) {
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unsigned sz = USB0->RXFIFOSZ;
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unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
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num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
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TU_ASSERT(-2 < num, 0);
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num_blocks += num;
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}
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}
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/* Find the best fit memory block */
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uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
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free_block_t const *min = NULL;
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uint_fast16_t min_sz = 0xFFFFu;
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free_block_t const *end = &free_blocks[num_blocks];
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for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
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uint_fast16_t sz = free_block_size(cur);
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if (sz < size_in_8byte_unit) continue;
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if (size_in_8byte_unit == sz) return cur->beg;
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if (sz < min_sz) min = cur;
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}
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TU_ASSERT(min, 0);
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return min->beg;
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}
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static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
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{
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volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
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return regs + epnum_minus1;
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}
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static unsigned find_pipe(uint_fast8_t dev_addr, uint_fast8_t ep_addr)
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{
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unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
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pipe_addr_t const *p = &_hcd.addr[0][dir_tx];
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for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) {
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if ((dev_addr == p->dev) && (ep_addr == p->ep))
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return i + 1;
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}
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return 0;
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}
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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{
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volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
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uintptr_t addr = (uintptr_t)buf;
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while (len >= 4) {
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reg->u32 = *(uint32_t const *)addr;
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addr += 4;
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len -= 4;
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}
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if (len >= 2) {
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reg->u16 = *(uint16_t const *)addr;
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addr += 2;
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len -= 2;
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}
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if (len) {
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reg->u8 = *(uint8_t const *)addr;
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}
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}
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static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
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{
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volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
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uintptr_t addr = (uintptr_t)buf;
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while (len >= 4) {
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*(uint32_t *)addr = reg->u32;
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addr += 4;
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len -= 4;
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}
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if (len >= 2) {
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*(uint32_t *)addr = reg->u16;
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addr += 2;
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len -= 2;
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}
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if (len) {
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*(uint32_t *)addr = reg->u8;
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}
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}
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static bool edpt0_xfer_out(void)
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{
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pipe_state_t *pipe = &_hcd.pipe0;
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unsigned const rem = pipe->remaining;
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if (!rem) {
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pipe->buf = NULL;
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return true;
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}
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unsigned const dev_addr = USB0->TXFUNCADDR0;
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unsigned const mps = _hcd.ctl_mps[dev_addr];
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unsigned const len = TU_MIN(rem, mps);
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void *buf = pipe->buf;
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if (len) {
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pipe_write_packet(buf, &USB0->FIFO0_WORD, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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pipe->remaining = rem - len;
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USB0->CSRL0 = USB_CSRL0_TXRDY;
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return false;
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}
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static bool edpt0_xfer_in(void)
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{
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pipe_state_t *pipe = &_hcd.pipe0;
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unsigned const rem = pipe->remaining;
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unsigned const dev_addr = USB0->TXFUNCADDR0;
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unsigned const mps = _hcd.ctl_mps[dev_addr];
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unsigned const vld = USB0->COUNT0;
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unsigned const len = TU_MIN(TU_MIN(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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pipe_read_packet(buf, &USB0->FIFO0_WORD, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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pipe->remaining = rem - len;
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return true;
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}
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USB0->CSRL0 = USB_CSRL0_REQPKT;
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return false;
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}
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static bool edpt0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
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{
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(void)rhport;
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const unsigned req = _hcd.bmRequestType;
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TU_ASSERT(req != REQUEST_TYPE_INVALID);
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TU_ASSERT(dev_addr < sizeof(_hcd.ctl_mps));
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USB0->TXFUNCADDR0 = dev_addr;
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const unsigned dir_in = tu_edpt_dir(ep_addr);
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if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
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TU_ASSERT(buffer);
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_hcd.pipe0.buf = buffer;
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_hcd.pipe0.length = buflen;
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_hcd.pipe0.remaining = buflen;
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if (dir_in)
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USB0->CSRL0 = USB_CSRL0_REQPKT;
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else
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edpt0_xfer_out();
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} else { /* STATUS stage */
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_hcd.pipe0.buf = NULL;
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_hcd.pipe0.length = 0;
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_hcd.pipe0.remaining = 0;
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USB0->CSRL0 = USB_CSRL0_STATUS | (dir_in ? USB_CSRL0_REQPKT: USB_CSRL0_TXRDY);
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}
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return true;
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}
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static bool pipe_xfer_out(uint_fast8_t pipenum)
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{
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pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1];
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unsigned const rem = pipe->remaining;
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if (!rem) {
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pipe->buf = NULL;
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return true;
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}
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hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
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unsigned const mps = regs->TXMAXP;
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unsigned const len = TU_MIN(rem, mps);
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void *buf = pipe->buf;
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if (len) {
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pipe_write_packet(buf, &USB0->FIFO0_WORD + pipenum, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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pipe->remaining = rem - len;
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regs->TXCSRL = USB_TXCSRL1_TXRDY;
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return false;
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}
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static bool pipe_xfer_in(uint_fast8_t pipenum)
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{
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pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0];
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volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
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TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
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const unsigned mps = regs->RXMAXP;
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const unsigned rem = pipe->remaining;
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const unsigned vld = regs->RXCOUNT;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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pipe_read_packet(buf, &USB0->FIFO0_WORD + pipenum, len);
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pipe->buf = buf + len;
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pipe->remaining = rem - len;
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}
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return NULL != buf;
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}
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regs->RXCSRL = USB_RXCSRL1_REQPKT;
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return false;
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}
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static bool edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
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{
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(void)rhport;
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unsigned const pipenum = find_pipe(dev_addr, ep_addr);
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unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
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pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx];
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pipe->buf = buffer;
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pipe->length = buflen;
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pipe->remaining = buflen;
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if (dir_tx) {
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pipe_xfer_out(pipenum);
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} else {
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volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
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regs->RXCSRL = USB_RXCSRL1_REQPKT;
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}
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return true;
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}
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static void process_ep0(uint8_t rhport)
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{
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(void)rhport;
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uint_fast8_t csrl = USB0->CSRL0;
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// TU_LOG1(" EP0 CSRL = %x\n", csrl);
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unsigned const dev_addr = USB0->TXFUNCADDR0;
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unsigned const req = _hcd.bmRequestType;
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if (csrl & (USB_CSRL0_ERROR | USB_CSRL0_NAKTO | USB_CSRL0_STALLED)) {
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/* No response / NAK timed out / Stall received */
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if (csrl & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY))
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USB0->CSRH0 = USB_CSRH0_FLUSH;
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USB0->CSRL0 = 0;
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_hcd.bmRequestType = REQUEST_TYPE_INVALID;
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uint8_t result = (csrl & USB_CSRL0_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
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if (REQUEST_TYPE_INVALID == req) { /* SETUP */
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uint8_t const ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
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hcd_event_xfer_complete(dev_addr, ep_addr,
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_hcd.pipe0.length - _hcd.pipe0.remaining,
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result, true);
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} else if (csrl & USB_CSRL0_STATUS) { /* STATUS */
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uint8_t const ep_addr = tu_edpt_dir(req) ?
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tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN);
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hcd_event_xfer_complete(dev_addr, ep_addr,
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_hcd.pipe0.length - _hcd.pipe0.remaining,
|
||||
result, true);
|
||||
} else { /* DATA */
|
||||
uint8_t const ep_addr = tu_edpt_dir(req) ?
|
||||
tu_edpt_addr(0, TUSB_DIR_IN): tu_edpt_addr(0, TUSB_DIR_OUT);
|
||||
hcd_event_xfer_complete(dev_addr, ep_addr,
|
||||
_hcd.pipe0.length - _hcd.pipe0.remaining,
|
||||
result, true);
|
||||
}
|
||||
return;
|
||||
}
|
||||
if (csrl & USB_CSRL0_STATUS) {
|
||||
/* STATUS IN */
|
||||
TU_ASSERT(USB_CSRL0_RXRDY == (csrl & USB_CSRL0_RXRDY),);
|
||||
TU_ASSERT(0 == USB0->COUNT0,);
|
||||
USB0->CSRL0 = 0;
|
||||
_hcd.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN),
|
||||
0, XFER_RESULT_SUCCESS, true);
|
||||
return;
|
||||
}
|
||||
if (csrl & USB_CSRL0_RXRDY) {
|
||||
/* DATA IN */
|
||||
TU_ASSERT(REQUEST_TYPE_INVALID != req,);
|
||||
TU_ASSERT(_hcd.pipe0.buf,);
|
||||
if (edpt0_xfer_in()) {
|
||||
hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN),
|
||||
_hcd.pipe0.length - _hcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* When CSRL0 is zero, it means that completion of sending a any length packet. */
|
||||
if (!_hcd.pipe0.buf) {
|
||||
/* STATUS OUT */
|
||||
TU_ASSERT(REQUEST_TYPE_INVALID != req,);
|
||||
_hcd.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
/* EP address is the reverse direction of DATA stage */
|
||||
uint8_t const ep_addr = tu_edpt_dir(req) ?
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN);
|
||||
hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true);
|
||||
return;
|
||||
}
|
||||
if (REQUEST_TYPE_INVALID == req) {
|
||||
/* SETUP */
|
||||
_hcd.bmRequestType = *(uint8_t*)_hcd.pipe0.buf;
|
||||
_hcd.pipe0.buf = NULL;
|
||||
hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
8, XFER_RESULT_SUCCESS, true);
|
||||
return;
|
||||
}
|
||||
|
||||
/* DATA OUT */
|
||||
if (edpt0_xfer_out()) {
|
||||
hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
_hcd.pipe0.length - _hcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum)
|
||||
{
|
||||
(void)rhport;
|
||||
bool completed;
|
||||
uint8_t result;
|
||||
|
||||
volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
|
||||
unsigned const csrl = regs->TXCSRL;
|
||||
// TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl);
|
||||
if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) {
|
||||
if (csrl & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR);
|
||||
completed = true;
|
||||
result = (csrl & USB_TXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
|
||||
} else {
|
||||
completed = pipe_xfer_out(pipenum);
|
||||
result = XFER_RESULT_SUCCESS;
|
||||
}
|
||||
if (completed) {
|
||||
pipe_addr_t *addr = &_hcd.addr[pipenum - 1][1];
|
||||
pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1];
|
||||
hcd_event_xfer_complete(addr->dev, addr->ep,
|
||||
pipe->length - pipe->remaining,
|
||||
result, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
|
||||
{
|
||||
(void)rhport;
|
||||
bool completed;
|
||||
uint8_t result;
|
||||
|
||||
volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
|
||||
unsigned const csrl = regs->RXCSRL;
|
||||
// TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl);
|
||||
if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) {
|
||||
if (csrl & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR);
|
||||
completed = true;
|
||||
result = (csrl & USB_RXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
|
||||
} else {
|
||||
completed = pipe_xfer_in(pipenum);
|
||||
result = XFER_RESULT_SUCCESS;
|
||||
}
|
||||
if (completed) {
|
||||
pipe_addr_t *addr = &_hcd.addr[pipenum - 1][0];
|
||||
pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0];
|
||||
hcd_event_xfer_complete(addr->dev, addr->ep,
|
||||
pipe->length - pipe->remaining,
|
||||
result, true);
|
||||
}
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Host API
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
bool hcd_init(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
|
||||
NVIC_ClearPendingIRQ(USB0_IRQn);
|
||||
_hcd.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
USB0->DEVCTL |= USB_DEVCTL_SESSION;
|
||||
USB0->IE = USB_IE_DISCON | USB_IE_CONN | USB_IE_BABBLE | USB_IE_RESUME;
|
||||
return true;
|
||||
}
|
||||
|
||||
void hcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
void hcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
uint32_t hcd_frame_number(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* The device must be reset at least once after connection
|
||||
* in order to start the frame counter. */
|
||||
if (_hcd.need_reset) hcd_port_reset(rhport);
|
||||
return USB0->FRAME;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Port API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
bool hcd_port_connect_status(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
unsigned devctl = USB0->DEVCTL;
|
||||
if (!(devctl & USB_DEVCTL_HOST)) return false;
|
||||
if (devctl & (USB_DEVCTL_LSDEV | USB_DEVCTL_FSDEV)) return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
void hcd_port_reset(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0->POWER |= USB_POWER_HSENAB | USB_POWER_RESET;
|
||||
unsigned cnt = SystemCoreClock / 1000 * 20;
|
||||
while (cnt--) __NOP();
|
||||
USB0->POWER &= ~USB_POWER_RESET;
|
||||
_hcd.need_reset = false;
|
||||
}
|
||||
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
unsigned devctl = USB0->DEVCTL;
|
||||
if (devctl & USB_DEVCTL_LSDEV) return TUSB_SPEED_LOW;
|
||||
if (!(devctl & USB_DEVCTL_FSDEV)) return TUSB_SPEED_INVALID;
|
||||
if (USB0->POWER & USB_POWER_HSMODE) return TUSB_SPEED_HIGH;
|
||||
return TUSB_SPEED_FULL;
|
||||
}
|
||||
|
||||
void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
if (sizeof(_hcd.ctl_mps) <= dev_addr) return;
|
||||
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
_hcd.ctl_mps[dev_addr] = 0;
|
||||
if (!dev_addr) return;
|
||||
|
||||
pipe_addr_t *p = &_hcd.addr[0][0];
|
||||
for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i) {
|
||||
for (unsigned j = 0; j < 2; ++j, ++p) {
|
||||
if (dev_addr != p->dev) continue;
|
||||
hw_addr_t volatile *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + i + 1;
|
||||
hw_endpoint_t volatile *regs = edpt_regs(i);
|
||||
USB0->EPIDX = i + 1;
|
||||
if (j) {
|
||||
USB0->TXIE &= ~TU_BIT(i + 1);
|
||||
if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
regs->TXMAXP = 0;
|
||||
regs->TXTYPE = 0;
|
||||
regs->TXINTERVAL = 0;
|
||||
fadr->TXFUNCADDR = 0;
|
||||
fadr->TXHUBADDR = 0;
|
||||
fadr->TXHUBPORT = 0;
|
||||
USB0->TXFIFOADD = 0;
|
||||
USB0->TXFIFOSZ = 0;
|
||||
} else {
|
||||
USB0->RXIE &= ~TU_BIT(i + 1);
|
||||
if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
regs->RXMAXP = 0;
|
||||
regs->RXTYPE = 0;
|
||||
regs->RXINTERVAL = 0;
|
||||
fadr->RXFUNCADDR = 0;
|
||||
fadr->RXHUBADDR = 0;
|
||||
fadr->RXHUBPORT = 0;
|
||||
USB0->RXFIFOADD = 0;
|
||||
USB0->RXFIFOSZ = 0;
|
||||
}
|
||||
p->dev = 0;
|
||||
p->ep = 0;
|
||||
pipe_state_t *pipe = &_hcd.pipe[i][j];
|
||||
pipe->buf = NULL;
|
||||
pipe->length = 0;
|
||||
pipe->remaining = 0;
|
||||
}
|
||||
}
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoints API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
|
||||
{
|
||||
(void)rhport;
|
||||
pipe_write_packet((void*)(uintptr_t)setup_packet, &USB0->FIFO0_WORD, 8);
|
||||
_hcd.pipe0.buf = (void*)(uintptr_t)setup_packet;
|
||||
_hcd.pipe0.length = 8;
|
||||
_hcd.pipe0.remaining = 0;
|
||||
_hcd.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
USB0->TXFUNCADDR0 = dev_addr;
|
||||
USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
if (sizeof(_hcd.ctl_mps) <= dev_addr) return false;
|
||||
unsigned const ep_addr = ep_desc->bEndpointAddress;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
if (0 == epn) {
|
||||
_hcd.ctl_mps[dev_addr] = ep_desc->wMaxPacketSize;
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
|
||||
/* Find a free pipe */
|
||||
unsigned pipenum = 0;
|
||||
pipe_addr_t *p = &_hcd.addr[0][dir_tx];
|
||||
for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) {
|
||||
if (0 == p->ep) {
|
||||
p->dev = dev_addr;
|
||||
p->ep = ep_addr;
|
||||
pipenum = i + 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!pipenum) return false;
|
||||
|
||||
unsigned const xfer = ep_desc->bmAttributes.xfer;
|
||||
unsigned const mps = tu_edpt_packet_size(ep_desc);
|
||||
|
||||
pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx];
|
||||
pipe->buf = NULL;
|
||||
pipe->length = 0;
|
||||
pipe->remaining = 0;
|
||||
|
||||
uint8_t pipe_type = 0;
|
||||
switch (hcd_port_speed_get(rhport)) {
|
||||
default: return false;
|
||||
case TUSB_SPEED_LOW: pipe_type |= USB_TXTYPE1_SPEED_LOW; break;
|
||||
case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break;
|
||||
case TUSB_SPEED_HIGH: pipe_type |= USB_TXTYPE1_SPEED_HIGH; break;
|
||||
}
|
||||
switch (xfer) {
|
||||
default: return false;
|
||||
case TUSB_XFER_BULK: pipe_type |= USB_TXTYPE1_PROTO_BULK; break;
|
||||
case TUSB_XFER_INTERRUPT: pipe_type |= USB_TXTYPE1_PROTO_INT; break;
|
||||
case TUSB_XFER_ISOCHRONOUS: pipe_type |= USB_TXTYPE1_PROTO_ISOC; break;
|
||||
}
|
||||
|
||||
hw_addr_t volatile *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + pipenum;
|
||||
hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
|
||||
if (dir_tx) {
|
||||
fadr->TXFUNCADDR = dev_addr;
|
||||
regs->TXMAXP = mps;
|
||||
regs->TXTYPE = pipe_type | epn;
|
||||
regs->TXINTERVAL = ep_desc->bInterval;
|
||||
if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
USB0->TXIE |= TU_BIT(pipenum);
|
||||
} else {
|
||||
fadr->RXFUNCADDR = dev_addr;
|
||||
regs->RXMAXP = mps;
|
||||
regs->RXTYPE = pipe_type | epn;
|
||||
regs->RXINTERVAL = ep_desc->bInterval;
|
||||
if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
USB0->RXIE |= TU_BIT(pipenum);
|
||||
}
|
||||
|
||||
/* Setup FIFO */
|
||||
int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
|
||||
if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
|
||||
unsigned addr = find_free_memory(size_in_log2_minus3);
|
||||
TU_ASSERT(addr);
|
||||
|
||||
USB0->EPIDX = pipenum;
|
||||
if (dir_tx) {
|
||||
USB0->TXFIFOADD = addr;
|
||||
USB0->TXFIFOSZ = size_in_log2_minus3;
|
||||
} else {
|
||||
USB0->RXFIFOADD = addr;
|
||||
USB0->RXFIFOSZ = size_in_log2_minus3;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
|
||||
{
|
||||
(void)rhport;
|
||||
bool ret = false;
|
||||
if (0 == tu_edpt_number(ep_addr)) {
|
||||
ret = edpt0_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
|
||||
} else {
|
||||
ret = edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
// clear stall, data toggle is also reset to DATA0
|
||||
bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
unsigned const pipenum = find_pipe(dev_addr, ep_addr);
|
||||
if (!pipenum) return false;
|
||||
hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
|
||||
unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
|
||||
if (dir_tx)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
return true;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* ISR
|
||||
*-------------------------------------------------------------------*/
|
||||
void hcd_int_handler(uint8_t rhport)
|
||||
{
|
||||
uint_fast8_t is, txis, rxis;
|
||||
|
||||
is = USB0->IS; /* read and clear interrupt status */
|
||||
txis = USB0->TXIS; /* read and clear interrupt status */
|
||||
rxis = USB0->RXIS; /* read and clear interrupt status */
|
||||
// TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
|
||||
|
||||
is &= USB0->IE; /* Clear disabled interrupts */
|
||||
if (is & USB_IS_RESUME) {
|
||||
}
|
||||
if (is & USB_IS_CONN) {
|
||||
_hcd.need_reset = true;
|
||||
hcd_event_device_attach(rhport, true);
|
||||
}
|
||||
if (is & USB_IS_DISCON) {
|
||||
hcd_event_device_remove(rhport, true);
|
||||
}
|
||||
if (is & USB_IS_BABBLE) {
|
||||
}
|
||||
txis &= USB0->TXIE; /* Clear disabled interrupts */
|
||||
if (txis & USB_TXIE_EP0) {
|
||||
process_ep0(rhport);
|
||||
txis &= ~TU_BIT(0);
|
||||
}
|
||||
while (txis) {
|
||||
unsigned const num = __builtin_ctz(txis);
|
||||
process_pipe_tx(rhport, num);
|
||||
txis &= ~TU_BIT(num);
|
||||
}
|
||||
rxis &= USB0->RXIE; /* Clear disabled interrupts */
|
||||
while (rxis) {
|
||||
unsigned const num = __builtin_ctz(rxis);
|
||||
process_pipe_rx(rhport, num);
|
||||
rxis &= ~TU_BIT(num);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue