refractor dcd_controller_reset & hcd_controller_reset to hal_controller_reset

This commit is contained in:
hathach 2013-11-06 12:15:11 +07:00
parent 024858a605
commit b2b53e61fb
9 changed files with 56 additions and 47 deletions

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@ -60,7 +60,7 @@
// CONTROLLER CONFIGURATION
//--------------------------------------------------------------------+
#define TUSB_CFG_CONTROLLER_0_MODE (TUSB_MODE_DEVICE)
#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_NONE)
#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_DEVICE)
//--------------------------------------------------------------------+
// HOST CONFIGURATION
@ -81,7 +81,7 @@
//--------------------------------------------------------------------+
// DEVICE CONFIGURATION
//--------------------------------------------------------------------+
#define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor
#define TUSB_CFG_DEVICE_FULLSPEED 0 // TODO refractor
#define TUSB_CFG_DEVICE_USE_ROM_DRIVER 0

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@ -371,7 +371,7 @@ app_descriptor_configuration_t app_tusb_desc_configuration =
.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
.bEndpointAddress = 0x83,
.bmAttributes = { .xfer = TUSB_XFER_BULK },
.wMaxPacketSize = { .size = 64 /*512*/ },
.wMaxPacketSize = { .size = TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512 },
.bInterval = 1
},
@ -381,7 +381,7 @@ app_descriptor_configuration_t app_tusb_desc_configuration =
.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
.bEndpointAddress = 0x03,
.bmAttributes = { .xfer = TUSB_XFER_BULK },
.wMaxPacketSize = { .size = 64 /*512*/ },
.wMaxPacketSize = { .size = TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512 },
.bInterval = 1
},
#endif

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@ -76,8 +76,8 @@
#define TUSB_CFG_HOST_HID_KEYBOARD 0
#define TUSB_CFG_HOST_HID_MOUSE 0
#define TUSB_CFG_HOST_HID_GENERIC 0
#define TUSB_CFG_HOST_MSC 0
#define TUSB_CFG_HOST_CDC 1
#define TUSB_CFG_HOST_MSC 1
#define TUSB_CFG_HOST_CDC 0
#define TUSB_CFG_HOST_CDC_RNDIS 0
//--------------------------------------------------------------------+

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@ -75,7 +75,6 @@ tusb_error_t dcd_init(void) ATTR_WARN_UNUSED_RESULT;
void dcd_isr(uint8_t coreid);
//------------- Controller API -------------//
tusb_error_t dcd_controller_reset(uint8_t coreid) ATTR_WARN_UNUSED_RESULT;
void dcd_controller_connect(uint8_t coreid);
void dcd_controller_disconnect(uint8_t coreid);
void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);

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@ -166,21 +166,21 @@ ATTR_ALIGNED(2048) dcd_data_t dcd_data TUSB_CFG_ATTR_USBRAM;
//--------------------------------------------------------------------+
// CONTROLLER API
//--------------------------------------------------------------------+
tusb_error_t dcd_controller_reset(uint8_t coreid)
{
volatile uint32_t * p_reg_usbcmd;
p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
// NXP chip powered with non-host mode --> sts bit is not correctly reflected
(*p_reg_usbcmd) |= BIT_(1); // TODO refractor reset controller
// timeout_timer_t timeout;
// timeout_set(&timeout, 2); // should not take longer the time to stop controller
while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
//tusb_error_t dcd_controller_reset(uint8_t coreid)
//{
// volatile uint32_t * p_reg_usbcmd;
//
// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
return TUSB_ERROR_NONE;
}
// p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
//// NXP chip powered with non-host mode --> sts bit is not correctly reflected
// (*p_reg_usbcmd) |= BIT_(1); // TODO refractor reset controller
//
//// timeout_timer_t timeout;
//// timeout_set(&timeout, 2); // should not take longer the time to stop controller
// while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
////
//// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
// return TUSB_ERROR_NONE;
//}
void dcd_controller_connect(uint8_t coreid)
{

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@ -102,8 +102,6 @@ tusb_error_t usbd_init (void)
ASSERT_STATUS ( dcd_init() );
dcd_controller_connect(0); // TODO USB1
return TUSB_ERROR_NONE;
}

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@ -54,9 +54,25 @@ enum {
LPC43XX_USBMODE_VBUS_HIGH = 1
};
static tusb_error_t hal_controller_reset(uint8_t coreid)
{ // TODO timeout expired to prevent trap
volatile uint32_t * p_reg_usbcmd;
p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
// NXP chip powered with non-host mode --> sts bit is not correctly reflected
(*p_reg_usbcmd) |= BIT_(1);
// timeout_timer_t timeout;
// timeout_set(&timeout, 2); // should not take longer the time to stop controller
while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
//
// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
return TUSB_ERROR_NONE;
}
tusb_error_t hal_init(void)
{
//------------- USB0 Clock -------------//
//------------- USB0 -------------//
#if TUSB_CFG_CONTROLLER_0_MODE
CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
@ -65,25 +81,24 @@ tusb_error_t hal_init(void)
LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
// reset controller & set role
hal_controller_reset(0);
#if TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST
hcd_controller_reset(0); // TODO where to place prototype
LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
dcd_controller_reset(0);
LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
#if TUSB_CFG_DEVICE_FULLSPEED // TODO for easy testing
LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
#endif
dcd_controller_connect(0);
#endif
hal_interrupt_enable(0);
#endif
//------------- USB1 Clock, only use on-chip FS PHY -------------//
//------------- USB1 -------------//
#if TUSB_CFG_CONTROLLER_1_MODE
// TODO confirm whether device mode require P2_5 or not
// Host require to config P2_5, TODO confirm whether device mode require P2_5 or not
scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur
/* connect CLK_USB1 to 60 MHz clock */
@ -91,11 +106,11 @@ tusb_error_t hal_init(void)
//LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
hal_controller_reset(1);
#if TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST
hcd_controller_reset(1); // TODO where to place prototype
LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
// dcd_controller_reset(1);
LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
dcd_controller_connect(1);
#endif

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@ -277,19 +277,19 @@ static tusb_error_t hcd_controller_stop(uint8_t hostid)
return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
}
tusb_error_t hcd_controller_reset(uint8_t hostid)
{
ehci_registers_t* const regs = get_operational_register(hostid);
timeout_timer_t timeout;
// NXP chip powered with non-host mode --> sts bit is not correctly reflected
regs->usb_cmd_bit.reset = 1;
timeout_set(&timeout, 2); // should not take longer the time to stop controller
while( regs->usb_cmd_bit.reset && !timeout_expired(&timeout)) {}
return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
}
//tusb_error_t hcd_controller_reset(uint8_t hostid)
//{
// ehci_registers_t* const regs = get_operational_register(hostid);
// timeout_timer_t timeout;
//
//// NXP chip powered with non-host mode --> sts bit is not correctly reflected
// regs->usb_cmd_bit.reset = 1;
//
// timeout_set(&timeout, 2); // should not take longer the time to stop controller
// while( regs->usb_cmd_bit.reset && !timeout_expired(&timeout)) {}
//
// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
//}
//--------------------------------------------------------------------+
// CONTROL PIPE API

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@ -469,9 +469,6 @@ typedef struct {
}device[TUSB_CFG_HOST_DEVICE_MAX];
}ehci_data_t;
//For NXP's MCU, host/device mode must be set immediately after a reset
tusb_error_t hcd_controller_reset(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
#ifdef __cplusplus
}
#endif