use lpcopen for lpc43x, work well
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hathach
parent
29416a5c1a
commit
9fec39d893
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@ -41,8 +41,6 @@
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#include "bsp/board.h"
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#include "pca9532.h"
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#include "tusb.h"
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#define BOARD_UART_PORT LPC_USART0
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#define BOARD_UART_PIN_PORT 0x0f
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#define BOARD_UART_PIN_TX 10 // PF.10 : UART0_TXD
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@ -97,16 +95,7 @@ const uint32_t OscRateIn = 12000000;
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static const PINMUX_GRP_T pinmuxing[] =
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{
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/* RMII pin group */
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{0x1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)}, //ENET_REF_CLK
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{0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, //ENET_TXEN
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{0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD0
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{0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD1
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{0x1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDIO
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{0xC, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDC
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{0x1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)}, //ENET_RX_DV
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{0x1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_RXD0
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{0x0, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, //ENET_RXD1
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// USB
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/* I2S */
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{0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)}, //I2S0_TX_CLK
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@ -181,16 +170,15 @@ void board_init(void)
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UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
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#endif
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#if 0
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//------------- USB -------------//
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// USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
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scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7); // USB0 VBus Power
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// USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
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Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
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#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
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scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
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GPIO_SetDir(5, BIT_(18), 1);
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// P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
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Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
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Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
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#endif
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#endif
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// USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
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// TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
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@ -50,9 +50,7 @@
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#include "device/dcd.h"
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#include "dcd_lpc43xx.h"
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#include "LPC43xx.h"
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#include "lpc43xx_cgu.h"
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#include "chip.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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@ -74,7 +72,7 @@ CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
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#endif
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static LPC_USB0_Type * const LPC_USB[2] = { LPC_USB0, ((LPC_USB0_Type*) LPC_USB1_BASE) };
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static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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static dcd_data_t* const dcd_data_ptr[2] =
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{
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@ -112,19 +110,18 @@ void dcd_set_config(uint8_t rhport, uint8_t config_num)
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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lpc_usb->ENDPTCTRL1 = lpc_usb->ENDPTCTRL2 = lpc_usb->ENDPTCTRL3 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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// USB1 only has 3 non-control endpoints
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if ( rhport == 0)
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// USB0 has 5 but USB1 only has 3 non-control endpoints
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for( int i=1; i < (rhport ? 6 : 4); i++)
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{
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lpc_usb->ENDPTCTRL4 = lpc_usb->ENDPTCTRL5 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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//------------- Clear All Registers -------------//
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@ -156,7 +153,7 @@ static void bus_reset(uint8_t rhport)
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bool dcd_init(uint8_t rhport)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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tu_memclr(p_dcd, sizeof(dcd_data_t));
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@ -203,7 +200,7 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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static inline volatile uint32_t * get_endpt_ctrl_reg(uint8_t rhport, uint8_t ep_idx)
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{
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return &(LPC_USB[rhport]->ENDPTCTRL0) + ep_idx/2;
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return &(LPC_USB[rhport]->ENDPTCTRL[0]) + ep_idx/2;
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}
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//--------------------------------------------------------------------+
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@ -321,7 +318,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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//--------------------------------------------------------------------+
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void hal_dcd_isr(uint8_t rhport)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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uint32_t const int_enable = lpc_usb->USBINTR_D;
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uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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@ -80,14 +80,9 @@ static void hal_controller_reset(uint8_t rhport)
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bool tusb_hal_init(void)
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{
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LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
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//------------- USB0 -------------//
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// USB0
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#if CFG_TUSB_RHPORT0_MODE
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CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
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TU_VERIFY( CGU_ERROR_SUCCESS == CGU_SetPLL0()); /* the usb core require output clock = 480MHz */
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CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
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CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); /* Enable PLL after all setting is done */
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Chip_USB0_Init();
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// reset controller & set role
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hal_controller_reset(0);
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@ -103,14 +98,9 @@ bool tusb_hal_init(void)
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#endif
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#endif
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//------------- USB1 -------------//
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// USB1
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#if CFG_TUSB_RHPORT1_MODE
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// Host require to config P2_5, TODO confirm whether device mode require P2_5 or not
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scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur
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/* connect CLK_USB1 to 60 MHz clock */
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CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */
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LPC_SCU->SFSUSB = (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
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Chip_USB1_Init();
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hal_controller_reset(1);
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