update lpc13u cmsis to 3.20
This commit is contained in:
hathach
parent
fa332a6150
commit
9776fb6d1a
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@ -30,7 +30,7 @@
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@ -42,7 +42,7 @@
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@ -55,7 +55,7 @@
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@ -63,7 +63,7 @@
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@ -121,7 +121,7 @@
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@ -147,7 +147,7 @@
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@ -155,7 +155,7 @@
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@ -212,7 +212,7 @@
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@ -239,7 +239,7 @@
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@ -307,7 +307,7 @@
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@ -332,7 +332,7 @@
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|
||||
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.985680963" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
|
||||
<option id="com.crt.advproject.gas.arch.614488739" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm0" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gas.arch.614488739" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gas.thumb.1110106343" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
|
||||
<option id="gnu.both.asm.option.flags.crt.1384228154" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
|
||||
<option id="com.crt.advproject.gas.fpu.620068352" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
</tool>
|
||||
<tool id="com.crt.advproject.link.cpp.exe.debug.738370064" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
|
||||
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.357593495" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
|
||||
<option id="com.crt.advproject.link.arch.1578855812" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm0" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.link.arch.1578855812" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.link.thumb.1249648720" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
|
||||
<option id="com.crt.advproject.link.script.1933263022" name="Linker script" superClass="com.crt.advproject.link.script" value=""device_os_none_Board_LPCLink2.ld"" valueType="string"/>
|
||||
<option id="com.crt.advproject.link.manage.1871988533" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
|
||||
|
|
@ -493,7 +493,7 @@
|
|||
<builder buildPath="${workspace_loc:/device_keyboard/Debug}" enableAutoBuild="false" enabledIncrementalBuild="true" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1213948863" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
|
||||
<tool id="com.crt.advproject.cpp.exe.debug.1215673371" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
|
||||
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.265056823" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
|
||||
<option id="com.crt.advproject.gcc.arch.1066934712" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm0" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gcc.arch.1066934712" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gcc.thumb.1913988235" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols.752273048" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="__REDLIB__"/>
|
||||
|
|
@ -520,7 +520,7 @@
|
|||
<inputType id="com.crt.advproject.compiler.input.503300094" superClass="com.crt.advproject.compiler.input"/>
|
||||
</tool>
|
||||
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.1959731457" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
|
||||
<option id="com.crt.advproject.gas.arch.1912407389" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm0" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gas.arch.1912407389" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.gas.thumb.860719262" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
|
||||
<option id="gnu.both.asm.option.flags.crt.669705632" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
|
||||
<option id="com.crt.advproject.gas.fpu.886955384" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
|
||||
|
|
@ -529,7 +529,7 @@
|
|||
</tool>
|
||||
<tool id="com.crt.advproject.link.cpp.exe.debug.1046410367" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
|
||||
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.971343908" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
|
||||
<option id="com.crt.advproject.link.arch.2038369756" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm0" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.link.arch.2038369756" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
|
||||
<option id="com.crt.advproject.link.thumb.712014632" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
|
||||
<option id="com.crt.advproject.link.script.178100429" name="Linker script" superClass="com.crt.advproject.link.script" value=""device_os_none_Board_NGX4330.ld"" valueType="string"/>
|
||||
<option id="com.crt.advproject.link.manage.171795197" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
|
||||
|
|
@ -568,45 +568,49 @@
|
|||
<storageModule moduleId="com.crt.config">
|
||||
<projectStorage><?xml version="1.0" encoding="UTF-8"?>
|
||||
<TargetConfig>
|
||||
<Properties property_0="" property_3="NXP" property_4="LPC11U37/401" property_count="5" version="1"/>
|
||||
<infoList vendor="NXP"><info chip="LPC11U37/401" match_id="0x00017C40" name="LPC11U37/401" stub="crt_emu_lpc11_13_nxp"><chip><name>LPC11U37/401</name>
|
||||
<family>LPC11Uxx</family>
|
||||
<Properties property_0="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/>
|
||||
<infoList vendor="NXP"><info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"><chip><name>LPC1347</name>
|
||||
<family>LPC13xx (12bit ADC)</family>
|
||||
<vendor>NXP (formerly Philips)</vendor>
|
||||
<reset board="None" core="Real" sys="Real"/>
|
||||
<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
|
||||
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
|
||||
<memory id="RAM" type="RAM"/>
|
||||
<memory id="Periph" is_volatile="true" type="Peripheral"/>
|
||||
<memoryInstance derived_from="Flash" id="MFlash128" location="0x0" size="0x20000"/>
|
||||
<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/>
|
||||
<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x20000"/>
|
||||
<peripheralInstance derived_from="CM0_NVIC" id="NVIC" location="0xe000e000"/>
|
||||
<peripheralInstance derived_from="LPC11U_GPIO" id="GPIO" location="0x50000000"/>
|
||||
<peripheralInstance derived_from="LPC11U_USBDEV" id="USB" location="0x40080000"/>
|
||||
<peripheralInstance derived_from="CM0_DCR" id="DCR" location="0xe000edf0"/>
|
||||
<peripheralInstance derived_from="LPC11U_GPIO_GROUP_INT" id="GPIOGROUP0INT" location="0x40060000"/>
|
||||
<peripheralInstance derived_from="LPC11U_GPIO_GROUP_INT" id="GPIOGROUP1INT" location="0x4005c000"/>
|
||||
<peripheralInstance derived_from="LPC11U_GPIO_INT" id="GPIOINT" location="0x4004c000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_SSP" id="SSP1" location="0x40058000"/>
|
||||
<peripheralInstance derived_from="LPC11U_FMC" id="FMC" location="0x4003c000"/>
|
||||
<peripheralInstance derived_from="LPC11U_SYSCTL" id="SYSCTL" location="0x40048000"/>
|
||||
<peripheralInstance derived_from="LPC11U_IOCON" id="IOCON" location="0x40044000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_SSP" id="SSP0" location="0x40040000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_PMU" id="PMU" location="0x40038000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_ADC" id="ADC" location="0x4001c000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_TIMER32" id="TIMER1" location="0x40018000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_TIMER32" id="TIMER0" location="0x40014000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_TIMER16" id="TMR161" location="0x40010000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_TIMER16" id="TMR160" location="0x4000c000"/>
|
||||
<peripheralInstance derived_from="LPC1xxx_UART_MODEM" id="UART0" location="0x40008000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_WDT" id="WDT" location="0x40004000"/>
|
||||
<peripheralInstance derived_from="LPC11_13_I2C" id="I2C0" location="0x40000000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/>
|
||||
<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
|
||||
<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
|
||||
<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
|
||||
<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
|
||||
<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
|
||||
<peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/>
|
||||
<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/>
|
||||
<peripheralInstance derived_from="USART" id="USART" location="0x40008000"/>
|
||||
<peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/>
|
||||
<peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/>
|
||||
<peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/>
|
||||
<peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/>
|
||||
<peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/>
|
||||
<peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/>
|
||||
<peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/>
|
||||
<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/>
|
||||
<peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/>
|
||||
<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/>
|
||||
<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/>
|
||||
<peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/>
|
||||
<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/>
|
||||
<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/>
|
||||
<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x40064000"/>
|
||||
<peripheralInstance derived_from="USB" id="USB" location="0x40080000"/>
|
||||
<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/>
|
||||
</chip>
|
||||
<processor><name gcc_name="cortex-m0">Cortex-M0</name>
|
||||
<processor><name gcc_name="cortex-m3">Cortex-M3</name>
|
||||
<family>Cortex-M</family>
|
||||
</processor>
|
||||
<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/>
|
||||
<link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/>
|
||||
</info>
|
||||
</infoList>
|
||||
</TargetConfig></projectStorage>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
History of updates to CMSIS_CORE_LPC13Uxx
|
||||
===========================================
|
||||
|
||||
18 July 2013
|
||||
------------
|
||||
CMSIS library project using ARM Cortex-M0 CMSIS files as
|
||||
supplied in ARM's CMSIS 3.20 March 2013 release, together
|
||||
with NXP's device specific files taken from old
|
||||
CMSISv2p10_LPC13Uxx project.
|
||||
|
||||
Note files are built -Os for both Debug and Release
|
||||
|
||||
|
||||
History of updates to CMSISv2p10_LPC13Uxx
|
||||
=========================================
|
||||
|
||||
17 February 2012
|
||||
----------------
|
||||
|
||||
CMSIS 2.1 library project using ARM Cortex-M3 CMSIS
|
||||
files as supplied in ARM's CMSIS 2.1 July 2011 release,
|
||||
together with device/board specific files from NXP for
|
||||
LPC1300 (12bit ADC) parts (ie LPC1315/16/17/45/46/47).
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,64 +1,64 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_LPC13Uxx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC13Uxx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13Uxx_H
|
||||
#define __SYSTEM_LPC13Uxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13Uxx_H */
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC13Uxx.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC13Uxx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13Uxx_H
|
||||
#define __SYSTEM_LPC13Uxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13Uxx_H */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
<!-- liblinks.xml
|
||||
|
||||
LPCXpresso "Smart update wizard" script file
|
||||
When executed on a particular application project, will
|
||||
add appropriate links to the specified library project.
|
||||
|
||||
Note that this script assumes that the application project
|
||||
contains the standard 'Debug' and 'Release' build
|
||||
configurations.
|
||||
-->
|
||||
|
||||
<project name="" update="true">
|
||||
<setting id="all.compiler.inc">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/inc}</value>
|
||||
</setting>
|
||||
<setting id="all.compiler.def">
|
||||
<value>__USE_CMSIS=CMSIS_CORE_LPC13Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.libs">
|
||||
<value>CMSIS_CORE_LPC13Uxx</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Debug">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Debug}</value>
|
||||
</setting>
|
||||
<setting id="linker.paths" buildType="Release">
|
||||
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Release}</value>
|
||||
</setting>
|
||||
<requires msg="Library project `CMSIS_CORE_LPC13Uxx` not found">
|
||||
<value>CMSIS_CORE_LPC13Uxx</value>
|
||||
</requires>
|
||||
</project>
|
||||
|
||||
|
|
@ -1,437 +1,437 @@
|
|||
/******************************************************************************
|
||||
* @file system_LPC13Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
/******************************************************************************
|
||||
* @file system_LPC13Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue