Update midi_test endpoints and FT9xx code
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@ -83,9 +83,15 @@ enum
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#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
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#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
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// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
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// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
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// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
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// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
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#define EPNUM_MIDI 0x02
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#define EPNUM_MIDI_OUT 0x02
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#define EPNUM_MIDI_IN 0x02
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#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
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// On Bridgetek FT9xx endpoint numbers must be unique...
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#define EPNUM_MIDI_OUT 0x02
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#define EPNUM_MIDI_IN 0x03
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#else
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#else
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#define EPNUM_MIDI 0x01
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#define EPNUM_MIDI_OUT 0x01
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#define EPNUM_MIDI_IN 0x01
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#endif
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#endif
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uint8_t const desc_fs_configuration[] =
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uint8_t const desc_fs_configuration[] =
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@ -94,7 +100,7 @@ uint8_t const desc_fs_configuration[] =
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TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
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TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
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// Interface number, string index, EP Out & EP In address, EP size
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// Interface number, string index, EP Out & EP In address, EP size
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TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 64)
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TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 64)
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};
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};
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#if TUD_OPT_HIGH_SPEED
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#if TUD_OPT_HIGH_SPEED
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@ -104,7 +110,7 @@ uint8_t const desc_hs_configuration[] =
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TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
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TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
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// Interface number, string index, EP Out & EP In address, EP size
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// Interface number, string index, EP Out & EP In address, EP size
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TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 512)
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TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 512)
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};
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};
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#endif
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#endif
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@ -56,10 +56,10 @@ static uint8_t _ft90x_setup_packet[8];
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struct ft90x_xfer_state
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struct ft90x_xfer_state
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{
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{
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uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
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volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
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int16_t total_size; // Total transfer size in bytes for this transfer.
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volatile int16_t total_size; // Total transfer size in bytes for this transfer.
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int16_t remain_size; // Total remaining in transfer.
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volatile int16_t remain_size; // Total remaining in transfer.
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uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
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volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
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uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
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uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
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uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
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uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
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@ -131,6 +131,7 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
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uint8_t end = 0;
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uint8_t end = 0;
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uint16_t ep_size = ep_xfer[ep_number].size;
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uint16_t ep_size = ep_xfer[ep_number].size;
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(void)ep_size;
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(void)ep_size;
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if ((xfer_bytes == 0) || (xfer_bytes < ep_size))
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if ((xfer_bytes == 0) || (xfer_bytes < ep_size))
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{
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{
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end = 1;
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end = 1;
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@ -186,39 +187,21 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
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return xfer_bytes;
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return xfer_bytes;
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}
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}
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// Reset all endpoints to a default state.
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// Reset all non-control endpoints to a default state.
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// Control endpoint enabled and ready. All others disabled.
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// Control endpoint is always enabled and ready. All others disabled.
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static void _ft90x_reset_edpts(void)
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static void _ft90x_reset_edpts(void)
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{
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{
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// Disable all endpoints and remove configuration values.
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// Disable all endpoints and remove configuration values.
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// Clear settings.
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for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
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tu_memclr(ep_xfer, sizeof(ep_xfer));
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for (int i = 0; i < USBD_MAX_ENDPOINT_COUNT; i++)
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{
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{
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// Clear settings.
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tu_memclr(&ep_xfer[i], sizeof(struct ft90x_xfer_state));
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// Disable hardware.
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// Disable hardware.
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USBD_EP_CR_REG(i) = 0;
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USBD_EP_CR_REG(i) = 0;
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}
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}
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// Setup the control endpoint only.
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#if CFG_TUD_ENDPOINT0_SIZE == 64
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 32
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_32 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 16
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_16 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 8
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_8 << BIT_USBD_EP0_MAX_SIZE);
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#else
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#error "CFG_TUD_ENDPOINT0_SIZE must be defined with a value of 8, 16, 32 or 64."
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#endif
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// Configure the control endpoint.
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ep_xfer[USBD_EP_0].size = CFG_TUD_ENDPOINT0_SIZE;
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ep_xfer[USBD_EP_0].type = TUSB_XFER_CONTROL;
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// Enable interrupts from USB device control.
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// Enable interrupts from USB device control.
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USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
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USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
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// Enable interrupts on EP0.
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USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
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}
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}
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// Enable or disable the USB PHY.
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// Enable or disable the USB PHY.
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@ -297,12 +280,13 @@ static void _dcd_ft90x_detach(void)
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SYS->MSC0CFG = SYS->MSC0CFG & (~MASK_SYS_MSC0CFG_USB_VBUS_EN);
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SYS->MSC0CFG = SYS->MSC0CFG & (~MASK_SYS_MSC0CFG_USB_VBUS_EN);
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#endif
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#endif
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CRITICAL_SECTION_BEGIN
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CRITICAL_SECTION_BEGIN
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// Disable interrupts from USB.
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USBD_REG(epie) = 0;
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USBD_REG(epie) = 0;
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USBD_REG(cmie) = 0;
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USBD_REG(cmie) = 0;
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// Turn off the device enable bit.
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USBD_REG(fctrl) = 0;
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CRITICAL_SECTION_END;
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CRITICAL_SECTION_END;
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// Disable the USB function.
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USBD_REG(fctrl) = 0;
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delayms(1);
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delayms(1);
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// Disable USB PHY
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// Disable USB PHY
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@ -628,8 +612,28 @@ void dcd_connect(uint8_t rhport)
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// Determine bus speed and signal speed to tusb.
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// Determine bus speed and signal speed to tusb.
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_ft90x_usb_speed();
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_ft90x_usb_speed();
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}
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}
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// Setup the control endpoint only.
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#if CFG_TUD_ENDPOINT0_SIZE == 64
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 32
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_32 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 16
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_16 << BIT_USBD_EP0_MAX_SIZE);
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#elif CFG_TUD_ENDPOINT0_SIZE == 8
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USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_8 << BIT_USBD_EP0_MAX_SIZE);
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#else
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#error "CFG_TUD_ENDPOINT0_SIZE must be defined with a value of 8, 16, 32 or 64."
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#endif
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CRITICAL_SECTION_END;
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CRITICAL_SECTION_END;
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// Configure the control endpoint.
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ep_xfer[USBD_EP_0].size = CFG_TUD_ENDPOINT0_SIZE;
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ep_xfer[USBD_EP_0].type = TUSB_XFER_CONTROL;
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// Enable interrupts on EP0.
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USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
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// Restore default endpoint state.
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// Restore default endpoint state.
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_ft90x_reset_edpts();
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_ft90x_reset_edpts();
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}
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}
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