lpc55 better multiport support
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hathach
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8642c2045c
commit
8bed369c7f
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@ -56,6 +56,19 @@
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#include "device/dcd.h"
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// only SRAM1 & USB RAM can be used for transfer.
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// Used to set DATABUFSTART which is 22-bit aligned
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// 2000 0000 to 203F FFFF
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#define SRAM_REGION 0x20000000
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// Absolute max of endpoints pairs for all port
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// - 11 13 15 51 54 has 5x2 endpoints
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// - 55 usb0 (FS) has 5x2 endpoints, usb1 (HS) has 6x2 endpoints
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#define MAX_EP_PAIRS 6
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//--------------------------------------------------------------------+
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// IP3511 Registers
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//--------------------------------------------------------------------+
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typedef struct {
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__IO uint32_t DEVCMDSTAT; // Device Command/Status register, offset: 0x0
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@ -73,45 +86,6 @@ typedef struct {
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__I uint32_t EPTOGGLE; // Endpoint toggle register, offset: 0x34
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} dcd_registers_t;
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_controller_t;
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// Number of endpoints
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// - 11 13 15 51 54 has 5x2 endpoints
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// - 55 usb0 (FS) has 5x2 endpoints, usb1 (HS) has 6x2 endpoints
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#define EP_COUNT 10
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#ifdef INCLUDE_FSL_DEVICE_REGISTERS
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) USB0_BASE , .irqnum = USB0_IRQn, .ep_count = FSL_FEATURE_USB_EP_NUM },
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#if FSL_FEATURE_SOC_USBHSD_COUNT
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{ .regs = (dcd_registers_t*) USBHSD_BASE, .irqnum = USB1_IRQn, .ep_count = FSL_FEATURE_USBHSD_EP_NUM }
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#endif
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};
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#else
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 5 },
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};
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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// only SRAM1 & USB RAM can be used for transfer.
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// Used to set DATABUFSTART which is 22-bit aligned
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// 2000 0000 to 203F FFFF
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#define SRAM_REGION 0x20000000
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/* Although device controller are the same. Somehow only LPC134x can execute
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* DMA with 1023 bytes for Bulk/Control. Others (11u, 51u, 54xxx) can only work
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* with max 64 bytes
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@ -141,6 +115,10 @@ enum {
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CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
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};
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//--------------------------------------------------------------------+
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// Endpoint Command/Status List
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//--------------------------------------------------------------------+
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typedef struct TU_ATTR_PACKED
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{
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// Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
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@ -171,20 +149,47 @@ typedef struct
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{
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// 256 byte aligned, 2 for double buffer (not used)
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// Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
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ep_cmd_sts_t ep[EP_COUNT][2];
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xfer_dma_t dma[EP_COUNT];
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ep_cmd_sts_t ep[2*MAX_EP_PAIRS][2];
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xfer_dma_t dma[2*MAX_EP_PAIRS];
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TU_ATTR_ALIGNED(64) uint8_t setup_packet[8];
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}dcd_data_t;
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// EP list must be 256-byte aligned
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
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//--------------------------------------------------------------------+
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// Multiple Controllers
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//--------------------------------------------------------------------+
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_pairs; // Max bi-directional Endpoints
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}dcd_controller_t;
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#ifdef INCLUDE_FSL_DEVICE_REGISTERS
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) USB0_BASE , .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM },
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#if FSL_FEATURE_SOC_USBHSD_COUNT
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{ .regs = (dcd_registers_t*) USBHSD_BASE, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
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#endif
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};
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#else
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_pairs = 5 },
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};
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#endif
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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// EP list must be 256-byte aligned
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
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static inline uint16_t get_buf_offset(void const * buffer)
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{
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uint32_t addr = (uint32_t) buffer;
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@ -212,19 +217,17 @@ void dcd_init(uint8_t rhport)
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dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
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CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
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NVIC_ClearPendingIRQ(USB0_IRQn);
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NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_enable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ(USB0_IRQn);
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(USB0_IRQn);
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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@ -334,7 +337,7 @@ static void bus_reset(uint8_t rhport)
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tu_memclr(&_dcd, sizeof(dcd_data_t));
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// disable all non-control endpoints on bus reset
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for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
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for(uint8_t ep_id = 2; ep_id < 2*MAX_EP_PAIRS; ep_id++)
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{
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_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
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}
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@ -352,9 +355,11 @@ static void bus_reset(uint8_t rhport)
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dcd_reg->INTEN = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
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}
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static void process_xfer_isr(uint32_t int_status)
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static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
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{
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for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
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uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
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for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
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{
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if ( tu_bit_test(int_status, ep_id) )
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{
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@ -373,10 +378,10 @@ static void process_xfer_isr(uint32_t int_status)
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{
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xfer_dma->total_bytes = xfer_dma->xferred_bytes;
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uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
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uint8_t const ep_addr = tu_edpt_addr(ep_id / 2, ep_id & 0x01);
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// TODO no way determine if the transfer is failed or not
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dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(rhport, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
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}
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}
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}
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@ -400,7 +405,7 @@ void dcd_int_handler(uint8_t rhport)
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if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
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{
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bus_reset(rhport);
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dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
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dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
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}
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if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
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@ -409,7 +414,7 @@ void dcd_int_handler(uint8_t rhport)
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if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
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{
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// debouncing as this can be set when device is powering
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dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
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dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
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}
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}
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@ -421,13 +426,13 @@ void dcd_int_handler(uint8_t rhport)
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
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{
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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}
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}
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}
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// else
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// { // resume signal
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// dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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// dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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// }
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// }
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}
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@ -441,7 +446,7 @@ void dcd_int_handler(uint8_t rhport)
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dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
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dcd_event_setup_received(0, _dcd.setup_packet, true);
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dcd_event_setup_received(rhport, _dcd.setup_packet, true);
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// keep waiting for next setup
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_dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
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@ -451,7 +456,7 @@ void dcd_int_handler(uint8_t rhport)
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}
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// Endpoint transfer complete interrupt
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process_xfer_isr(int_status);
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process_xfer_isr(rhport, int_status);
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}
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#endif
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