refactor dcd_lpc18_43, making it capatible with rt10xx
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hathach
parent
623b16af2e
commit
8aacd1eacd
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@ -40,12 +40,61 @@
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#include "fsl_device_registers.h"
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#else
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#include "chip.h"
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// Register base to CAPLENGTH
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#define DCD_REGS_BASE { (dcd_registers_t*) (LPC_USB0_BASE + 0x100), (dcd_registers_t*) (LPC_USB1_BASE + 0x100) }
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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// Device Register starting with CAPLENGTH offset
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typedef struct
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{
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t;
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/*---------- ENDPTCTRL ----------*/
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enum {
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ENDPTCTRL_MASK_STALL = TU_BIT(0),
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@ -153,7 +202,8 @@ typedef struct {
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}dcd_data_t;
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static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
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static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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//static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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static dcd_registers_t* dcd_regs[] = DCD_REGS_BASE;
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//--------------------------------------------------------------------+
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// CONTROLLER API
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@ -162,7 +212,7 @@ static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
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dcd_registers_t* lpc_usb = dcd_regs[rhport];
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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@ -179,7 +229,7 @@ static void bus_reset(uint8_t rhport)
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//------------- Clear All Registers -------------//
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lpc_usb->ENDPTNAK = lpc_usb->ENDPTNAK;
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lpc_usb->ENDPTNAKEN = 0;
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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lpc_usb->USBSTS = lpc_usb->USBSTS;
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
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lpc_usb->ENDPTCOMPLETE = lpc_usb->ENDPTCOMPLETE;
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@ -202,16 +252,16 @@ static void bus_reset(uint8_t rhport)
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void dcd_init(uint8_t rhport)
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{
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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dcd_registers_t* const lpc_usb = dcd_regs[rhport];
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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lpc_usb->ENDPOINTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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lpc_usb->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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lpc_usb->USBSTS = lpc_usb->USBSTS;
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lpc_usb->USBINTR = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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lpc_usb->USBCMD_D |= TU_BIT(0); // connect
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lpc_usb->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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lpc_usb->USBCMD |= TU_BIT(0); // connect
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}
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void dcd_int_enable(uint8_t rhport)
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@ -229,7 +279,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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dcd_regs[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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@ -279,7 +329,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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@ -288,8 +338,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// data toggle also need to be reset
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_regs[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -313,7 +363,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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// Enable EP Control
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LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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@ -328,7 +378,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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{
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while(LPC_USB[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
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while(dcd_regs[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
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}
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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@ -340,7 +390,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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// start transfer
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LPC_USB[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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dcd_regs[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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return true;
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}
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@ -350,11 +400,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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//--------------------------------------------------------------------+
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void dcd_isr(uint8_t rhport)
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{
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LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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dcd_registers_t* const lpc_usb = dcd_regs[rhport];
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uint32_t const int_enable = lpc_usb->USBINTR_D;
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uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
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uint32_t const int_enable = lpc_usb->USBINTR;
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uint32_t const int_status = lpc_usb->USBSTS & int_enable;
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lpc_usb->USBSTS = int_status; // Acknowledge handled interrupt
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if (int_status == 0) return;// disabled interrupt sources
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@ -367,7 +417,7 @@ void dcd_isr(uint8_t rhport)
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if (int_status & INT_MASK_SUSPEND)
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{
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if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
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if (lpc_usb->PORTSC1 & PORTSC_SUSPEND_MASK)
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{
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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@ -380,7 +430,7 @@ void dcd_isr(uint8_t rhport)
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// TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INT_MASK_PORT_CHANGE)
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// {
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// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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// if ( !(lpc_usb->PORTSC1 & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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// {
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// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
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// dcd_event_handler(&event, true);
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