freertos semaphore post issue with control transfer

configAssert misunderstand _control_sem as mutex !!!!
This commit is contained in:
hathach 2018-03-30 18:36:04 +07:00
parent d13160c4ae
commit 8516ca27a1
3 changed files with 20 additions and 19 deletions

View File

@ -52,7 +52,7 @@ enum
{
OSAL_TIMEOUT_NOTIMEOUT = 0, // for use within ISR, return immediately
OSAL_TIMEOUT_NORMAL = 10*5, // default is 10 msec, FIXME [CMSIS-RTX] easily timeout with 10 msec
OSAL_TIMEOUT_WAIT_FOREVER = 0xFFFFFFFF
OSAL_TIMEOUT_WAIT_FOREVER = 0xFFFFFFFFUL
};
#ifdef __cplusplus

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@ -63,9 +63,8 @@
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
typedef struct {
dcd_qhd_t qhd[DCD_QHD_MAX]; ///< Must be at 2K alignment
dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
}dcd_data_t;
extern ATTR_WEAK dcd_data_t dcd_data0;
@ -461,24 +460,22 @@ void hal_dcd_isr(uint8_t rhport)
dcd_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request);
}
//------------- Control Request Completed -------------//
else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
{
for(uint8_t ep_idx = 0; ep_idx < 2; ep_idx++)
// determine Control OUT or IN
uint8_t ep_idx = BIT_TEST_(edpt_complete, 0) ? 0 : 1;
// TODO use the actual QTD instead of the qhd's overlay to get expected bytes for actual byte xferred
dcd_qtd_t* const p_qtd = (dcd_qtd_t*) p_dcd->qhd[ep_idx].qtd_addr;
if ( p_qtd->int_on_complete )
{
if ( BIT_TEST_(edpt_complete, edpt_phy2pos(ep_idx)) )
{
// TODO use the actual QTD instead of the qhd's overlay to get expected bytes for actual byte xferred
dcd_qtd_t volatile * const p_qtd = &p_dcd->qhd[ep_idx].qtd_overlay;
bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
(void) succeeded;
if ( p_qtd->int_on_complete )
{
bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
(void) succeeded;
dcd_control_complete(rhport);
}
}
dcd_control_complete(rhport);
}
}

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@ -43,6 +43,8 @@
#ifndef _TUSB_DCD_LPC43XX_H_
#define _TUSB_DCD_LPC43XX_H_
#include "common/tusb_common.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -92,7 +94,8 @@ enum {
};
typedef struct {
typedef struct
{
// Word 0: Next QTD Pointer
uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
@ -121,7 +124,8 @@ typedef struct {
VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
typedef struct ATTR_ALIGNED(64) {
typedef struct
{
// Word 0: Capabilities and Characteristics
uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
@ -147,7 +151,7 @@ typedef struct ATTR_ALIGNED(64) {
volatile uint8_t list_qtd_idx[DCD_QTD_PER_QHD_MAX];
uint8_t reserved[16-DCD_QTD_PER_QHD_MAX];
} dcd_qhd_t;
} dcd_qhd_t;
VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");