fix clear stall usage, fix reset data toggle with dcd_clear_stall for nrf52

This commit is contained in:
hathach 2019-05-09 23:31:18 +07:00
parent 81cb1c9510
commit 77bc421359
4 changed files with 15 additions and 3 deletions

View File

@ -107,7 +107,7 @@ void dcd_remote_wakeup(uint8_t rhport);
* must be called to notify the stack * must be called to notify the stack
* - busy : Check if endpoint transferring is complete (TODO remove) * - busy : Check if endpoint transferring is complete (TODO remove)
* - stall : stall endpoint * - stall : stall endpoint
* - clear_stall : clear stall * - clear_stall : clear stall, data toggle is also reset to DATA0
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc); bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes); bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);

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@ -456,7 +456,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
case TUSB_REQ_CLEAR_FEATURE: case TUSB_REQ_CLEAR_FEATURE:
if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue ) if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue )
{ {
dcd_edpt_clear_stall(rhport, tu_u16_low(p_request->wIndex)); usbd_edpt_clear_stall(rhport, tu_u16_low(p_request->wIndex));
} }
usbd_control_status(rhport, p_request); usbd_control_status(rhport, p_request);
break; break;

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@ -322,7 +322,12 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
if ( tu_edpt_number(ep_addr) ) if ( tu_edpt_number(ep_addr) )
{ {
// clear stall
NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
// reset data toggle to DATA0
NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
__ISB(); __DSB(); __ISB(); __DSB();
} }
} }

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@ -128,7 +128,6 @@
*/ */
#ifndef CFG_TUSB_DEBUG #ifndef CFG_TUSB_DEBUG
#define CFG_TUSB_DEBUG 0 #define CFG_TUSB_DEBUG 0
#warning CFG_TUSB_DEBUG is not defined, default value is 0
#endif #endif
// place data in accessible RAM for usb controller // place data in accessible RAM for usb controller
@ -165,6 +164,14 @@
#define CFG_TUD_MSC 0 #define CFG_TUD_MSC 0
#endif #endif
#ifndef CFG_TUD_MIDI
#define CFG_TUD_MIDI 0
#endif
#ifndef CFG_TUD_CUSTOM_CLASS
#define CFG_TUD_CUSTOM_CLASS 0
#endif
#endif // TUSB_OPT_DEVICE_ENABLED #endif // TUSB_OPT_DEVICE_ENABLED
//-------------------------------------------------------------------- //--------------------------------------------------------------------