added rt1010 board support
not tested on the actual hardware board though.
This commit is contained in:
hathach
parent
9758f3e461
commit
778cff19c1
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include "fsl_device_registers.h"
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// required since iMX RT10xx SDK include this file for board size
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#define BOARD_FLASH_SIZE (0x1000000U)
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#endif /* BOARD_H_ */
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m7 \
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-mfloat-abi=hard \
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-mfpu=fpv5-d16 \
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-D__ARMVFP__=0 -D__ARMFPV5__=0\
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-DCPU_MIMXRT1011DAE5A \
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-DXIP_EXTERNAL_FLASH=1 \
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-DXIP_BOOT_HEADER_ENABLE=1 \
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-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
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# mcu driver cause following warnings
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CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough=
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MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1011
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# All source paths should be relative to the top level.
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LD_FILE = $(MCU_DIR)/gcc/MIMXRT1011xxxxx_flexspi_nor.ld
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SRC_C += \
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$(MCU_DIR)/system_MIMXRT1011.c \
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$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
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$(MCU_DIR)/project_template/clock_config.c \
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$(MCU_DIR)/drivers/fsl_clock.c \
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$(MCU_DIR)/drivers/fsl_gpio.c \
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$(MCU_DIR)/drivers/fsl_common.c \
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$(MCU_DIR)/drivers/fsl_lpuart.c
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INC += \
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$(TOP)/hw/bsp/$(BOARD) \
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$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
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$(TOP)/$(MCU_DIR) \
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$(TOP)/$(MCU_DIR)/drivers \
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$(TOP)/$(MCU_DIR)/project_template \
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SRC_S += $(MCU_DIR)/gcc/startup_MIMXRT1011.S
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# For TinyUSB port source
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VENDOR = nxp
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CHIP_FAMILY = transdimension
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM7
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# For flash-jlink target
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JLINK_DEVICE = MIMXRT1011DAE5A
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JLINK_IF = swd
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# flash by copying bin file to DAP Mass Storage
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flash: $(BUILD)/$(BOARD)-firmware.bin
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cp $< /media/$(USER)/RT1010-EVK/
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "evkmimxrt1010_flexspi_nor_config.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_100MHz,
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.sflashA1Size = 16u * 1024u * 1024u,
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.lookupTable =
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{
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.blockSize = 256u * 1024u,
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.isUniformBlockSize = false,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */
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@ -0,0 +1,267 @@
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
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#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
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#include <stdint.h>
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#include <stdbool.h>
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#include "fsl_common.h"
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/*! @name Driver version */
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/*@{*/
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/*! @brief XIP_BOARD driver version 2.0.0. */
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#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* FLEXSPI memory config block related defintions */
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI Feature related definitions */
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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/* Lookup table related defintions */
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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//!@brief Definitions for FlexSPI Serial Clock Frequency
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typedef enum _FlexSpiSerialClockFreq
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{
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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} flexspi_serial_clk_freq_t;
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//!@brief FlexSPI clock configuration type
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enum
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{
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kFlexSpiClk_SDR, //!< Clock configure for SDR mode
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kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
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};
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//!@brief FlexSPI Read Sample Clock Source definition
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typedef enum _FlashReadSampleClkSource
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{
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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} flexspi_read_sample_clk_t;
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//!@brief Misc feature bit definitions
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enum
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{
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kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
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kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
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kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
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kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
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kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
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};
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//!@brief Flash Type Definition
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enum
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{
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kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
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kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
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kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
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};
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//!@brief Flash Pad Definitions
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enum
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{
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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};
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//!@brief FlexSPI LUT Sequence structure
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typedef struct _lut_sequence
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{
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uint8_t seqNum; //!< Sequence Number, valid number: 1-16
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uint8_t seqId; //!< Sequence Index, valid number: 0-15
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uint16_t reserved;
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} flexspi_lut_seq_t;
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//!@brief Flash Configuration Command Type
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enum
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{
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kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
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kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
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kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
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kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
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kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
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kDeviceConfigCmdType_Reset, //!< Reset device command
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};
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//!@brief FlexSPI Memory Configuration Block
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typedef struct _FlexSPIConfig
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{
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uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
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uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
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uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
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uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
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uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
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uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
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uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
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//! Serial NAND, need to refer to datasheet
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uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
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uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
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//! Generic configuration, etc.
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uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
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//! DPI/QPI/OPI switch or reset command
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flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
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//! sequence number, [31:16] Reserved
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uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
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uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
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uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
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flexspi_lut_seq_t
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configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
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uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
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uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
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uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
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uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
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//! details
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uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
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uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
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uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
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//! Chapter for more details
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uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
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//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
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uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
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uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
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uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
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uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
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uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
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uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
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uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
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uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
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uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
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uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
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uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
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uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
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uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
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uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
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//! busy flag is 0 when flash device is busy
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uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
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flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
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uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
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} flexspi_mem_config_t;
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/* */
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#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
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#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
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#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
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#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
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#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
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#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
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#define NOR_CMD_INDEX_DUMMY 6 //!< 6
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#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
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#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
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CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
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2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
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CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
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4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2018, hathach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include "../board.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_lpuart.h"
|
||||
|
||||
#include "clock_config.h"
|
||||
|
||||
#define LED_PINMUX IOMUXC_GPIO_11_GPIOMUX_IO11
|
||||
#define LED_PORT GPIO1
|
||||
#define LED_PIN 11
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
// SW8 button
|
||||
#define BUTTON_PINMUX IOMUXC_GPIO_SD_05_GPIO2_IO05
|
||||
#define BUTTON_PORT GPIO2
|
||||
#define BUTTON_PIN 5
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
// UART
|
||||
#define UART_PORT LPUART1
|
||||
#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD
|
||||
#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD
|
||||
|
||||
const uint8_t dcd_data[] = { 0x00 };
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
// Init clock
|
||||
BOARD_BootClockRUN();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
// Enable IOCON clock
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
// NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
// LED
|
||||
IOMUXC_SetPinMux( LED_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
|
||||
|
||||
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
|
||||
GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
|
||||
board_led_write(true);
|
||||
|
||||
// Button
|
||||
IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig(BUTTON_PINMUX, 0x01B0A0U);
|
||||
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
|
||||
GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
|
||||
|
||||
// UART
|
||||
IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
|
||||
IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
|
||||
IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
|
||||
|
||||
lpuart_config_t uart_config;
|
||||
LPUART_GetDefaultConfig(&uart_config);
|
||||
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
|
||||
uart_config.enableTx = true;
|
||||
uart_config.enableRx = true;
|
||||
LPUART_Init(UART_PORT, &uart_config, (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U));
|
||||
|
||||
//------------- USB0 -------------//
|
||||
// Clock
|
||||
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
|
||||
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
|
||||
|
||||
USBPHY_Type* usb_phy = USBPHY;
|
||||
|
||||
// Enable PHY support for Low speed device + LS via FS Hub
|
||||
usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
|
||||
|
||||
// Enable all power for normal operation
|
||||
usb_phy->PWD = 0;
|
||||
|
||||
// TX Timing
|
||||
uint32_t phytx = usb_phy->TX;
|
||||
phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
|
||||
phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
|
||||
usb_phy->TX = phytx;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB Interrupt Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void USB_OTG1_IRQHandler(void)
|
||||
{
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
tuh_isr(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
tud_isr(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
// active low
|
||||
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
LPUART_ReadBlocking(UART_PORT, buf, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
int board_uart_write(void const * buf, int len)
|
||||
{
|
||||
LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue