implementing dcd_edpt_open
This commit is contained in:
hathach
parent
988edce745
commit
759fa76280
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@ -0,0 +1,215 @@
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/* Auto-generated config file hpl_usart_config.h */
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#ifndef HPL_USART_CONFIG_H
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#define HPL_USART_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_USART_7_ENABLE
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#define CONF_USART_7_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <o> Frame parity
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// <0x0=>Even parity
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// <0x1=>Odd parity
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// <0x2=>Parity forced to 0
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// <0x3=>Parity forced to 1
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// <0x4=>No parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_USART_7_PARITY
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#define CONF_USART_7_PARITY 0x4
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#endif
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// <o> Character Size
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// <0x0=>5 bits
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// <0x1=>6 bits
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// <0x2=>7 bits
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// <0x3=>8 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_USART_7_CHSIZE
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#define CONF_USART_7_CHSIZE 0x3
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#endif
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// <o> Stop Bit
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// <0=>1 stop bit
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// <1=>1.5 stop bits
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// <2=>2 stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_USART_7_SBMODE
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#define CONF_USART_7_SBMODE 0
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#endif
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// <o> Clock Output Select
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// <0=>The USART does not drive the SCK pin
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// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
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// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
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// <id> usart_clock_output_select
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#ifndef CONF_USART_7_CLKO
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#define CONF_USART_7_CLKO 0
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#endif
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// <o> Baud rate <1-3000000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_USART_7_BAUD
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#define CONF_USART_7_BAUD 9600
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_USART_7_ADVANCED_CONFIG
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#define CONF_USART_7_ADVANCED_CONFIG 0
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#endif
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// <o> Channel Mode
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// <0=>Normal Mode
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// <1=>Automatic Echo
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// <2=>Local Loopback
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// <3=>Remote Loopback
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// <i> Channel mode in USART frame
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// <id> usart_channel_mode
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#ifndef CONF_USART_7_CHMODE
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#define CONF_USART_7_CHMODE 0
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#endif
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// <q> 9 bits character enable
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// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
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// <id> usart_9bits_enable
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#ifndef CONF_USART_7_MODE9
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#define CONF_USART_7_MODE9 0
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#endif
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// <o> Variable Sync
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// <0=>User defined configuration
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// <1=>sync field is updated when a character is written into US_THR
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// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
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// <id> variable_sync
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#ifndef CONF_USART_7_VAR_SYNC
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#define CONF_USART_7_VAR_SYNC 0
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#endif
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// <o> Oversampling Mode
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// <0=>16 Oversampling
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// <1=>8 Oversampling
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// <i> Oversampling Mode in UART mode
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// <id> usart__oversampling_mode
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#ifndef CONF_USART_7_OVER
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#define CONF_USART_7_OVER 0
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#endif
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// <o> Inhibit Non Ack
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// <0=>The NACK is generated
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// <1=>The NACK is not generated
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// <i> Inhibit Non Acknowledge
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// <id> usart__inack
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#ifndef CONF_USART_7_INACK
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#define CONF_USART_7_INACK 1
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#endif
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// <o> Disable Successive NACK
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// <0=>NACK is sent on the ISO line as soon as a parity error occurs
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// <1=>Many parity errors generate a NACK on the ISO line
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// <i> Disable Successive NACK
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// <id> usart_dsnack
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#ifndef CONF_USART_7_DSNACK
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#define CONF_USART_7_DSNACK 0
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#endif
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// <o> Inverted Data
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// <0=>Data isn't inverted, nomal mode
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// <1=>Data is inverted
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// <i> Inverted Data
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// <id> usart_invdata
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#ifndef CONF_USART_7_INVDATA
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#define CONF_USART_7_INVDATA 0
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#endif
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// <o> Maximum Number of Automatic Iteration <0-7>
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// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
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// <id> usart_max_iteration
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#ifndef CONF_USART_7_MAX_ITERATION
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#define CONF_USART_7_MAX_ITERATION 0
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#endif
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// <q> Receive Line Filter enable
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// <i> whether the USART filters the receive line using a three-sample filter
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// <id> usart_receive_filter_enable
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#ifndef CONF_USART_7_FILTER
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#define CONF_USART_7_FILTER 0
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#endif
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// <q> Manchester Encoder/Decoder Enable
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// <i> whether the USART Manchester Encoder/Decoder
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// <id> usart_manchester_filter_enable
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#ifndef CONF_USART_7_MAN
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#define CONF_USART_7_MAN 0
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#endif
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// <o> Manchester Synchronization Mode
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// <0=>The Manchester start bit is a 0 to 1 transition
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// <1=>The Manchester start bit is a 1 to 0 transition
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// <i> Manchester Synchronization Mode
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// <id> usart_manchester_synchronization_mode
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#ifndef CONF_USART_7_MODSYNC
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#define CONF_USART_7_MODSYNC 0
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#endif
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// <o> Start Frame Delimiter Selector
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// <0=>Start frame delimiter is COMMAND or DATA SYNC
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// <1=>Start frame delimiter is one bit
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// <i> Start Frame Delimiter Selector
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// <id> usart_start_frame_delimiter
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#ifndef CONF_USART_7_ONEBIT
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#define CONF_USART_7_ONEBIT 0
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#endif
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_USART_7_FRACTIONAL
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#define CONF_USART_7_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>LSB is transmitted first
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// <1=>MSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_msbf
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#ifndef CONF_USART_7_MSBF
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#define CONF_USART_7_MSBF 0
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#endif
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// </e>
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#define CONF_USART_7_MODE 0x0
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// Calculate BAUD register value in UART mode
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#if CONF_FLEXCOM7_CK_SRC < 3
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#ifndef CONF_USART_7_BAUD_CD
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#define CONF_USART_7_BAUD_CD ((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / 8 / (2 - CONF_USART_7_OVER))
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#endif
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#ifndef CONF_USART_7_BAUD_FP
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#define CONF_USART_7_BAUD_FP \
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((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / (2 - CONF_USART_7_OVER) - 8 * CONF_USART_7_BAUD_CD)
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#endif
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#elif CONF_FLEXCOM7_CK_SRC == 3
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// No division is active. The value written in US_BRGR has no effect.
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#ifndef CONF_USART_7_BAUD_CD
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#define CONF_USART_7_BAUD_CD 1
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#endif
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#ifndef CONF_USART_7_BAUD_FP
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#define CONF_USART_7_BAUD_FP 1
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#endif
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_USART_CONFIG_H
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@ -0,0 +1,85 @@
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/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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/**
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* \def CONF_HCLK_FREQUENCY
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* \brief HCLK's Clock frequency
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*/
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#ifndef CONF_HCLK_FREQUENCY
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#define CONF_HCLK_FREQUENCY 8000000
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#endif
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/**
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* \def CONF_FCLK_FREQUENCY
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* \brief FCLK's Clock frequency
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*/
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#ifndef CONF_FCLK_FREQUENCY
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#define CONF_FCLK_FREQUENCY 8000000
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#endif
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/**
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* \def CONF_CPU_FREQUENCY
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* \brief CPU's Clock frequency
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*/
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 8000000
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#endif
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/**
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* \def CONF_SLCK_FREQUENCY
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* \brief Slow Clock frequency
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*/
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#define CONF_SLCK_FREQUENCY 32768
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/**
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* \def CONF_MCK_FREQUENCY
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* \brief Master Clock frequency
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*/
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#define CONF_MCK_FREQUENCY 8000000
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// <o> USB Clock Source
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// <0=> USB Clock Controller (USB_48M)
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// <id> usb_clock_source
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// <i> Select the clock source for USB.
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#ifndef CONF_UDP_SRC
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#define CONF_UDP_SRC 0
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#endif
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/**
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* \def CONF_UDP_FREQUENCY
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* \brief UDP's Clock frequency
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*/
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#ifndef CONF_UDP_FREQUENCY
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#define CONF_UDP_FREQUENCY 48005120
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#endif
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// <h> FLEXCOM Clock Settings
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// <o> FLEXCOM Clock source
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// <0=> Master Clock (MCK)
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// <1=> MCK / 8
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// <2=> Programmable Clock Controller 6 (PMC_PCK6)
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// <2=> Programmable Clock Controller 7 (PMC_PCK7)
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// <3=> External Clock
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// <i> This defines the clock source for the FLEXCOM, PCK6 is used for FLEXCOM0/1/2/3 and PCK7 is used for FLEXCOM4/5/6/7
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// <id> flexcom_clock_source
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#ifndef CONF_FLEXCOM7_CK_SRC
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#define CONF_FLEXCOM7_CK_SRC 0
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#endif
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// <o> FLEXCOM External Clock Input on SCK <1-4294967295>
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// <i> Inputs the external clock frequency on SCK
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// <id> flexcom_clock_freq
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#ifndef CONF_FLEXCOM7_SCK_FREQ
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#define CONF_FLEXCOM7_SCK_FREQ 10000000
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#endif
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#ifndef CONF_FLEXCOM7_FREQUENCY
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#define CONF_FLEXCOM7_FREQUENCY 8000000
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H
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@ -35,6 +35,8 @@
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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#define EP_COUNT 6
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// Transfer descriptor
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typedef struct
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{
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@ -44,8 +46,8 @@ typedef struct
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uint16_t epsize;
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} xfer_desc_t;
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// Endpoint 0-5 with OUT & IN
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xfer_desc_t _dcd_xfer[6][2];
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// Endpoint 0-5, each can only be either OUT or In
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xfer_desc_t _dcd_xfer[EP_COUNT];
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void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes)
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{
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@ -77,7 +79,7 @@ static void bus_reset(void)
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{
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tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
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_dcd_xfer[0][0].epsize = _dcd_xfer[0][1].epsize = CFG_TUD_ENDPOINT0_SIZE;
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_dcd_xfer[0].epsize = CFG_TUD_ENDPOINT0_SIZE;
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// Enable EP0 control
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UDP->UDP_CSR[0] = UDP_CSR_EPEDS_Msk;
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@ -163,11 +165,29 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
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}
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// Configure endpoint's registers according to descriptor
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// SAMG doesnt support using a same endpoint with IN and OUT
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// e.g EP1 OUT & EP1 IN cannot exist together
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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(void) ep_desc;
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return false;
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uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
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uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
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// TODO Isochronous is not supported yet
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TU_VERIFY(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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TU_VERIFY(epnum < EP_COUNT);
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// Must not already enabled
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TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0);
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// Configure type and eanble EP
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UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir);
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// Enable EP Interrupt
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UDP->UDP_IER |= (1 << epnum);
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return true;
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}
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// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
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@ -178,7 +198,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_desc_t* xfer = &_dcd_xfer[epnum][dir];
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_begin(xfer, buffer, total_bytes);
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uint16_t const xact_len = xfer_packet_len(xfer);
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@ -217,7 +237,6 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// uint8_t const dir = tu_edpt_dir(ep_addr);
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// Set force stall bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_FORCESTALL_Msk;
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@ -227,7 +246,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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(void) ep_addr;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// clear stall, must also clear data toggle
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_FORCESTALL_Msk;
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}
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//--------------------------------------------------------------------+
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@ -282,12 +305,13 @@ void dcd_isr(uint8_t rhport)
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}
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}
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for(uint8_t epnum = 0; epnum < 6; epnum++)
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for(uint8_t epnum = 0; epnum < EP_COUNT; epnum++)
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{
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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// Endpoint IN
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if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
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{
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xfer_desc_t* xfer = &_dcd_xfer[epnum][1];
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uint16_t xact_len = xfer_packet_len(xfer);
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xfer_packet_done(xfer);
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