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change lpc17xx cmsis file & ohci to be able to build with IAR

This commit is contained in:
hathach 2014-03-04 15:19:50 +07:00
parent 93a60641ea
commit 6f24dd50a0
9 changed files with 3610 additions and 1698 deletions
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183
demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmFunc.h
View File

@ -350,189 +350,16 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
#include <cmsis_iar.h>
/** \brief Disable IRQ Interrupts
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
#include <cmsis_ccs.h>
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts

185
demos/bsp/lpc175x_6x/CMSISv2p00_LPC17xx/inc/core_cmInstr.h
View File

@ -263,190 +263,13 @@ extern void __CLREX(void);
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
#include <cmsis_iar.h>
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/

10
demos/host/host_freertos/host_freertos.uvopt
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@ -1042,10 +1042,10 @@
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>2</ColumnNumber>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>2094</TopLine>
<CurrentLine>2109</CurrentLine>
<TopLine>2112</TopLine>
<CurrentLine>2115</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\vendor\freertos\freertos\Source\tasks.c</PathWithFileName>
<FilenameWithoutPath>tasks.c</FilenameWithoutPath>
@ -1570,10 +1570,10 @@
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>20</ColumnNumber>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>122</TopLine>
<CurrentLine>133</CurrentLine>
<CurrentLine>129</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\bsp\lpc175x_6x\startup_keil\startup_LPC17xx.s</PathWithFileName>
<FilenameWithoutPath>startup_LPC17xx.s</FilenameWithoutPath>

3905
demos/host/host_os_none/host_os_none.ewd
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File diff suppressed because it is too large Load Diff

971
demos/host/host_os_none/host_os_none.ewp
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File diff suppressed because it is too large Load Diff

4
tinyusb/common/compiler/compiler_iar.h
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@ -66,6 +66,7 @@
#define ATTR_ALIGNED_64 _Pragma("data_alignment=64")
#define ATTR_ALIGNED_48 _Pragma("data_alignment=48")
#define ATTR_ALIGNED_32 _Pragma("data_alignment=32")
#define ATTR_ALIGNED_16 _Pragma("data_alignment=16")
#define ATTR_ALIGNED_4 _Pragma("data_alignment=4")
#ifndef ATTR_ALWAYS_INLINE
@ -86,6 +87,9 @@
#define __be2n __REV
#define __n2be __be2n
#define __n2be_16(u16) ((uint16_t) __REV16(u16))
#define __be2n_16(u16) __n2be_16(u16)
#ifdef __cplusplus
}
#endif

10
tinyusb/host/ehci/ehci.h
View File

@ -152,6 +152,8 @@ typedef struct {
uint32_t buffer[5];
} ehci_qtd_t; // XXX qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with ATTR_ALIGNED(32)
STATIC_ASSERT( sizeof(ehci_qtd_t) == 32, "size is not correct" );
/// Queue Head (section 3.6)
typedef struct {
/// Word 0: Queue Head Horizontal Link Pointer
@ -202,6 +204,8 @@ typedef struct {
ehci_qtd_t * volatile p_qtd_list_tail; // tail of the scheduled TD list
} ehci_qhd_t;
STATIC_ASSERT( sizeof(ehci_qhd_t) == 64, "size is not correct" );
/// Highspeed Isochronous Transfer Descriptor (section 3.3)
typedef struct ATTR_ALIGNED(32) {
/// Word 0: Next Link Pointer
@ -232,6 +236,8 @@ typedef struct ATTR_ALIGNED(32) {
// uint32_t reserved[6];
} ehci_itd_t;
STATIC_ASSERT( sizeof(ehci_itd_t) == 64, "size is not correct" );
/// Split (Full-Speed) Isochronous Transfer Descriptor
typedef struct ATTR_ALIGNED(32) {
/// Word 0: Next Link Pointer
@ -288,12 +294,14 @@ typedef struct ATTR_ALIGNED(32) {
/*---------- Word 6 ----------*/
ehci_link_t back;
/// SITD is 32-byte aligned but occupies only 28 --> 6 bytes for storing extra data
/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
uint8_t used;
uint8_t ihd_idx;
uint8_t reserved2[2];
} ehci_sitd_t;
STATIC_ASSERT( sizeof(ehci_sitd_t) == 32, "size is not correct" );
//--------------------------------------------------------------------+
// EHCI Operational Register
//--------------------------------------------------------------------+

20
tinyusb/host/ohci/ohci.c
View File

@ -320,7 +320,7 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t con
p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
//------------- Attach TDs list to Control Endpoint -------------//
p_ed->td_head = (uint32_t) p_setup;
p_ed->td_head.address = (uint32_t) p_setup;
OHCI_REG->command_status_bit.control_list_filled = 1;
@ -450,13 +450,13 @@ static ohci_gtd_t * gtd_find_free(uint8_t dev_addr)
static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
{
// tail is always NULL
if ( align16(p_ed->td_head) == 0 )
if ( align16(p_ed->td_head.address) == 0 )
{ // TD queue is empty --> head = TD
p_ed->td_head |= (uint32_t) p_gtd;
p_ed->td_head.address |= (uint32_t) p_gtd;
}
else
{ // TODO currently only support queue up to 2 TD each endpoint at a time
((ohci_gtd_t*) align16(p_ed->td_head))->next_td = (uint32_t) p_gtd;
((ohci_gtd_t*) align16(p_ed->td_head.address))->next_td = (uint32_t) p_gtd;
}
}
@ -513,19 +513,19 @@ tusb_error_t hcd_pipe_close(pipe_handle_t pipe_hdl)
bool hcd_pipe_is_busy(pipe_handle_t pipe_hdl)
{
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
return align16(p_ed->td_head) != align16(p_ed->td_tail.address);
return align16(p_ed->td_head.address) != align16(p_ed->td_tail.address);
}
bool hcd_pipe_is_error(pipe_handle_t pipe_hdl)
{
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
return p_ed->halted;
return p_ed->td_head.halted;
}
bool hcd_pipe_is_stalled(pipe_handle_t pipe_hdl)
{
ohci_ed_t const * const p_ed = ed_from_pipe_handle(pipe_hdl);
return p_ed->halted && p_ed->is_stalled;
return p_ed->td_head.halted && p_ed->is_stalled;
}
uint8_t hcd_pipe_get_endpoint_addr(pipe_handle_t pipe_hdl)
@ -541,8 +541,8 @@ tusb_error_t hcd_pipe_clear_stall(pipe_handle_t pipe_hdl)
p_ed->is_stalled = 0;
p_ed->td_tail.address &= 0x0Ful; // set tail pointer back to NULL
p_ed->toggle = 0; // reset data toggle
p_ed->halted = 0;
p_ed->td_head.toggle = 0; // reset data toggle
p_ed->td_head.halted = 0;
if ( TUSB_XFER_BULK == ed_get_xfer_type(p_ed) ) OHCI_REG->command_status_bit.bulk_list_filled = 1;
@ -630,7 +630,7 @@ static void done_queue_isr(uint8_t hostid)
if ((event != TUSB_EVENT_XFER_COMPLETE))
{
p_ed->td_tail.address &= 0x0Ful;
p_ed->td_tail.address |= align16(p_ed->td_head); // mark halted EP as empty queue
p_ed->td_tail.address |= align16(p_ed->td_head.address); // mark halted EP as empty queue
if ( event == TUSB_EVENT_XFER_STALLED ) p_ed->is_stalled = 1;
}

20
tinyusb/host/ohci/ohci.h
View File

@ -87,7 +87,7 @@ typedef struct {
}ohci_td_item_t;
typedef struct {
typedef struct ATTR_ALIGNED(16) {
//------------- Word 0 -------------//
uint32_t used : 1;
uint32_t index : 4; // endpoint index the td belongs to, or device address in case of control xfer
@ -109,11 +109,11 @@ typedef struct {
//------------- Word 3 -------------//
uint8_t* buffer_end;
} ATTR_ALIGNED(16) ohci_gtd_t;
} ohci_gtd_t;
STATIC_ASSERT( sizeof(ohci_gtd_t) == 16, "size is not correct" );
typedef struct {
typedef struct ATTR_ALIGNED(16) {
//------------- Word 0 -------------//
uint32_t device_address : 7;
uint32_t endpoint_number : 4;
@ -140,21 +140,21 @@ typedef struct {
//------------- Word 2 -------------//
volatile union {
uint32_t td_head;
uint32_t address;
struct {
uint32_t halted : 1;
uint32_t toggle : 1;
uint32_t : 30;
};
};
}td_head;
//------------- Word 3 -------------//
uint32_t next_ed; // 4 lsb bits are free to use
} ATTR_ALIGNED(16) ohci_ed_t;
} ohci_ed_t;
STATIC_ASSERT( sizeof(ohci_ed_t) == 16, "size is not correct" );
typedef struct {
typedef struct ATTR_ALIGNED(32) {
/*---------- Word 1 ----------*/
uint32_t starting_frame : 16;
uint32_t : 5; // can be used
@ -175,12 +175,12 @@ typedef struct {
/*---------- Word 5-8 ----------*/
volatile uint16_t offset_packetstatus[8];
} ATTR_ALIGNED(32) ochi_itd_t;
} ochi_itd_t;
STATIC_ASSERT( sizeof(ochi_itd_t) == 32, "size is not correct" );
// structure with member alignment required from large to small
typedef struct {
typedef struct ATTR_ALIGNED(256) {
ohci_hcca_t hcca;
ohci_ed_t bulk_head_ed; // static bulk head (dummy)
@ -198,7 +198,7 @@ typedef struct {
ohci_gtd_t gtd[OHCI_MAX_QTD];
}device[TUSB_CFG_HOST_DEVICE_MAX];
}ATTR_ALIGNED(256) ohci_data_t;
} ohci_data_t;
//--------------------------------------------------------------------+
// OHCI Operational Register