complete double buffering for queueing xfer for lpc11u/13u requried by msc device

2013-11-14 14:12:07 +07:00 · 2013-11-14 14:12:07 +07:00 · 6e8440afe5
parent 7d84139bd4
commit 6e8440afe5
11 changed files with 145 additions and 102 deletions
--- a/demos/device/device_os_none/.cproject
+++ b/demos/device/device_os_none/.cproject
@ -30,7 +30,7 @@
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+								<option id="com.crt.advproject.gcc.arch.658802474" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
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@ -54,7 +54,7 @@
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+								<option id="com.crt.advproject.gas.arch.1370417737" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
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@ -62,7 +62,7 @@
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+								<option id="com.crt.advproject.link.arch.1411471839" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
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@ -119,7 +119,7 @@
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+								<option id="com.crt.advproject.gcc.arch.227583493" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
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@ -143,7 +143,7 @@
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+								<option id="com.crt.advproject.gas.arch.62277376" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
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@ -151,7 +151,7 @@
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-								<option id="com.crt.advproject.link.arch.5439507" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm0" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.arch.5439507" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
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@ -208,7 +208,7 @@
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+								<option id="com.crt.advproject.gcc.arch.1901283003" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
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@ -234,7 +234,7 @@
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+								<option id="com.crt.advproject.gas.arch.767404687" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
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@ -243,7 +243,7 @@
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+								<option id="com.crt.advproject.link.arch.449102543" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
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@ -302,7 +302,7 @@
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@ -326,7 +326,7 @@
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@ -334,7 +334,7 @@
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@ -371,45 +371,49 @@
 	<storageModule moduleId="com.crt.config">
 		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
 &lt;TargetConfig&gt;&#13;
-&lt;Properties property_0="" property_3="NXP" property_4="LPC11U37/401" property_count="5" version="1"/&gt;&#13;
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-&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;Properties property_0="" property_3="NXP" property_4="LPC1347" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1347" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC1347&lt;/name&gt;&#13;
+&lt;family&gt;LPC13xx (12bit ADC)&lt;/family&gt;&#13;
 &lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
 &lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
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 &lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
-&lt;memoryInstance derived_from="Flash" id="MFlash128" location="0x0" size="0x20000"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
 &lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
 &lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
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-&lt;peripheralInstance derived_from="LPC1xxx_UART_MODEM" id="UART0" location="0x40008000"/&gt;&#13;
-&lt;peripheralInstance derived_from="LPC11_13_WDT" id="WDT" location="0x40004000"/&gt;&#13;
-&lt;peripheralInstance derived_from="LPC11_13_I2C" id="I2C0" location="0x40000000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x40064000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
 &lt;/chip&gt;&#13;
-&lt;processor&gt;&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
 &lt;family&gt;Cortex-M&lt;/family&gt;&#13;
 &lt;/processor&gt;&#13;
-&lt;link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
 &lt;/info&gt;&#13;
 &lt;/infoList&gt;&#13;
 &lt;/TargetConfig&gt;</projectStorage>
--- a/demos/device/device_os_none/tusb_config.h
+++ b/demos/device/device_os_none/tusb_config.h
@ -80,12 +80,14 @@
 #define TUSB_CFG_DEVICE_FULLSPEED       1 // TODO refractor, remove

 //------------- CLASS -------------//
-#define TUSB_CFG_DEVICE_HID_KEYBOARD  1
+#define TUSB_CFG_DEVICE_HID_KEYBOARD  0
 #define TUSB_CFG_DEVICE_HID_MOUSE     0
 #define TUSB_CFG_DEVICE_HID_GENERIC   0
-#define TUSB_CFG_DEVICE_MSC           0
+#define TUSB_CFG_DEVICE_MSC           1
 #define TUSB_CFG_DEVICE_CDC           0

+// TODO LPC11UXX seems not able to DMA > 64 bytes control transfer while LPC13uxx has no problem with that
+
 //--------------------------------------------------------------------+
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------+
--- a/readme.md
+++ b/readme.md
@ -49,7 +49,10 @@ coming soon ...

 ## Supported MCUs ##

- NXP LPC43xx family
+- NXP 
+  - LPC43xx
+  - LPC13uxx (12 bit ADC)
+  - LPC11uxx

 ## Supported Toolchains ##

@ -69,6 +72,10 @@ this code base can run out of the box with the following boards
 - [NGX Technologies LPC4330 Explorer](http://shop.ngxtechnologies.com/product_info.php?products_id=104)
 - [Keil MCB4357 Evaluation Board](http://www.keil.com/mcb4300)

+## Known Issues ##
+
+- LPC11uxx & LPC13uxx cannot able to STALL Control OUT endpoint !!! --> unsupported with data out request may cause host stuck with control transfer forever. (reproduce: enable keyboard + mouse, return error in set report of hid_device)
+
 ## Coding Standards ##

 C is a dangerous language by itself, plus tinyusb make use of goodies features of C99, which saves a tons of code lines (also means save a tons of bugs). However, those features can be misused and pave the way for bugs sneaking into. Therefore, to minimize bugs, the author try to comply with published Coding Standards like:
--- a/tinyusb/class/hid_device.c
+++ b/tinyusb/class/hid_device.c
@ -165,7 +165,8 @@ tusb_error_t hidd_control_request(uint8_t coreid, tusb_control_request_t const *

      case HID_REQUEST_CONTROL_SET_REPORT:
      {
-        return TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
+        return TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT; // TODO test STALL control out endpoint (with mouse+keyboard)
+
        // TODO HIDD set report support
        hid_request_report_type_t report_type = u16_high_u8(p_request->wValue);
        uint8_t report_id = u16_low_u8(p_request->wValue);
--- a/tinyusb/class/msc_device.c
+++ b/tinyusb/class/msc_device.c
@ -56,7 +56,7 @@ typedef struct {
  endpoint_handle_t edpt_in, edpt_out;

  // must be in USB ram
-  ATTR_USB_MIN_ALIGNMENT uint8_t max_lun;
+  ATTR_USB_MIN_ALIGNMENT uint8_t max_lun; // can STALL for one LUN

  ATTR_USB_MIN_ALIGNMENT msc_cmd_block_wrapper_t  cbw;
  ATTR_USB_MIN_ALIGNMENT msc_cmd_status_wrapper_t csw;
@ -176,6 +176,7 @@ void mscd_isr(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xferred_b
  }

  //------------- Status Phase -------------//
+  // TODO need to be true for dcd_lpc43xx to clean up qtd !!!
  ASSERT( dcd_pipe_xfer( p_msc->edpt_in , &p_msc->csw, sizeof(msc_cmd_status_wrapper_t), true) == TUSB_ERROR_NONE, VOID_RETURN );

  //------------- Queue the next CBW -------------//
--- a/tinyusb/common/binary.h
+++ b/tinyusb/common/binary.h
@ -66,7 +66,7 @@
 #define BIT_CLR_(x, n) ( (x) & (~BIT_(n)) )

 /// test n-th bit of x
-#define BIT_TEST_(x, n) ( (x) & BIT_(n) )
+#define BIT_TEST_(x, n) ( ((x) & BIT_(n)) ? true : false )

 #if defined(__GNUC__) && !defined(__CC_ARM)

--- a/tinyusb/device/dcd.h
+++ b/tinyusb/device/dcd.h
@ -78,7 +78,7 @@ void dcd_isr(uint8_t coreid);
 void dcd_controller_connect(uint8_t coreid);
 void dcd_controller_disconnect(uint8_t coreid);
 void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);
-void dcd_controller_set_configuration(uint8_t coreid, uint8_t config_num);
+void dcd_controller_set_configuration(uint8_t coreid);

 //------------- PIPE API -------------//
 tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * buffer, uint16_t length);
--- a/tinyusb/device/dcd_lpc43xx.c
+++ b/tinyusb/device/dcd_lpc43xx.c
@ -197,7 +197,7 @@ void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr)
  LPC_USB[coreid]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
 }

-void dcd_controller_set_configuration(uint8_t coreid, uint8_t config_num)
+void dcd_controller_set_configuration(uint8_t coreid)
 {

 }
--- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c
+++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c
@ -56,7 +56,7 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-#define DCD_LPC13XX_QHD 10
+#define DCD_11U_13U_QHD_COUNT 10

 enum {
  INT_MASK_SOF           = BIT_(30),
@ -98,9 +98,9 @@ typedef struct {
    }bits;
    uint32_t value;
  };
-} lpc13xx_dev_cmd_stat;
+} reg_dev_cmd_stat_t;

-STATIC_ASSERT( sizeof(lpc13xx_dev_cmd_stat) == 4, "size is not correct" );
+STATIC_ASSERT( sizeof(reg_dev_cmd_stat_t) == 4, "size is not correct" );


 // buffer input must be 64 byte alignment
@ -114,26 +114,26 @@ typedef struct {
  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
-}dcd_lpc13xx_qhd_t;
+}dcd_11u_13u_qhd_t;

-STATIC_ASSERT( sizeof(dcd_lpc13xx_qhd_t) == 4, "size is not correct" );
+STATIC_ASSERT( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );

 typedef struct {
-  dcd_lpc13xx_qhd_t qhd[DCD_LPC13XX_QHD][2]; ///< must be 256 byte alignment, 2 for double buffer
+  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer

-  uint16_t expected_bytes[DCD_LPC13XX_QHD]; ///< expected bytes of the queued transfer
-  uint8_t  class_code[DCD_LPC13XX_QHD]; // class where the endpoints belongs to TODO no need for control endpoints
+  uint16_t expected_bytes[DCD_11U_13U_QHD_COUNT]; ///< expected bytes of the queued transfer
+  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; // class where the endpoints belongs to TODO no need for control endpoints
  // there is padding from 80 --> 128 = 48 bytes

  // should start from 128
  ATTR_ALIGNED(64) tusb_control_request_t setup_request;

-}dcd_lpc13xx_data_t;
+}dcd_11u_13u_data_t;

 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-ATTR_ALIGNED(256) static dcd_lpc13xx_data_t dcd_data TUSB_CFG_ATTR_USBRAM;
+ATTR_ALIGNED(256) static dcd_11u_13u_data_t dcd_data TUSB_CFG_ATTR_USBRAM;

 static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
 static inline uint16_t addr_offset(void const * p_buffer)
@ -151,7 +151,7 @@ void dcd_controller_connect(uint8_t coreid)
  LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_CMD_CONNECT;
 }

-void dcd_controller_set_configuration(uint8_t coreid, uint8_t config_num)
+void dcd_controller_set_configuration(uint8_t coreid)
 {

 }
@ -168,7 +168,6 @@ tusb_error_t dcd_init(void)
 {
  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
-  LPC_USB->EPBUFCFG     = 0; // TODO double buffering

  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
@ -179,8 +178,8 @@ tusb_error_t dcd_init(void)

 static void bus_reset(void)
 {
-  memclr_(&dcd_data, sizeof(dcd_lpc13xx_data_t));
-  for(uint8_t ep_id = 2; ep_id < DCD_LPC13XX_QHD; ep_id++)
+  memclr_(&dcd_data, sizeof(dcd_11u_13u_data_t));
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
  { // disable all non-control endpoints on bus reset
    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
  }
@ -188,6 +187,7 @@ static void bus_reset(void)
  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);

  LPC_USB->EPINUSE      = 0;
+  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
  LPC_USB->EPSKIP       = 0xFFFFFFFF;

  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
@ -245,20 +245,29 @@ void dcd_isr(uint8_t coreid)
  }

  //------------- Non-Control Endpoints -------------//
-  for(uint8_t ep_id = 2; ep_id < DCD_LPC13XX_QHD; ep_id++ )
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
  {
    if ( BIT_TEST_(int_status, ep_id) )
    {
-      endpoint_handle_t edpt_hdl =
+      // Ignore if interrupt caused by buffer0 while we only have "Interrupt On Complete" with buffer1
+      // usbd/class driver under no situations to set "Interrupt On Complete" on both buffers
+      // Single Buffering and (Double with completed on buffer1) is valid
+      if ( !BIT_TEST_(LPC_USB->EPBUFCFG, ep_id) || !BIT_TEST_(LPC_USB->EPINUSE, ep_id) )
      {
-          .coreid     = coreid,
-          .index      = ep_id,
-          .class_code = dcd_data.class_code[ep_id]
-      };
+        endpoint_handle_t edpt_hdl =
+        {
+            .coreid     = coreid,
+            .index      = ep_id,
+            .class_code = dcd_data.class_code[ep_id]
+        };

-      // TODO no way determine if the transfer is failed or not
-      usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE,
-                    dcd_data.expected_bytes[ep_id] - dcd_data.qhd[ep_id][0].total_bytes); // only number of bytes in the IOC qtd
+        LPC_USB->INTEN    = BIT_CLR_(LPC_USB->INTEN    , ep_id); // clear interrupt on completion
+        LPC_USB->EPBUFCFG = BIT_CLR_(LPC_USB->EPBUFCFG , ep_id); // clear double buffering
+
+        // TODO no way determine if the transfer is failed or not
+        usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE,
+                      dcd_data.expected_bytes[ep_id] - dcd_data.qhd[ep_id][0].total_bytes); // only number of bytes in the IOC qtd
+      }
    }
  }

@ -309,11 +318,11 @@ tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void *
 //  return (pos < DCD_QHD_MAX/2) ? (2*pos) : (2*(pos-16)+1);
 //}

-static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint)
-{
-  return physical_endpoint/2 + ( (physical_endpoint%2) ? 16 : 0);
-}
+//static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
+//static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint)
+//{
+//  return physical_endpoint/2 + ( (physical_endpoint%2) ? 16 : 0);
+//}

 static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
 static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
@ -334,7 +343,7 @@ tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
 {
  ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring

-  dcd_data.qhd[edpt_hdl.index][0].stall = 1;
+  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;

  return TUSB_ERROR_NONE;
 }
@ -342,10 +351,12 @@ tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl)
 tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
 {
  uint8_t ep_id = edpt_addr2phy(edpt_addr);
+  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;

-  dcd_data.qhd[ep_id][0].stall           = 0;
-  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
-  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
+  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
+
+  dcd_data.qhd[ep_id][active_buffer].toggle_reset    = 1;
+  dcd_data.qhd[ep_id][active_buffer].feedback_toggle = 0;

  return TUSB_ERROR_NONE;
 }
@ -362,10 +373,10 @@ endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const
  //------------- Prepare Queue Head -------------//
  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);

-  ASSERT( dcd_data.qhd[ep_id][0].disable, null_handle ); // endpoint must not previously opened
+  ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened

-  memclr_(dcd_data.qhd[ep_id], 2*sizeof(dcd_lpc13xx_qhd_t));
-  dcd_data.qhd[ep_id][0].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  memclr_(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
+  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
  dcd_data.class_code[ep_id] = class_code;

  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
@ -380,7 +391,7 @@ endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const

 bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
 {
-  return dcd_data.qhd[edpt_hdl.index][0].active;
+  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
 }

 //// add only, controller virtually cannot know
@ -391,28 +402,43 @@ bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl)
 //  return TUSB_ERROR_NONE;
 //}

-//tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
-//{
-//
-//}
-
-tusb_error_t  dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t total_bytes, bool int_on_complete)
+tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
 {
  ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring

-  if (int_on_complete)
-  {
-    LPC_USB->INTEN = BIT_SET_(LPC_USB->INTEN, edpt_hdl.index);
-  }else
-  {
-    LPC_USB->INTEN = BIT_CLR_(LPC_USB->INTEN, edpt_hdl.index);
-  }
-
  dcd_data.qhd[edpt_hdl.index][0].buff_addr_offset = addr_offset(buffer);
  dcd_data.qhd[edpt_hdl.index][0].total_bytes      = total_bytes;
  dcd_data.expected_bytes[edpt_hdl.index]          = total_bytes;

-  dcd_data.qhd[edpt_hdl.index][0].active           = 1;
+  LPC_USB->EPBUFCFG = BIT_SET_(LPC_USB->EPBUFCFG, edpt_hdl.index); // queue xfer requires double buffering
+
+  return TUSB_ERROR_NONE;
+}
+
+tusb_error_t  dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void* buffer, uint16_t total_bytes, bool int_on_complete)
+{
+  ASSERT( !dcd_pipe_is_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
+
+
+  // In case both Buffers (0 & 1) have xfer and only buffer1 has int_on_complete, enable interrupt will also cause buffer0's
+  // xfer completion assert interrupt. This is unintentional side effect, and only can be handled in dcd_isr
+  LPC_USB->INTEN   = int_on_complete ? BIT_SET_(LPC_USB->INTEN, edpt_hdl.index) : BIT_CLR_(LPC_USB->INTEN, edpt_hdl.index);
+
+  // double buffering means there is another xfer has been queued in buffer0
+  uint8_t buff_idx = BIT_TEST_(LPC_USB->EPBUFCFG, edpt_hdl.index) ? 1 : 0;
+
+  dcd_data.qhd[edpt_hdl.index][buff_idx].buff_addr_offset = addr_offset(buffer);
+  dcd_data.qhd[edpt_hdl.index][buff_idx].total_bytes      = total_bytes;
+  dcd_data.expected_bytes[edpt_hdl.index]                 = total_bytes; // TODO currently only calculate xferred bytes on IOC one
+
+  if (buff_idx)
+  {
+    LPC_USB->EPINUSE = BIT_CLR_(LPC_USB->EPINUSE, edpt_hdl.index); // force HW to use buffer0
+    dcd_data.qhd[edpt_hdl.index][1].active = 1;
+  }
+
+  dcd_data.qhd[edpt_hdl.index][0].active = 1; // buffer0 always has queued xfer
+

 	return TUSB_ERROR_NONE;
 }
--- a/tinyusb/device/usbd.c
+++ b/tinyusb/device/usbd.c
@ -146,9 +146,11 @@ tusb_error_t usbd_init (void)
 //--------------------------------------------------------------------+
 // CONTROL REQUEST
 //--------------------------------------------------------------------+
+// TODO Host (windows) can get HID report descriptor before set configured
+// need to open interface before set configured
 tusb_error_t usbh_set_configure_received(uint8_t coreid, uint8_t config_number)
 {
-  dcd_controller_set_configuration(coreid, config_number);
+  dcd_controller_set_configuration(coreid);
  usbd_devices[coreid].state = TUSB_DEVICE_STATE_CONFIGURED;

  //------------- parse configuration & open drivers -------------//
@ -287,7 +289,7 @@ void usbd_setup_received_isr(uint8_t coreid, tusb_control_request_t * p_request)
  if(TUSB_ERROR_NONE != error)
  { // Response with Protocol Stall if request is not supported
    dcd_pipe_control_stall(coreid);
-    ASSERT(error == TUSB_ERROR_NONE, VOID_RETURN);
+//    ASSERT(error == TUSB_ERROR_NONE, VOID_RETURN);
  }
 }

--- a/tinyusb/hal/hal.h
+++ b/tinyusb/hal/hal.h
@ -110,7 +110,7 @@ static inline bool hal_debugger_is_attached(void)
 #if !defined(_TEST_) && !(MCU==MCU_LPC11UXX)
  return ( (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == CoreDebug_DHCSR_C_DEBUGEN_Msk );
 #else
-  return false;
+  return true; // force to break into breakpoint
 #endif
 }