remove CFG_TUD_CDC_FLUSH_ON_SOF option

This commit is contained in:
hathach 2018-08-30 15:20:15 +07:00
parent 583326e535
commit 61e4a8c3d3
7 changed files with 1 additions and 40 deletions

View File

@ -87,11 +87,6 @@
#define CFG_TUD_CDC_RX_BUFSIZE 64
#define CFG_TUD_CDC_TX_BUFSIZE 64
// TX is sent automatically every Start of Frame event.
// If not enabled, application must call tud_cdc_write_flush() periodically
#define CFG_TUD_CDC_FLUSH_ON_SOF 1
//--------------------------------------------------------------------+
// USB RAM PLACEMENT
//--------------------------------------------------------------------+

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@ -101,10 +101,6 @@
#define CFG_TUD_CDC_RX_BUFSIZE 64
#define CFG_TUD_CDC_TX_BUFSIZE 64
// TX is sent automatically every Start of Frame event.
// If not enabled, application must call tud_cdc_write_flush() periodically
#define CFG_TUD_CDC_FLUSH_ON_SOF 0
//--------------------------------------------------------------------
// MSC
//--------------------------------------------------------------------

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@ -101,10 +101,6 @@
#define CFG_TUD_CDC_RX_BUFSIZE 64
#define CFG_TUD_CDC_TX_BUFSIZE 64
// TX is sent automatically every Start of Frame event.
// If not enabled, application must call tud_cdc_write_flush() periodically
#define CFG_TUD_CDC_FLUSH_ON_SOF 0
//--------------------------------------------------------------------
// MSC
//--------------------------------------------------------------------

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@ -85,12 +85,6 @@
#define CFG_TUD_CDC_RX_BUFSIZE 128
#define CFG_TUD_CDC_TX_BUFSIZE 128
// TX is sent automatically in Start of Frame event.
// If not enabled, application must call tud_cdc_write_flush() periodically
#define CFG_TUD_CDC_FLUSH_ON_SOF 1
// Number of supported Logical Unit Number (At least 1)
#define CFG_TUD_MSC_MAXLUN 1

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@ -90,7 +90,7 @@ CFG_TUSB_ATTR_USBRAM static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
//--------------------------------------------------------------------+
bool tud_cdc_n_connected(uint8_t itf)
{
// DTR (bit 0) active isconsidered as connected
// DTR (bit 0) active is considered as connected
return BIT_TEST_(_cdcd_itf[itf].line_state, 0);
}
@ -348,14 +348,4 @@ tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
return TUSB_ERROR_NONE;
}
#if CFG_TUD_CDC_FLUSH_ON_SOF
void cdcd_sof(uint8_t rhport)
{
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
{
tud_cdc_n_flush(i);
}
}
#endif
#endif

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@ -116,12 +116,6 @@ tusb_error_t cdcd_control_request_st (uint8_t rhport, tusb_control_request_t con
tusb_error_t cdcd_xfer_cb (uint8_t rhport, uint8_t edpt_addr, tusb_event_t event, uint32_t xferred_bytes);
void cdcd_reset (uint8_t rhport);
#if CFG_TUD_CDC_FLUSH_ON_SOF
void cdcd_sof(uint8_t rhport);
#else
#define cdcd_sof NULL
#endif
#endif
#ifdef __cplusplus

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@ -261,10 +261,6 @@ void tusb_hal_nrf_power_event (uint32_t event)
NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
#if CFG_TUD_CDC && CFG_TUD_CDC_FLUSH_ON_SOF
NRF_USBD->INTENSET |= USBD_INTEN_SOF_Msk;
#endif
// Enable interrupt, Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice
NVIC_SetPriority(USBD_IRQn, USB_NVIC_PRIO);
NVIC_ClearPendingIRQ(USBD_IRQn);