Rework USB FIFO allocation scheme and allow RX FIFO size reduction
This commit is contained in:
Reinhard Panhuber
parent
e79a7b9152
commit
56c47188d8
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@ -139,15 +139,6 @@ typedef struct {
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uint8_t interval;
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} xfer_ctl_t;
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// EP size and transfer type report
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typedef struct TU_ATTR_PACKED {
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// The following format may look complicated but it is the most elegant way of addressing the required fields: EP number, EP direction, and EP transfer type.
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// The codes assigned to those fields, according to the USB specification, can be neatly used as indices.
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uint16_t ep_size[EP_MAX][2]; ///< dim 1: EP number, dim 2: EP direction denoted by TUSB_DIR_OUT (= 0) and TUSB_DIR_IN (= 1)
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bool ep_transfer_type[EP_MAX][2][4]; ///< dim 1: EP number, dim 2: EP direction, dim 3: transfer type, where 0 = Control, 1 = Isochronous, 2 = Bulk, and 3 = Interrupt
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///< I know very well that EP0 can only be used as control EP and we waste space here but for the sake of simplicity we accept that. It is used in a non-persistent way anyway!
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} ep_sz_tt_report_t;
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typedef volatile uint32_t * usb_fifo_t;
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xfer_ctl_t xfer_status[EP_MAX][2];
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@ -156,8 +147,9 @@ xfer_ctl_t xfer_status[EP_MAX][2];
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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// FIFO RAM allocation so far in words
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static uint16_t _allocated_fifo_words;
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
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static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
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static bool _rx_ep_closed;
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// Setup the control endpoint 0.
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static void bus_reset(uint8_t rhport)
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@ -170,6 +162,7 @@ static void bus_reset(uint8_t rhport)
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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tu_memclr(xfer_status, sizeof(xfer_status));
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_rx_ep_closed = false;
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for(uint8_t n = 0; n < EP_MAX; n++) {
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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@ -182,16 +175,28 @@ static void bus_reset(uint8_t rhport)
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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// The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
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// We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
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// between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
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// configuration done below.
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//
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// Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
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// All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
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// configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
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// opened when the host sends an additional command: setInterface. At this point in time
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// the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
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// an additional memory
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//
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// --------------- 320 or 1024 ( 1280 or 4096 bytes )
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// | IN FIFO 0 |
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// --------------- (320 or 1024) - 16
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// | IN FIFO 1 |
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// --------------- (320 or 1024) - 16 - x
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// | . . . . |
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// --------------- (320 or 1024) - 16 - x - y - ... - z
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// | IN FIFO MAX |
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// ---------------
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// | ... |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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// --------------- x + 16 + GRXFSIZ
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// | IN FIFO 1 |
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// --------------- 16 + GRXFSIZ
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// | IN FIFO 0 |
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// | FREE |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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@ -213,24 +218,20 @@ static void bus_reset(uint8_t rhport)
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// NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
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// of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
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//
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// FIXME: for Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
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// For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
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// are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
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// overwrite this.
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#if TUD_OPT_HIGH_SPEED
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_allocated_fifo_words = 271 + 2*EP_MAX;
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usb_otg->GRXFSIZ = 271 + 2*EP_MAX;
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#else
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_allocated_fifo_words = 47 + 2*EP_MAX;
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usb_otg->GRXFSIZ = 47 + 2*EP_MAX;
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#endif
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usb_otg->GRXFSIZ = _allocated_fifo_words;
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_allocated_fifo_words_tx += 16;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += 16;
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// TU_LOG2_INT(_allocated_fifo_words);
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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// Fixed control EP0 size to 64 bytes
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in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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@ -557,8 +558,22 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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xfer->max_size = desc_edpt->wMaxPacketSize.size;
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xfer->interval = desc_edpt->bInterval;
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uint16_t const fifo_size = tu_max16((desc_edpt->wMaxPacketSize.size + 3) / 4, 16); // Round up to next full word, minimum value must be 16
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if(dir == TUSB_DIR_OUT)
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{
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// Calculate required size of RX FIFO
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uint16_t size_rx = 15 + 2*fifo_size + 2*EP_MAX;
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// If size_rx needs to be extended check if possible and if so enlarge it
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if (usb_otg->GRXFSIZ < size_rx)
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{
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TU_ASSERT(size_rx + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
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// Enlarge RX FIFO
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usb_otg->GRXFSIZ = size_rx;
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}
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out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
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(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
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(desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
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@ -570,16 +585,28 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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// The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
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// We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
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// between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
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// configuration done below.
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//
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// Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
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// All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
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// configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
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// opened when the host sends an additional command: setInterface. At this point in time
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// the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
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// an additional memory
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//
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// --------------- 320 or 1024 ( 1280 or 4096 bytes )
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// | IN FIFO 0 |
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// --------------- (320 or 1024) - 16
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// | IN FIFO 1 |
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// --------------- (320 or 1024) - 16 - x
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// | . . . . |
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// --------------- (320 or 1024) - 16 - x - y - ... - z
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// | IN FIFO MAX |
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// ---------------
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// | ... |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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// --------------- x + 16 + GRXFSIZ
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// | IN FIFO 1 |
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// --------------- 16 + GRXFSIZ
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// | IN FIFO 0 |
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// | FREE |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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@ -592,29 +619,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// - Interrupt is EPSize
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// - Bulk/ISO is max(EPSize, remaining-fifo / non-opened-EPIN)
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uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
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uint16_t fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // +3 for rounding up to next full word
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// Check if free space is available
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TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
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if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
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{
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uint8_t opened = 0;
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for(uint8_t i = 0; i < EP_MAX; i++)
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{
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if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
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}
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// EP Size or equally divided of remaining whichever is larger
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fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
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}
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// FIFO overflows, we probably need a better allocating scheme
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TU_ASSERT(fifo_size <= fifo_remaining);
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_allocated_fifo_words_tx += fifo_size;
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// DIEPTXF starts at FIFO #1.
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// Both TXFD and TXSA are in unit of 32-bit words.
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += fifo_size;
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
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(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
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@ -728,9 +740,17 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
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{
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uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
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uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
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// For now only endpoint that has FIFO at the end of FIFO memory can be closed without fuss.
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TU_ASSERT(fifo_start + fifo_size == _allocated_fifo_words,);
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_allocated_fifo_words -= fifo_size;
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// For now only the last opened endpoint can be closed without fuss.
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TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
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_allocated_fifo_words_tx -= fifo_size;
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}
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else
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{
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// Update max_size
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xfer_status[epnum][TUSB_DIR_OUT].max_size = 0;
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// Set flag such that RX FIFO gets reduced in size one RX FIFO is empty
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_rx_ep_closed = true;
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}
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}
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@ -884,6 +904,24 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_
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TU_BREAKPOINT();
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break;
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}
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// If an OUT EP was closed update (reduce) the RX FIFO size if RX FIFO is empty - since this function handle_rxflvl_ints() gets looped from dcd_int_handler() until RX FIFO is empty it is guaranteed to be entered
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if (_rx_ep_closed && (usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL))
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{
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// Determine largest EP size for RX FIFO
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uint16_t sz = xfer_status[0][TUSB_DIR_OUT].max_size;
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for (uint8_t cnt = 1; cnt < EP_MAX; cnt++)
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{
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if (sz < xfer_status[cnt][TUSB_DIR_OUT].max_size) sz = xfer_status[cnt][TUSB_DIR_OUT].max_size;
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}
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// Update size of RX FIFO
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usb_otg->GRXFSIZ = 15 + 2*sz/4 + 2*EP_MAX; // sz was in bytes and is now needed in words
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// Disable flag
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_rx_ep_closed = false;
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}
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}
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static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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@ -1063,11 +1101,11 @@ void dcd_int_handler(uint8_t rhport)
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handle_epin_ints(rhport, dev, in_ep);
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}
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// // Check for Incomplete isochronous IN transfer
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// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
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// printf(" IISOIXFR!\r\n");
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//// TU_LOG2(" IISOIXFR!\r\n");
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// }
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// // Check for Incomplete isochronous IN transfer
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// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
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// printf(" IISOIXFR!\r\n");
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//// TU_LOG2(" IISOIXFR!\r\n");
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// }
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}
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#endif
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