adding lpcxpresso11u37 board
This commit is contained in:
hathach
parent
192a95a96e
commit
4ef3946a25
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@ -8,6 +8,9 @@ CFLAGS += \
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
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-D__USE_LPCOPEN
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# lpc_types.h cause following errors
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CFLAGS += -Wno-error=strict-prototypes
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/ea4088qs/lpc4088.ld
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@ -0,0 +1,46 @@
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m0 \
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-nostdlib \
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-DCORE_M0 \
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-D__VTOR_PRESENT=0 \
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-D__USE_LPCOPEN \
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-DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
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-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
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# startup.c and lpc_types.h cause following errors
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CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
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MCU_DIR = hw/mcu/nxp/lpc_driver/lpc11uxx
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/lpcxpresso11u37/lpc11u37.ld
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SRC_C += \
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$(MCU_DIR)/cr_startup_lpc11xx.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/chip_11xx.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/clock_11xx.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/gpio_11xx_1.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/iocon_11xx.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/sysctl_11xx.c \
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$(MCU_DIR)/lpc_chip_11uxx/src/sysinit_11xx.c
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INC += \
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$(TOP)/$(MCU_DIR)/lpc_chip_11uxx/inc
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# For TinyUSB port source
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VENDOR = nxp
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CHIP_FAMILY = lpc_ip3511
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM0
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# For flash-jlink target
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JLINK_DEVICE = LPC11U37/401
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JLINK_IF = swd
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# flash using pyocd
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flash: $(BUILD)/$(BOARD)-firmware.hex
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pyocd flash -t lpc11u37 $<
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@ -0,0 +1,195 @@
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/*
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* GENERATED FILE - DO NOT EDIT
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* Copyright (c) 2008-2013 Code Red Technologies Ltd,
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* Copyright 2015, 2018-2019 NXP
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* (c) NXP Semiconductors 2013-2019
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* Generated linker script file for LPC11U37/401
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Sep 6, 2019 12:16:06 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
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RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
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RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
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}
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/* Define a symbol for the top of each memory region */
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__base_MFlash128 = 0x0 ; /* MFlash128 */
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__base_Flash = 0x0 ; /* Flash */
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__top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
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__top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
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__base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
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__base_RAM = 0x10000000 ; /* RAM */
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__top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
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__top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
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__base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
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__base_RAM2 = 0x20004000 ; /* RAM2 */
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__top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
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__top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
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ENTRY(ResetISR)
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SECTIONS
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{
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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} > MFlash128
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > MFlash128
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > MFlash128
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__exidx_start = .;
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.ARM.exidx : ALIGN(4)
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > MFlash128
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__exidx_end = .;
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_etext = .;
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/* DATA section for RamUsb2 */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$RamUsb2)
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*(.data.$RAM2)
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*(.data.$RamUsb2)
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*(.data.$RAM2.*)
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*(.data.$RamUsb2.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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} > RamUsb2 AT>MFlash128
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/* MAIN DATA SECTION */
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.uninit_RESERVED (NOLOAD) :
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{
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. = ALIGN(4) ;
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KEEP(*(.bss.$RESERVED*))
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. = ALIGN(4) ;
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_end_uninit_RESERVED = .;
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} > RamLoc8
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/* Main DATA section (RamLoc8) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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*(vtable)
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*(.ramfunc*)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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} > RamLoc8 AT>MFlash128
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/* BSS section for RamUsb2 */
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.bss_RAM2 :
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{
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. = ALIGN(4) ;
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PROVIDE(__start_bss_RAM2 = .) ;
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*(.bss.$RAM2)
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*(.bss.$RamUsb2)
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*(.bss.$RAM2.*)
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*(.bss.$RamUsb2.*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM2 = .) ;
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} > RamUsb2
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/* MAIN BSS SECTION */
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.bss :
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{
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. = ALIGN(4) ;
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_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4) ;
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_ebss = .;
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PROVIDE(end = .);
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} > RamLoc8
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/* NOINIT section for RamUsb2 */
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.noinit_RAM2 (NOLOAD) :
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{
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. = ALIGN(4) ;
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*(.noinit.$RAM2)
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*(.noinit.$RamUsb2)
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*(.noinit.$RAM2.*)
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*(.noinit.$RamUsb2.*)
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. = ALIGN(4) ;
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} > RamUsb2
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/* DEFAULT NOINIT SECTION */
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.noinit (NOLOAD):
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{
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. = ALIGN(4) ;
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_noinit = .;
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*(.noinit*)
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. = ALIGN(4) ;
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_end_noinit = .;
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} > RamLoc8
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PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
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PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
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/* ## Create checksum value (used in startup) ## */
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PROVIDE(__valid_user_code_checksum = 0 -
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(_vStackTop
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+ (ResetISR + 1)
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+ (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
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+ (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
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)
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);
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/* Provide basic symbols giving location and size of main text
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* block, including initial values of RW data sections. Note that
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* these will need extending to give a complete picture with
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* complex images (e.g multiple Flash banks).
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*/
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_image_start = LOADADDR(.text);
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_image_end = LOADADDR(.data) + SIZEOF(.data);
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_image_size = _image_end - _image_start;
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}
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@ -0,0 +1,200 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "chip.h"
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#include "../board.h"
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#define LED_PORT 1
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#define LED_PIN 0
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#define LED_STATE_ON 0
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// Wake up Switch
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#define BUTTON_PORT 0
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#define BUTTON_PIN 16
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#define BUTTON_STATE_ACTIVE 0
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/* System oscillator rate and RTC oscillator rate */
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const uint32_t OscRateIn = 12000000;
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const uint32_t RTCOscRateIn = 32768;
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/* Pin muxing table, only items that need changing from their default pin
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state are in this table. Not every pin is mapped. */
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/* IOCON pin definitions for pin muxing */
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typedef struct {
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uint32_t port : 8; /* Pin port */
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uint32_t pin : 8; /* Pin number */
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uint32_t modefunc : 16; /* Function and mode */
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} PINMUX_GRP_T;
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static const PINMUX_GRP_T pinmuxing[] =
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{
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{0, 3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
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{0, 6, (IOCON_FUNC1 | IOCON_MODE_INACT)}, /* PIO0_6 used for USB_CONNECT */
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{0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
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{0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
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};
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/* Setup system clocking */
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static void SystemSetupClocking(void)
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{
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volatile int i;
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/* Powerup main oscillator */
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Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
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/* Wait 200us for OSC to be stablized, no status
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indication, dummy wait. */
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for (i = 0; i < 0x100; i++) {}
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/* Set system PLL input to main oscillator */
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Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
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/* Power down PLL to change the PLL divider ratio */
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Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
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/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
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MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
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FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
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FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
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Chip_Clock_SetupSystemPLL(3, 1);
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/* Powerup system PLL */
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Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
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/* Wait for PLL to lock */
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while (!Chip_Clock_IsSystemPLLLocked()) {}
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/* Set system clock divider to 1 */
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Chip_Clock_SetSysClockDiv(1);
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/* Setup FLASH access to 3 clocks */
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Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
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/* Set main clock source to the system PLL. This will drive 48MHz
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for the main clock and 48MHz for the system clock */
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Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
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/* Set USB PLL input to main oscillator */
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Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
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/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
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MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
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FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
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FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
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Chip_Clock_SetupUSBPLL(3, 1);
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/* Powerup USB PLL */
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Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
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/* Wait for PLL to lock */
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while (!Chip_Clock_IsUSBPLLLocked()) {}
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}
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// Invoked by startup code
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void SystemInit(void)
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{
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SystemSetupClocking();
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
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/* Enable IOCON clock */
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
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for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++)
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{
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Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
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}
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}
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void board_init(void)
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{
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SystemCoreClockUpdate();
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#if CFG_TUSB_OS == OPT_OS_NONE
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// 1ms tick timer
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SysTick_Config(SystemCoreClock / 1000);
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#elif CFG_TUSB_OS == OPT_OS_FREERTOS
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
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NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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#endif
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Chip_GPIO_Init(LPC_GPIO);
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// LED
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Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
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// Button
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Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
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// USB: Setup PLL clock, and power
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/* enable USB main clock */
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Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
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/* Enable AHB clock to the USB block and USB RAM. */
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
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/* power UP USB Phy */
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Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state)
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{
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Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
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}
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uint32_t board_button_read(void)
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{
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return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
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}
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int board_uart_read(uint8_t* buf, int len)
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{
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(void) buf;
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(void) len;
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return 0;
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}
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int board_uart_write(void const * buf, int len)
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{
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(void) buf;
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(void) len;
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return 0;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void SysTick_Handler (void)
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{
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system_ticks++;
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}
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uint32_t board_millis(void)
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{
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return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
#define LED_PIN 17
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
// Wake up Swtich
|
||||
// Wake up Switch
|
||||
#define BUTTON_PORT 0
|
||||
#define BUTTON_PIN 16
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ CFLAGS += \
|
|||
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
|
||||
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
|
||||
|
||||
# startup.c and lpc_types.h cause following errors
|
||||
CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/lpcxpresso1347/lpc1347.ld
|
||||
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ ResetISR(void) {
|
|||
bss_init ((unsigned int)ExeAddr, SectionLen);
|
||||
#endif
|
||||
|
||||
// extern void SystemInit(void);
|
||||
extern void SystemInit(void);
|
||||
SystemInit();
|
||||
|
||||
#if defined (__cplusplus)
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ CFLAGS += \
|
|||
-DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
|
||||
-DRTC_EV_SUPPORT=0
|
||||
|
||||
# lpc_types.h cause following errors
|
||||
CFLAGS += -Wno-error=strict-prototypes
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/lpcxpresso1769/lpc1769.ld
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ CFLAGS += \
|
|||
-DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
|
||||
-DRTC_EV_SUPPORT=0
|
||||
|
||||
# startup.c and lpc_types.h cause following errors
|
||||
CFLAGS += -Wno-error=nested-externs -Wno-error=strict-prototypes
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/mbed1768/lpc1768.ld
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,9 @@ CFLAGS += \
|
|||
-DCFG_TUSB_MCU=OPT_MCU_LPC18XX \
|
||||
-D__USE_LPCOPEN
|
||||
|
||||
# lpc_types.h cause following errors
|
||||
CFLAGS += -Wno-error=strict-prototypes
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/mcb1800/lpc1857.ld
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 42dac0b08d94986bd5423c6327b097fec0c47911
|
||||
Subproject commit 675b41620db763f89bdbe946cbfb7a9e8f27d42b
|
||||
Loading…
Reference in New Issue