Merge remote-tracking branch 'upstream/master' into edpt_ISO_xfer
This commit is contained in:
commit
485d8fa77e
|
@ -86,6 +86,7 @@ This code base already had supported for a handful of following boards (sorted a
|
|||
- [LPCXpresso 54114](https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso54114-board:OM13089)
|
||||
- [LPCXpresso 55s69 EVK](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK)
|
||||
- [NGX LPC4330-Xplorer](https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027)
|
||||
- [Double M33 Express](https://www.crowdsupply.com/steiert-solutions/double-m33-express)
|
||||
|
||||
### Sony
|
||||
|
||||
|
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b191008
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
|
||||
RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000200
|
||||
m_text (RX) : ORIGIN = 0x00010200, LENGTH = 0x0007FE00
|
||||
m_core1_image (RX) : ORIGIN = 0x00090000, LENGTH = 0x00008000
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE
|
||||
rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
|
||||
m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* section for storing the secondary core image */
|
||||
.m0code :
|
||||
{
|
||||
. = ALIGN(4) ;
|
||||
KEEP (*(.m0code))
|
||||
*(.m0code*)
|
||||
. = ALIGN(4) ;
|
||||
} > m_core1_image
|
||||
|
||||
/* NOINIT section for rpmsg_sh_mem */
|
||||
.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
__RPMSG_SH_MEM_START__ = .;
|
||||
*(.noinit.$rpmsg_sh_mem*)
|
||||
. = ALIGN(4) ;
|
||||
__RPMSG_SH_MEM_END__ = .;
|
||||
} > rpmsg_sh_mem
|
||||
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.ramfunc*) /* for functions in ram */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
m_usb_bdt (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(512);
|
||||
*(m_usb_bdt)
|
||||
} > m_usb_sram
|
||||
|
||||
m_usb_global (NOLOAD) :
|
||||
{
|
||||
*(m_usb_global)
|
||||
} > m_usb_sram
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
CFLAGS += \
|
||||
-flto \
|
||||
-mthumb \
|
||||
-mabi=aapcs \
|
||||
-mcpu=cortex-m33 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-sp-d16 \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
|
||||
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
|
||||
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
|
||||
|
||||
MCU_DIR = hw/mcu/nxp/sdk/devices/LPC55S69
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/$(BOARD)/LPC55S69_cm33_core0_uf2.ld
|
||||
|
||||
SRC_C += \
|
||||
$(MCU_DIR)/system_LPC55S69_cm33_core0.c \
|
||||
$(MCU_DIR)/drivers/fsl_clock.c \
|
||||
$(MCU_DIR)/drivers/fsl_gpio.c \
|
||||
$(MCU_DIR)/drivers/fsl_power.c \
|
||||
$(MCU_DIR)/drivers/fsl_reset.c \
|
||||
$(MCU_DIR)/drivers/fsl_usart.c \
|
||||
$(MCU_DIR)/drivers/fsl_flexcomm.c
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
|
||||
$(TOP)/$(MCU_DIR) \
|
||||
$(TOP)/$(MCU_DIR)/drivers
|
||||
|
||||
SRC_S += $(MCU_DIR)/gcc/startup_LPC55S69_cm33_core0.S
|
||||
|
||||
LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
|
||||
|
||||
# For TinyUSB port source
|
||||
VENDOR = nxp
|
||||
CHIP_FAMILY = lpc_ip3511
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM33_NTZ/non_secure
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC55S69
|
||||
|
||||
# flash using pyocd
|
||||
flash: $(BUILD)/$(BOARD)-firmware.hex
|
||||
pyocd flash -t LPC55S69 $<
|
|
@ -0,0 +1,400 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2018, hathach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include "../board.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_iocon.h"
|
||||
#include "fsl_sctimer.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void USB0_IRQHandler(void)
|
||||
{
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
void USB1_IRQHandler(void)
|
||||
{
|
||||
tud_int_handler(1);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
#define LED_PORT 0
|
||||
#define LED_PIN 1
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
// WAKE button
|
||||
#define BUTTON_PORT 0
|
||||
#define BUTTON_PIN 5
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
// Number of neopixels
|
||||
#define NEOPIXEL_NUMBER 2
|
||||
#define NEOPIXEL_PORT 0
|
||||
#define NEOPIXEL_PIN 27
|
||||
|
||||
// UART
|
||||
#define UART_DEV USART0
|
||||
|
||||
// IOCON pin mux
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
|
||||
#define IOCON_PIO_FUNC4 0x04u /*!<@brief Selects pin function 4 */
|
||||
#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) /*!<@brief Digital pin function 0 enabled */
|
||||
#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) /*!<@brief Digital pin function 1 enabled */
|
||||
#define IOCON_PIO_DIG_FUNC4_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) /*!<@brief Digital pin function 2 enabled */
|
||||
#define IOCON_PIO_DIG_FUNC7_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) /*!<@brief Digital pin function 2 enabled */
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Neopixel Driver
|
||||
//--------------------------------------------------------------------+
|
||||
#define NEO_SCT SCT0
|
||||
#define NEO_MATCH_PERIOD 0
|
||||
#define NEO_MATCH_0 1
|
||||
#define NEO_MATCH_1 2
|
||||
#define NEO_EVENT_RISE 2
|
||||
#define NEO_EVENT_FALL_0 0
|
||||
#define NEO_EVENT_FALL_1 1
|
||||
#define NEO_EVENT_NEXT 3
|
||||
#define NEO_EVENT_START 4
|
||||
#define NEO_SCT_OUTPUT 6
|
||||
#define NEO_STATE_IDLE 24
|
||||
//#define NEO_ARRAY_SIZE (3 * NEOPIXEL_NUMBER)
|
||||
|
||||
//volatile uint32_t _neopixel_array[NEO_ARRAY_SIZE] = {0x10, 0x20, 0x30, 0x40, 0x50, 0x60};
|
||||
volatile uint32_t _neopixel_array[NEOPIXEL_NUMBER] = {0x404040, 0x202020};
|
||||
volatile uint32_t _neopixel_count = 0;
|
||||
|
||||
void neopixel_int_handler(void){
|
||||
uint32_t eventFlag = NEO_SCT->EVFLAG;
|
||||
if (eventFlag & (1 << NEO_EVENT_NEXT)) {
|
||||
_neopixel_count += 1;
|
||||
if (_neopixel_count < (NEOPIXEL_NUMBER)) {
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFFFFFF & (~_neopixel_array[_neopixel_count]);
|
||||
NEO_SCT->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
|
||||
}
|
||||
}
|
||||
NEO_SCT->EVFLAG = eventFlag;
|
||||
}
|
||||
|
||||
void SCT0_DriverIRQHandler(void){
|
||||
neopixel_int_handler();
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
void neopixel_set(uint32_t pixel, uint32_t color){
|
||||
if (pixel < NEOPIXEL_NUMBER) {
|
||||
_neopixel_array[pixel] = color;
|
||||
}
|
||||
}
|
||||
|
||||
void neopixel_update(void){
|
||||
// while (NEO_SCT->CTRL & SCT_CTRL_HALT_L_MASK);
|
||||
_neopixel_count = 0;
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFFFFFF & (~_neopixel_array[0]);
|
||||
NEO_SCT->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
void neopixel_int_handler(void){
|
||||
uint32_t eventFlag = NEO_SCT->EVFLAG;
|
||||
// if ((eventFlag & (1 << NEO_EVENT_NEXT)) && (_neopixel_count < (NEO_ARRAY_SIZE))) {
|
||||
// NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFF & (~_neopixel_array[_neopixel_count]);
|
||||
if ((eventFlag & (1 << NEO_EVENT_NEXT)) && (_neopixel_count < (NEOPIXEL_NUMBER))) {
|
||||
_neopixel_count += 1;
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFFFFFF & (~_neopixel_array[_neopixel_count]);
|
||||
NEO_SCT->EVFLAG = eventFlag;
|
||||
NEO_SCT->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
|
||||
} else {
|
||||
NEO_SCT->EVFLAG = eventFlag;
|
||||
}
|
||||
}
|
||||
|
||||
void SCT0_DriverIRQHandler(void){
|
||||
neopixel_int_handler();
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
void neopixel_update(uint32_t pixel, uint32_t color){
|
||||
if (pixel < NEOPIXEL_NUMBER) {
|
||||
_neopixel_array[pixel] = color;
|
||||
_neopixel_count = 0;
|
||||
// NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFF & (~_neopixel_array[0]);
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0xFFFFFF & (~_neopixel_array[0]);
|
||||
NEO_SCT->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
|
||||
}
|
||||
}
|
||||
*/
|
||||
void neopixel_init(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Sct0);
|
||||
RESET_PeripheralReset(kSCT0_RST_SHIFT_RSTn);
|
||||
|
||||
NEO_SCT->CONFIG = (
|
||||
SCT_CONFIG_UNIFY(1) |
|
||||
SCT_CONFIG_CLKMODE(kSCTIMER_System_ClockMode) |
|
||||
SCT_CONFIG_NORELOAD_L(1) );
|
||||
NEO_SCT->CTRL = (
|
||||
SCT_CTRL_HALT_L(1) |
|
||||
SCT_CTRL_CLRCTR_L(1) );
|
||||
|
||||
NEO_SCT->MATCH[NEO_MATCH_PERIOD] = 120;
|
||||
NEO_SCT->MATCH[NEO_MATCH_0] = 30;
|
||||
NEO_SCT->MATCH[NEO_MATCH_1] = 60;
|
||||
NEO_SCT->EV[NEO_EVENT_START].STATE = (1 << NEO_STATE_IDLE);
|
||||
NEO_SCT->EV[NEO_EVENT_START].CTRL = (
|
||||
kSCTIMER_OutputLowEvent | SCT_EV_CTRL_IOSEL(NEO_SCT_OUTPUT) |
|
||||
SCT_EV_CTRL_STATELD(1) | SCT_EV_CTRL_STATEV(23));
|
||||
// NEO_SCT->EV[NEO_EVENT_RISE].STATE = 0xFE;
|
||||
NEO_SCT->EV[NEO_EVENT_RISE].STATE = 0xFFFFFE;
|
||||
NEO_SCT->EV[NEO_EVENT_RISE].CTRL = (
|
||||
kSCTIMER_MatchEventOnly | SCT_EV_CTRL_MATCHSEL(NEO_MATCH_PERIOD) |
|
||||
SCT_EV_CTRL_STATELD(0) | SCT_EV_CTRL_STATEV(31));
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].STATE = 0x0;
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_0].CTRL = (
|
||||
kSCTIMER_MatchEventOnly | SCT_EV_CTRL_MATCHSEL(NEO_MATCH_0) |
|
||||
SCT_EV_CTRL_STATELD(0) );
|
||||
// NEO_SCT->EV[NEO_EVENT_FALL_1].STATE = 0xFF;
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_1].STATE = 0xFFFFFF;
|
||||
NEO_SCT->EV[NEO_EVENT_FALL_1].CTRL = (
|
||||
kSCTIMER_MatchEventOnly | SCT_EV_CTRL_MATCHSEL(NEO_MATCH_1) |
|
||||
SCT_EV_CTRL_STATELD(0) );
|
||||
NEO_SCT->EV[NEO_EVENT_NEXT].STATE = 0x1;
|
||||
NEO_SCT->EV[NEO_EVENT_NEXT].CTRL = (
|
||||
kSCTIMER_MatchEventOnly | SCT_EV_CTRL_MATCHSEL(NEO_MATCH_PERIOD) |
|
||||
SCT_EV_CTRL_STATELD(1) | SCT_EV_CTRL_STATEV(NEO_STATE_IDLE));
|
||||
|
||||
NEO_SCT->LIMIT = (1 << NEO_EVENT_START) | (1 << NEO_EVENT_RISE) | (1 << NEO_EVENT_NEXT);
|
||||
NEO_SCT->HALT = (1 << NEO_EVENT_NEXT);
|
||||
NEO_SCT->START = (1 << NEO_EVENT_START);
|
||||
|
||||
NEO_SCT->OUT[NEO_SCT_OUTPUT].SET = (1 << NEO_EVENT_START) | (1 << NEO_EVENT_RISE);
|
||||
NEO_SCT->OUT[NEO_SCT_OUTPUT].CLR = (1 << NEO_EVENT_FALL_0) | (1 << NEO_EVENT_FALL_1) | (1 << NEO_EVENT_NEXT);
|
||||
|
||||
NEO_SCT->STATE = NEO_STATE_IDLE;
|
||||
NEO_SCT->OUTPUT = 0x0;
|
||||
NEO_SCT->RES = SCT_RES_O6RES(0x2);
|
||||
NEO_SCT->EVEN = (1 << NEO_EVENT_NEXT);
|
||||
EnableIRQ(SCT0_IRQn);
|
||||
|
||||
neopixel_set(0, 0x101000);
|
||||
neopixel_set(1, 0x101000);
|
||||
neopixel_update();
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
name: BOARD_BootClockFROHF96M
|
||||
outputs:
|
||||
- {id: SYSTICK_clock.outFreq, value: 96 MHz}
|
||||
- {id: System_clock.outFreq, value: 96 MHz}
|
||||
settings:
|
||||
- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
|
||||
sources:
|
||||
- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
|
||||
******************************************************************/
|
||||
void BootClockFROHF96M(void)
|
||||
{
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Set up FRO */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
|
||||
accidentally being below the voltage for current speed */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
|
||||
|
||||
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*!< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = 96000000U;
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
// Enable IOCON clock
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
// Init 96 MHz clock
|
||||
BootClockFROHF96M();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
GPIO_PortInit(GPIO, 0);
|
||||
GPIO_PortInit(GPIO, 1);
|
||||
|
||||
// LED
|
||||
/* PORT0 PIN1 configured as PIO0_1 */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 1U, IOCON_PIO_DIG_FUNC0_EN);
|
||||
|
||||
gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 1};
|
||||
GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
|
||||
|
||||
// Neopixel
|
||||
/* PORT0 PIN27 configured as SCT0_OUT6 */
|
||||
IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
|
||||
|
||||
neopixel_init();
|
||||
|
||||
// Button
|
||||
/* PORT0 PIN5 configured as PIO0_5 */
|
||||
IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
|
||||
|
||||
gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
|
||||
GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
|
||||
|
||||
// UART
|
||||
/* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 29U, IOCON_PIO_DIG_FUNC1_EN);
|
||||
/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 30U, IOCON_PIO_DIG_FUNC1_EN);
|
||||
|
||||
#if defined(UART_DEV) && CFG_TUSB_DEBUG
|
||||
// Enable UART when debug log is on
|
||||
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
|
||||
usart_config_t uart_config;
|
||||
USART_GetDefaultConfig(&uart_config);
|
||||
uart_config.baudRate_Bps = BOARD_UART_BAUDRATE;
|
||||
uart_config.enableTx = true;
|
||||
uart_config.enableRx = true;
|
||||
USART_Init(UART_DEV, &uart_config, 12000000);
|
||||
#endif
|
||||
|
||||
// USB VBUS
|
||||
/* PORT0 PIN22 configured as USB0_VBUS */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
|
||||
|
||||
// USB Controller
|
||||
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB0 Phy */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*< Turn on USB1 Phy */
|
||||
|
||||
/* reset the IP to make sure it's in reset state. */
|
||||
RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
|
||||
RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
|
||||
|
||||
#if (defined CFG_TUSB_RHPORT1_MODE) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
|
||||
CLOCK_EnableClock(kCLOCK_Usbh1);
|
||||
/* Put PHY powerdown under software control */
|
||||
USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
|
||||
/* According to reference mannual, device mode setting has to be set by access usb host register */
|
||||
USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
|
||||
/* enable usb1 host clock */
|
||||
CLOCK_DisableClock(kCLOCK_Usbh1);
|
||||
#endif
|
||||
|
||||
#if (defined CFG_TUSB_RHPORT0_MODE) && (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
|
||||
// Enable USB Clock Adjustments to trim the FRO for the full speed controller
|
||||
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
|
||||
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
|
||||
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
|
||||
/* enable usb0 host clock */
|
||||
CLOCK_EnableClock(kCLOCK_Usbhsl0);
|
||||
/*According to reference mannual, device mode setting has to be set by access usb host register */
|
||||
USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
|
||||
/* disable usb0 host clock */
|
||||
CLOCK_DisableClock(kCLOCK_Usbhsl0);
|
||||
CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB Device clock */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
if (state) {
|
||||
neopixel_set(0, 0x100000);
|
||||
neopixel_set(1, 0x101010);
|
||||
} else {
|
||||
neopixel_set(0, 0x001000);
|
||||
neopixel_set(1, 0x000010);
|
||||
}
|
||||
neopixel_update();
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
// active low
|
||||
return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const * buf, int len)
|
||||
{
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
|
@ -46,7 +46,7 @@
|
|||
#endif
|
||||
|
||||
#ifndef CFG_TUD_HID_EP_BUFSIZE
|
||||
#define CFG_TUD_HID_EP_BUFSIZE 16
|
||||
#define CFG_TUD_HID_EP_BUFSIZE 64
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
|
|
|
@ -1103,6 +1103,24 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
|
|||
{
|
||||
TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, desc_ep->wMaxPacketSize.size);
|
||||
|
||||
if (TUSB_XFER_ISOCHRONOUS == desc_ep->bmAttributes.xfer)
|
||||
{
|
||||
TU_ASSERT(desc_ep->wMaxPacketSize.size <= (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023));
|
||||
}
|
||||
else
|
||||
{
|
||||
uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 512 : 64);
|
||||
|
||||
if (TUSB_XFER_BULK == desc_ep->bmAttributes.xfer)
|
||||
{
|
||||
// Bulk must be EXACTLY 512/64 bytes
|
||||
TU_ASSERT(desc_ep->wMaxPacketSize.size == max_epsize);
|
||||
}else
|
||||
{
|
||||
TU_ASSERT(desc_ep->wMaxPacketSize.size <= max_epsize);
|
||||
}
|
||||
}
|
||||
|
||||
return dcd_edpt_open(rhport, desc_ep);
|
||||
}
|
||||
|
||||
|
|
|
@ -664,7 +664,7 @@ static void handle_bus_reset(void)
|
|||
(void)USB->USB_ALTEV_REG;
|
||||
_dcd.in_reset = true;
|
||||
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
USB->USB_DMA_CTRL_REG = 0;
|
||||
|
||||
USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
|
||||
|
@ -821,14 +821,13 @@ void dcd_disconnect(uint8_t rhport)
|
|||
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
{
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
|
||||
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
|
||||
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
|
||||
uint8_t iso_mask = 0;
|
||||
|
||||
(void)rhport;
|
||||
|
||||
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 1023);
|
||||
TU_ASSERT(epnum < EP_MAX);
|
||||
|
||||
xfer->max_packet_size = desc_edpt->wMaxPacketSize.size;
|
||||
|
|
|
@ -252,7 +252,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
|
|||
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
|
||||
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
|
||||
|
||||
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
|
||||
TU_ASSERT(epnum < EP_MAX);
|
||||
|
||||
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
|
||||
|
|
|
@ -37,14 +37,23 @@
|
|||
/* MACRO TYPEDEF CONSTANT ENUM
|
||||
*------------------------------------------------------------------*/
|
||||
static TU_ATTR_ALIGNED(4) UsbDeviceDescBank sram_registers[8][2];
|
||||
static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8];
|
||||
|
||||
// Setup packet is only 8 bytes in length. However under certain scenario,
|
||||
// USB DMA controller may decide to overwrite/overflow the buffer with
|
||||
// 2 extra bytes of CRC. From datasheet's "Management of SETUP Transactions" section
|
||||
// If the number of received data bytes is the maximum data payload specified by
|
||||
// PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer.
|
||||
// If the number of received data is equal or less than the data payload specified
|
||||
// by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
|
||||
// Therefore we will need to increase it to 10 bytes here.
|
||||
static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8+2];
|
||||
|
||||
// ready for receiving SETUP packet
|
||||
static inline void prepare_setup(void)
|
||||
{
|
||||
// Only make sure the EP0 OUT buffer is ready
|
||||
sram_registers[0][0].ADDR.reg = (uint32_t) _setup_packet;
|
||||
sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(_setup_packet);
|
||||
sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(tusb_control_request_t);
|
||||
sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0;
|
||||
}
|
||||
|
||||
|
@ -378,7 +387,7 @@ void dcd_int_handler (uint8_t rhport)
|
|||
USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND;
|
||||
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
// Handle SETUP packet
|
||||
|
|
|
@ -338,7 +338,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
if (intr_status & UDP_ISR_ENDBUSRES_Msk)
|
||||
{
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
// SOF
|
||||
|
|
|
@ -533,7 +533,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
if ( int_status & USBD_INTEN_USBRESET_Msk )
|
||||
{
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
// ISOIN: Data was moved to endpoint buffer, client will be notified in SOF
|
||||
|
|
|
@ -329,8 +329,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
USBD->ATTR |= USBD_ATTR_USB_EN_Msk | USBD_ATTR_PHY_EN_Msk;
|
||||
|
||||
bus_reset();
|
||||
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
if(state & USBD_STATE_SUSPEND)
|
||||
|
|
|
@ -340,7 +340,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
|
||||
bus_reset();
|
||||
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
if(state & USBD_ATTR_SUSPEND_Msk)
|
||||
|
|
|
@ -224,7 +224,7 @@ static void process_bus_reset(uint8_t rhport)
|
|||
_dcd.addr = 0;
|
||||
prepare_next_setup_packet(rhport);
|
||||
KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
static void process_bus_inactive(uint8_t rhport)
|
||||
|
|
|
@ -471,7 +471,7 @@ static void bus_event_isr(uint8_t rhport)
|
|||
if (dev_status & SIE_DEV_STATUS_RESET_MASK)
|
||||
{
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
if (dev_status & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)
|
||||
|
|
|
@ -243,7 +243,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
|
|||
(void) rhport;
|
||||
|
||||
// TODO not support ISO yet
|
||||
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
|
||||
TU_VERIFY(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
|
||||
|
||||
//------------- Prepare Queue Head -------------//
|
||||
uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
|
||||
|
@ -357,7 +357,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
|
||||
{
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
|
||||
|
|
|
@ -547,7 +547,7 @@ void dcd_int_handler(uint8_t rhport) {
|
|||
// USBRST is start of reset.
|
||||
clear_istr_bits(USB_ISTR_RESET);
|
||||
dcd_handle_bus_reset();
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
return; // Don't do the rest of the things here; perhaps they've been cleared?
|
||||
}
|
||||
|
||||
|
|
|
@ -46,13 +46,13 @@
|
|||
#define STM32L4_SYNOPSYS
|
||||
#endif
|
||||
|
||||
#if TUSB_OPT_DEVICE_ENABLED && \
|
||||
#if TUSB_OPT_DEVICE_ENABLED && \
|
||||
( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
|
||||
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
|
||||
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
|
||||
)
|
||||
|
||||
// EP_MAX : Max number of bi-directional endpoints including EP0
|
||||
|
@ -116,6 +116,7 @@
|
|||
#define EP_FIFO_SIZE EP_FIFO_SIZE_HS
|
||||
#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE
|
||||
#define RHPORT_IRQn OTG_HS_IRQn
|
||||
|
||||
#endif
|
||||
|
||||
#define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
|
||||
|
@ -141,25 +142,40 @@ typedef struct {
|
|||
uint8_t interval;
|
||||
} xfer_ctl_t;
|
||||
|
||||
// EP size and transfer type report
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
// The following format may look complicated but it is the most elegant way of addressing the required fields: EP number, EP direction, and EP transfer type.
|
||||
// The codes assigned to those fields, according to the USB specification, can be neatly used as indices.
|
||||
uint16_t ep_size[EP_MAX][2]; ///< dim 1: EP number, dim 2: EP direction denoted by TUSB_DIR_OUT (= 0) and TUSB_DIR_IN (= 1)
|
||||
bool ep_transfer_type[EP_MAX][2][4]; ///< dim 1: EP number, dim 2: EP direction, dim 3: transfer type, where 0 = Control, 1 = Isochronous, 2 = Bulk, and 3 = Interrupt
|
||||
///< I know very well that EP0 can only be used as control EP and we waste space here but for the sake of simplicity we accept that. It is used in a non-persistent way anyway!
|
||||
} ep_sz_tt_report_t;
|
||||
|
||||
typedef volatile uint32_t * usb_fifo_t;
|
||||
|
||||
xfer_ctl_t xfer_status[EP_MAX][2];
|
||||
#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
|
||||
|
||||
// EP0 transfers are limited to 1 packet - larger sizes has to be split
|
||||
static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
|
||||
static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
|
||||
|
||||
// FIFO RAM allocation so far in words
|
||||
static uint16_t _allocated_fifo_words;
|
||||
// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
|
||||
static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
|
||||
static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size)
|
||||
|
||||
// Calculate the RX FIFO size according to recommendations from reference manual
|
||||
static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
|
||||
{
|
||||
return 15 + 2*(ep_size/4) + 2*EP_MAX;
|
||||
}
|
||||
|
||||
static void update_grxfsiz(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
|
||||
|
||||
// Determine largest EP size for RX FIFO
|
||||
uint16_t max_epsize = 0;
|
||||
for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
|
||||
{
|
||||
max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
|
||||
}
|
||||
|
||||
// Update size of RX FIFO
|
||||
usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
|
||||
}
|
||||
|
||||
// Setup the control endpoint 0.
|
||||
static void bus_reset(uint8_t rhport)
|
||||
|
@ -172,6 +188,7 @@ static void bus_reset(uint8_t rhport)
|
|||
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
|
||||
|
||||
tu_memclr(xfer_status, sizeof(xfer_status));
|
||||
_out_ep_closed = false;
|
||||
|
||||
for(uint8_t n = 0; n < EP_MAX; n++) {
|
||||
out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
||||
|
@ -184,16 +201,28 @@ static void bus_reset(uint8_t rhport)
|
|||
// "USB Data FIFOs" section in reference manual
|
||||
// Peripheral FIFO architecture
|
||||
//
|
||||
// The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
|
||||
// We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
|
||||
// between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
|
||||
// configuration done below.
|
||||
//
|
||||
// Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
|
||||
// All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
|
||||
// configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
|
||||
// opened when the host sends an additional command: setInterface. At this point in time
|
||||
// the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
|
||||
// an additional memory
|
||||
//
|
||||
// --------------- 320 or 1024 ( 1280 or 4096 bytes )
|
||||
// | IN FIFO 0 |
|
||||
// --------------- (320 or 1024) - 16
|
||||
// | IN FIFO 1 |
|
||||
// --------------- (320 or 1024) - 16 - x
|
||||
// | . . . . |
|
||||
// --------------- (320 or 1024) - 16 - x - y - ... - z
|
||||
// | IN FIFO MAX |
|
||||
// ---------------
|
||||
// | ... |
|
||||
// --------------- y + x + 16 + GRXFSIZ
|
||||
// | IN FIFO 2 |
|
||||
// --------------- x + 16 + GRXFSIZ
|
||||
// | IN FIFO 1 |
|
||||
// --------------- 16 + GRXFSIZ
|
||||
// | IN FIFO 0 |
|
||||
// | FREE |
|
||||
// --------------- GRXFSIZ
|
||||
// | OUT FIFO |
|
||||
// | ( Shared ) |
|
||||
|
@ -215,24 +244,16 @@ static void bus_reset(uint8_t rhport)
|
|||
// NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
|
||||
// of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
|
||||
//
|
||||
// FIXME: for Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
|
||||
// For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
|
||||
// are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
|
||||
// overwrite this.
|
||||
|
||||
#if TUD_OPT_HIGH_SPEED
|
||||
_allocated_fifo_words = 271 + 2*EP_MAX;
|
||||
#else
|
||||
_allocated_fifo_words = 47 + 2*EP_MAX;
|
||||
#endif
|
||||
usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
|
||||
|
||||
usb_otg->GRXFSIZ = _allocated_fifo_words;
|
||||
_allocated_fifo_words_tx = 16;
|
||||
|
||||
// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
|
||||
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
|
||||
|
||||
_allocated_fifo_words += 16;
|
||||
|
||||
// TU_LOG2_INT(_allocated_fifo_words);
|
||||
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
|
||||
|
||||
// Fixed control EP0 size to 64 bytes
|
||||
in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
|
||||
|
@ -536,6 +557,8 @@ void dcd_disconnect(uint8_t rhport)
|
|||
|
||||
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
|
||||
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
|
||||
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
|
||||
|
@ -546,21 +569,26 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
|||
|
||||
TU_ASSERT(epnum < EP_MAX);
|
||||
|
||||
if (desc_edpt->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
|
||||
{
|
||||
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 1024 : 1023));
|
||||
}
|
||||
else
|
||||
{
|
||||
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 512 : 64));
|
||||
}
|
||||
|
||||
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
|
||||
xfer->max_size = desc_edpt->wMaxPacketSize.size;
|
||||
xfer->interval = desc_edpt->bInterval;
|
||||
|
||||
uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word
|
||||
|
||||
if(dir == TUSB_DIR_OUT)
|
||||
{
|
||||
// Calculate required size of RX FIFO
|
||||
uint16_t const sz = calc_rx_ff_size(4*fifo_size);
|
||||
|
||||
// If size_rx needs to be extended check if possible and if so enlarge it
|
||||
if (usb_otg->GRXFSIZ < sz)
|
||||
{
|
||||
TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
|
||||
|
||||
// Enlarge RX FIFO
|
||||
usb_otg->GRXFSIZ = sz;
|
||||
}
|
||||
|
||||
out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
|
||||
(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
|
||||
(desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
|
||||
|
@ -573,15 +601,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
|||
// Peripheral FIFO architecture
|
||||
//
|
||||
// --------------- 320 or 1024 ( 1280 or 4096 bytes )
|
||||
// | IN FIFO 0 |
|
||||
// --------------- (320 or 1024) - 16
|
||||
// | IN FIFO 1 |
|
||||
// --------------- (320 or 1024) - 16 - x
|
||||
// | . . . . |
|
||||
// --------------- (320 or 1024) - 16 - x - y - ... - z
|
||||
// | IN FIFO MAX |
|
||||
// ---------------
|
||||
// | ... |
|
||||
// --------------- y + x + 16 + GRXFSIZ
|
||||
// | IN FIFO 2 |
|
||||
// --------------- x + 16 + GRXFSIZ
|
||||
// | IN FIFO 1 |
|
||||
// --------------- 16 + GRXFSIZ
|
||||
// | IN FIFO 0 |
|
||||
// | FREE |
|
||||
// --------------- GRXFSIZ
|
||||
// | OUT FIFO |
|
||||
// | ( Shared ) |
|
||||
|
@ -589,34 +617,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
|||
//
|
||||
// In FIFO is allocated by following rules:
|
||||
// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
|
||||
// - Offset: allocated so far
|
||||
// - Size
|
||||
// - Interrupt is EPSize
|
||||
// - Bulk/ISO is max(EPSize, remaining-fifo / non-opened-EPIN)
|
||||
|
||||
uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
|
||||
uint16_t fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // +3 for rounding up to next full word
|
||||
// Check if free space is available
|
||||
TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
|
||||
|
||||
if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
|
||||
{
|
||||
uint8_t opened = 0;
|
||||
for(uint8_t i = 0; i < EP_MAX; i++)
|
||||
{
|
||||
if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
|
||||
}
|
||||
|
||||
// EP Size or equally divided of remaining whichever is larger
|
||||
fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
|
||||
}
|
||||
|
||||
// FIFO overflows, we probably need a better allocating scheme
|
||||
TU_ASSERT(fifo_size <= fifo_remaining);
|
||||
_allocated_fifo_words_tx += fifo_size;
|
||||
|
||||
// DIEPTXF starts at FIFO #1.
|
||||
// Both TXFD and TXSA are in unit of 32-bit words.
|
||||
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
|
||||
|
||||
_allocated_fifo_words += fifo_size;
|
||||
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
|
||||
|
||||
in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
|
||||
(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
|
||||
|
@ -758,13 +767,21 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
|
|||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
dcd_edpt_disable(rhport, ep_addr, false);
|
||||
|
||||
// Update max_size
|
||||
xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation
|
||||
|
||||
if (dir == TUSB_DIR_IN)
|
||||
{
|
||||
uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
|
||||
uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
|
||||
// For now only endpoint that has FIFO at the end of FIFO memory can be closed without fuss.
|
||||
TU_ASSERT(fifo_start + fifo_size == _allocated_fifo_words,);
|
||||
_allocated_fifo_words -= fifo_size;
|
||||
// For now only the last opened endpoint can be closed without fuss.
|
||||
TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
|
||||
_allocated_fifo_words_tx -= fifo_size;
|
||||
}
|
||||
else
|
||||
{
|
||||
_out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1025,13 +1042,15 @@ void dcd_int_handler(uint8_t rhport)
|
|||
|
||||
uint32_t int_status = usb_otg->GINTSTS;
|
||||
|
||||
if(int_status & USB_OTG_GINTSTS_USBRST) {
|
||||
if(int_status & USB_OTG_GINTSTS_USBRST)
|
||||
{
|
||||
// USBRST is start of reset.
|
||||
usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
|
||||
bus_reset(rhport);
|
||||
}
|
||||
|
||||
if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
|
||||
if(int_status & USB_OTG_GINTSTS_ENUMDNE)
|
||||
{
|
||||
// ENUMDNE is the end of reset where speed of the link is detected
|
||||
|
||||
usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
|
||||
|
@ -1068,45 +1087,59 @@ void dcd_int_handler(uint8_t rhport)
|
|||
}
|
||||
|
||||
#if USE_SOF
|
||||
if(int_status & USB_OTG_GINTSTS_SOF) {
|
||||
if(int_status & USB_OTG_GINTSTS_SOF)
|
||||
{
|
||||
usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
// RxFIFO non-empty interrupt handling.
|
||||
if(int_status & USB_OTG_GINTSTS_RXFLVL) {
|
||||
if(int_status & USB_OTG_GINTSTS_RXFLVL)
|
||||
{
|
||||
// RXFLVL bit is read-only
|
||||
|
||||
// Mask out RXFLVL while reading data from FIFO
|
||||
usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
|
||||
|
||||
// Loop until all available packets were handled
|
||||
do {
|
||||
do
|
||||
{
|
||||
handle_rxflvl_ints(rhport, out_ep);
|
||||
int_status = usb_otg->GINTSTS;
|
||||
} while(int_status & USB_OTG_GINTSTS_RXFLVL);
|
||||
|
||||
// Manage RX FIFO size
|
||||
if (_out_ep_closed)
|
||||
{
|
||||
update_grxfsiz(rhport);
|
||||
|
||||
// Disable flag
|
||||
_out_ep_closed = false;
|
||||
}
|
||||
|
||||
usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
||||
}
|
||||
|
||||
// OUT endpoint interrupt handling.
|
||||
if(int_status & USB_OTG_GINTSTS_OEPINT) {
|
||||
if(int_status & USB_OTG_GINTSTS_OEPINT)
|
||||
{
|
||||
// OEPINT is read-only
|
||||
handle_epout_ints(rhport, dev, out_ep);
|
||||
}
|
||||
|
||||
// IN endpoint interrupt handling.
|
||||
if(int_status & USB_OTG_GINTSTS_IEPINT) {
|
||||
if(int_status & USB_OTG_GINTSTS_IEPINT)
|
||||
{
|
||||
// IEPINT bit read-only
|
||||
handle_epin_ints(rhport, dev, in_ep);
|
||||
}
|
||||
|
||||
// // Check for Incomplete isochronous IN transfer
|
||||
// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
|
||||
// printf(" IISOIXFR!\r\n");
|
||||
//// TU_LOG2(" IISOIXFR!\r\n");
|
||||
// }
|
||||
// // Check for Incomplete isochronous IN transfer
|
||||
// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
|
||||
// printf(" IISOIXFR!\r\n");
|
||||
//// TU_LOG2(" IISOIXFR!\r\n");
|
||||
// }
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -232,9 +232,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
|||
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
|
||||
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
|
||||
|
||||
// Unsupported endpoint numbers/size or type (Iso not supported. Control
|
||||
// Unsupported endpoint numbers or type (Iso not supported. Control
|
||||
// not supported on nonzero endpoints).
|
||||
if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7) || \
|
||||
if( (epnum > 7) || \
|
||||
(desc_edpt->bmAttributes.xfer == 0) || \
|
||||
(desc_edpt->bmAttributes.xfer == 1)) {
|
||||
return false;
|
||||
|
@ -572,7 +572,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
{
|
||||
case USBVECINT_RSTR:
|
||||
bus_reset();
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
break;
|
||||
|
||||
// Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet
|
||||
|
|
|
@ -332,7 +332,7 @@ static void dcd_reset(void)
|
|||
usb_out_ev_enable_write(1);
|
||||
usb_setup_ev_enable_write(3);
|
||||
|
||||
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
// Initializes the USB peripheral for device mode and enables it.
|
||||
|
|
|
@ -151,22 +151,22 @@
|
|||
#define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
|
||||
#endif
|
||||
|
||||
#if ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST ) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST )) || \
|
||||
((CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE))
|
||||
#if (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST ) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST )) || \
|
||||
(((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE))
|
||||
#error "TinyUSB currently does not support same modes on more than 1 roothub port"
|
||||
#endif
|
||||
|
||||
// Which roothub port is configured as host
|
||||
#define TUH_OPT_RHPORT ( (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 1 : -1) )
|
||||
#define TUH_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
|
||||
#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 )
|
||||
|
||||
// Which roothub port is configured as device
|
||||
#define TUD_OPT_RHPORT ( (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) ? 1 : -1) )
|
||||
#define TUD_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
|
||||
|
||||
#if TUD_OPT_RHPORT == 0
|
||||
#define TUD_OPT_HIGH_SPEED ( CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED )
|
||||
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
|
||||
#else
|
||||
#define TUD_OPT_HIGH_SPEED ( CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED )
|
||||
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
|
||||
#endif
|
||||
|
||||
#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 )
|
||||
|
|
|
@ -202,7 +202,7 @@ void setUp(void)
|
|||
tusb_init();
|
||||
}
|
||||
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, false);
|
||||
dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, false);
|
||||
tud_task();
|
||||
}
|
||||
|
||||
|
|
|
@ -86,8 +86,8 @@
|
|||
//------------- CDC -------------//
|
||||
|
||||
// FIFO size of CDC TX and RX
|
||||
#define CFG_TUD_CDC_RX_BUFSIZE 64
|
||||
#define CFG_TUD_CDC_TX_BUFSIZE 64
|
||||
#define CFG_TUD_CDC_RX_BUFSIZE 512
|
||||
#define CFG_TUD_CDC_TX_BUFSIZE 512
|
||||
|
||||
//------------- MSC -------------//
|
||||
|
||||
|
@ -97,7 +97,7 @@
|
|||
//------------- HID -------------//
|
||||
|
||||
// Should be sufficient to hold ID (if any) + Data
|
||||
#define CFG_TUD_HID_EP_BUFSIZE 16
|
||||
#define CFG_TUD_HID_EP_BUFSIZE 64
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue