temp fix for dcd 43xx suspend detection (disconnection does not generate interrupt)
This commit is contained in:
hathach
parent
83f1d660ce
commit
41ffcaf4a5
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@ -30,7 +30,7 @@
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@ -54,7 +54,7 @@
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@ -62,7 +62,7 @@
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@ -120,7 +120,7 @@
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@ -144,7 +144,7 @@
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@ -152,7 +152,7 @@
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@ -209,7 +209,7 @@
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@ -235,7 +235,7 @@
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@ -244,7 +244,7 @@
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@ -303,7 +303,7 @@
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@ -327,7 +327,7 @@
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@ -335,7 +335,7 @@
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@ -372,73 +372,82 @@
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|
||||
<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/>
|
||||
<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/>
|
||||
<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/>
|
||||
<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/>
|
||||
<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/>
|
||||
<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
|
||||
<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/>
|
||||
<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/>
|
||||
<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/>
|
||||
<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/>
|
||||
<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/>
|
||||
<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/>
|
||||
<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/>
|
||||
<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/>
|
||||
<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/>
|
||||
<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/>
|
||||
<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
|
||||
<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/>
|
||||
<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/>
|
||||
<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/>
|
||||
<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/>
|
||||
<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/>
|
||||
<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/>
|
||||
<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/>
|
||||
<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
|
||||
<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
|
||||
<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/>
|
||||
<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/>
|
||||
<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
|
||||
<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/>
|
||||
<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
|
||||
<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
|
||||
<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
|
||||
<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
|
||||
<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/>
|
||||
<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/>
|
||||
<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
|
||||
<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/>
|
||||
<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/>
|
||||
<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/>
|
||||
<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
|
||||
<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
|
||||
<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
|
||||
<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
|
||||
<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
|
||||
<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
|
||||
<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
|
||||
<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
|
||||
<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
|
||||
<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
|
||||
<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/>
|
||||
<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/>
|
||||
<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/>
|
||||
<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/>
|
||||
<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/>
|
||||
<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/>
|
||||
<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/>
|
||||
<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/>
|
||||
<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/>
|
||||
<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/>
|
||||
<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/>
|
||||
<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/>
|
||||
<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/>
|
||||
<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/>
|
||||
<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/>
|
||||
<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/>
|
||||
<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/>
|
||||
<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/>
|
||||
<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/>
|
||||
<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/>
|
||||
<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/>
|
||||
<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/>
|
||||
<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/>
|
||||
<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/>
|
||||
<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/>
|
||||
<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/>
|
||||
<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/>
|
||||
<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/>
|
||||
<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/>
|
||||
<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/>
|
||||
<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/>
|
||||
<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/>
|
||||
<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/>
|
||||
<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/>
|
||||
<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/>
|
||||
<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/>
|
||||
<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/>
|
||||
<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/>
|
||||
<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/>
|
||||
<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/>
|
||||
<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/>
|
||||
<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/>
|
||||
<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/>
|
||||
<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/>
|
||||
<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/>
|
||||
<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/>
|
||||
<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/>
|
||||
</chip>
|
||||
<processor><name gcc_name="cortex-m3">Cortex-M3</name>
|
||||
<processor><name gcc_name="cortex-m4">Cortex-M4</name>
|
||||
<family>Cortex-M</family>
|
||||
</processor>
|
||||
<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
|
||||
<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
|
||||
</info>
|
||||
</infoList>
|
||||
</TargetConfig></projectStorage>
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
|
||||
#define TUSB_CFG_DEVICE_HID_MOUSE 0
|
||||
#define TUSB_CFG_DEVICE_HID_GENERIC 0
|
||||
#define TUSB_CFG_DEVICE_MSC 0
|
||||
#define TUSB_CFG_DEVICE_MSC 1
|
||||
#define TUSB_CFG_DEVICE_CDC 1
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1999,8 +1999,9 @@ INCLUDE_FILE_PATTERNS =
|
|||
PREDEFINED = TUSB_CFG_CONTROLLER_0_MODE=TUSB_MODE_HOST \
|
||||
TUSB_CFG_CONTROLLER_1_MODE=TUSB_MODE_HOST \
|
||||
TUSB_CFG_HOST_HID_KEYBOARD=1 \
|
||||
ATTR_PACKED_STRUCT(x)=x \
|
||||
TUSB_CFG_HOST_CDC_RNDIS=1 \
|
||||
ATTR_PACKED_STRUCT(x)=x
|
||||
ATTR_ALIGNED(x)=
|
||||
|
||||
# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
|
||||
# tag can be used to specify a list of macro names that should be expanded. The
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ typedef struct {
|
|||
|
||||
STATIC_ASSERT( sizeof(dcd_qtd_t) == 32, "size is not correct");
|
||||
|
||||
typedef struct {
|
||||
typedef struct ATTR_ALIGNED(64) {
|
||||
// Word 0: Capabilities and Characteristics
|
||||
uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
|
||||
uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
|
||||
|
|
@ -154,7 +154,7 @@ typedef struct {
|
|||
uint8_t list_qtd_idx[DCD_QTD_PER_QHD_MAX];
|
||||
|
||||
uint8_t reserved[15-DCD_QTD_PER_QHD_MAX];
|
||||
} ATTR_ALIGNED(64) dcd_qhd_t;
|
||||
} dcd_qhd_t;
|
||||
|
||||
STATIC_ASSERT( sizeof(dcd_qhd_t) == 64, "size is not correct");
|
||||
|
||||
|
|
@ -543,13 +543,23 @@ void dcd_isr(uint8_t coreid)
|
|||
usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESET);
|
||||
}
|
||||
|
||||
// if (int_status & INT_MASK_SUSPEND)
|
||||
if (int_status & INT_MASK_SUSPEND)
|
||||
{
|
||||
if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
|
||||
{ // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
||||
if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
|
||||
{
|
||||
usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_SUSPENDED);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// TODO disconnection does not generate interrupt !!!!!!
|
||||
// if (int_status & INT_MASK_PORT_CHANGE)
|
||||
// {
|
||||
// uint32_t portsc = lpc_usb->PORTSC1_D;
|
||||
//
|
||||
// if (portsc & PORTSC_SUSPEND_MASK)
|
||||
// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
|
||||
// {
|
||||
// tusbd_device_suspended_cb(coreid);
|
||||
// usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_UNPLUGGED);
|
||||
// }
|
||||
// }
|
||||
|
||||
|
|
@ -589,8 +599,6 @@ void dcd_isr(uint8_t coreid)
|
|||
}
|
||||
|
||||
if (int_status & INT_MASK_SOF) { }
|
||||
if (int_status & INT_MASK_SUSPEND) { }
|
||||
if (int_status & INT_MASK_PORT_CHANGE) { }
|
||||
if (int_status & INT_MASK_NAK) { }
|
||||
if (int_status & INT_MASK_ERROR) ASSERT(false, VOID_RETURN);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue