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switch gd32 and stm32f4 to use new dwc2 driver

This commit is contained in:
hathach 2021-10-25 00:06:57 +07:00
parent 06de6b725c
commit 32742571da
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GPG Key ID: 2FA891220FBFD581
5 changed files with 1516 additions and 1374 deletions
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2
hw/bsp/gd32vf103/family.mk
View File

@ -35,7 +35,7 @@ CFLAGS += \
CFLAGS += -Wno-error=unused-parameter
SRC_C += \
src/portable/st/synopsys/dcd_synopsys.c \
src/portable/synopsys/dwc2/dcd_dwc2.c \
$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \

288
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -52,26 +52,11 @@
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
#if TUD_OPT_RHPORT == 0
#define EP_MAX EP_MAX_FS
#define EP_FIFO_SIZE EP_FIFO_SIZE_FS
#define RHPORT_REGS_BASE USB_OTG_FS_PERIPH_BASE
#define RHPORT_IRQn OTG_FS_IRQn
#else
#define EP_MAX EP_MAX_HS
#define EP_FIFO_SIZE EP_FIFO_SIZE_HS
#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE
#define RHPORT_IRQn OTG_HS_IRQn
#endif
#define GLOBAL_BASE(_port) ((dwc2_core_t*) RHPORT_REGS_BASE)
#define DEVICE_BASE(_port) ((dwc2_device_t *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE))
#define OUT_EP_BASE(_port) ((dwc2_epout_t *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE))
#define IN_EP_BASE(_port) ((dwc2_epin_t *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE))
#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
#define GLOBAL_BASE(_port) ((dwc2_core_t*) DWC2_REG_BASE)
#define DEVICE_BASE(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
#define IN_EP_BASE(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
#define OUT_EP_BASE(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
enum
{
@ -139,17 +124,17 @@ static void bus_reset(uint8_t rhport)
_out_ep_closed = false;
// clear device address
dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
dev->DCFG &= ~DCFG_DAD_Msk;
// 1. NAK for all OUT endpoints
for(uint8_t n = 0; n < EP_MAX; n++) {
out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
out_ep[n].DOEPCTL |= DOEPCTL_SNAK;
}
// 2. Un-mask interrupt bits
dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM;
// "USB Data FIFOs" section in reference manual
// Peripheral FIFO architecture
@ -206,27 +191,27 @@ static void bus_reset(uint8_t rhport)
_allocated_fifo_words_tx = 16;
// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
// Fixed control EP0 size to 64 bytes
in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
}
// Set turn-around timeout according to link speed
extern uint32_t SystemCoreClock;
static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
{
usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
usb_otg->GUSBCFG &= ~GUSBCFG_TRDT;
if ( speed == TUSB_SPEED_HIGH )
{
// Use fixed 0x09 for Highspeed
usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
}
else
{
@ -255,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
turnaround = 0xFU;
// Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
}
}
@ -263,7 +248,7 @@ static tusb_speed_t get_speed(uint8_t rhport)
{
(void) rhport;
dwc2_device_t * dev = DEVICE_BASE(rhport);
uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
}
@ -283,8 +268,8 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
dwc2_device_t * dev = DEVICE_BASE(rhport);
// Clear and set speed bits
dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
dev->DCFG &= ~(3 << DCFG_DSPD_Pos);
dev->DCFG |= (bitvalue << DCFG_DSPD_Pos);
}
#if defined(USB_HS_PHYC)
@ -347,16 +332,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
// IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
if(dir == TUSB_DIR_IN) {
// A full IN transfer (multiple packets, possibly) triggers XFRC.
in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
in_ep[epnum].DIEPTSIZ = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
// For ISO endpoint set correct odd/even bit for next frame.
if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
{
// Take odd/even bit from frame counter.
uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
}
// Enable fifo empty interrupt only if there are something to put in the fifo.
if(total_bytes != 0) {
@ -364,16 +349,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
}
} else {
// A full OUT transfer (multiple packets, possibly) triggers XFRC.
out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
out_ep[epnum].DOEPTSIZ &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
out_ep[epnum].DOEPTSIZ |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
out_ep[epnum].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK;
if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
{
// Take odd/even bit from frame counter.
uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
}
}
}
@ -385,7 +370,6 @@ void dcd_init (uint8_t rhport)
{
// Programming model begins in the last section of the chapter on the USB
// peripheral in each Reference Manual.
dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
// No HNP/SRP (no OTG support), program timeout later.
@ -394,23 +378,23 @@ void dcd_init (uint8_t rhport)
// On selected MCUs HS port1 can be used with external PHY via ULPI interface
#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
// deactivate internal PHY
usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
usb_otg->GCCFG &= ~GCCFG_PWRDWN;
// Init The UTMI Interface
usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
// Select default internal VBUS Indicator and Drive for ULPI
usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
#else
usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
#endif
#if defined(USB_HS_PHYC)
// Highspeed with embedded UTMI PHYC
// Select UTMI Interface
usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
usb_otg->GCCFG |= GCCFG_PHYHSEN;
// Enables control of a High Speed USB PHY
USB_HS_PHYCInit();
@ -418,17 +402,17 @@ void dcd_init (uint8_t rhport)
} else
{
// Enable internal PHY
usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
}
// Reset core after selecting PHY
// Reset core after selecting PHYst
// Wait AHB IDLE, reset then wait until it is cleared
while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
usb_otg->GRSTCTL |= GRSTCTL_CSRST;
while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
// Restart PHY clock
*((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
*((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
// Clear all interrupts
usb_otg->GINTSTS |= usb_otg->GINTSTS;
@ -436,25 +420,25 @@ void dcd_init (uint8_t rhport)
// Required as part of core initialization.
// TODO: How should mode mismatch be handled? It will cause
// the core to stop working/require reset.
usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
dwc2_device_t * dev = DEVICE_BASE(rhport);
// If USB host misbehaves during status portion of control xfer
// (non zero-length packet), send STALL back and discard.
dev->DCFG |= USB_OTG_DCFG_NZLSOHSK;
dev->DCFG |= DCFG_NZLSOHSK;
set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
// Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN;
usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM |
USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
usb_otg->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM |
GINTMSK_USBSUSPM | GINTMSK_WUIM |
GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0);
// Enable global interrupt
usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
usb_otg->GAHBCFG |= GAHBCFG_GINT;
dcd_connect(rhport);
}
@ -474,7 +458,7 @@ void dcd_int_disable (uint8_t rhport)
void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
{
dwc2_device_t * dev = DEVICE_BASE(rhport);
dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
// Response with status after changing device address
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
@ -498,30 +482,30 @@ void dcd_remote_wakeup(uint8_t rhport)
dwc2_device_t * dev = DEVICE_BASE(rhport);
// set remote wakeup
dev->DCTL |= USB_OTG_DCTL_RWUSIG;
dev->DCTL |= DCTL_RWUSIG;
// enable SOF to detect bus resume
usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
usb_otg->GINTSTS = GINTSTS_SOF;
usb_otg->GINTMSK |= GINTMSK_SOFM;
// Per specs: remote wakeup signal bit must be clear within 1-15ms
remote_wakeup_delay();
dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
dev->DCTL &= ~DCTL_RWUSIG;
}
void dcd_connect(uint8_t rhport)
{
(void) rhport;
dwc2_device_t * dev = DEVICE_BASE(rhport);
dev->DCTL &= ~USB_OTG_DCTL_SDIS;
dev->DCTL &= ~DCTL_SDIS;
}
void dcd_disconnect(uint8_t rhport)
{
(void) rhport;
dwc2_device_t * dev = DEVICE_BASE(rhport);
dev->DCTL |= USB_OTG_DCTL_SDIS;
dev->DCTL |= DCTL_SDIS;
}
@ -563,12 +547,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
usb_otg->GRXFSIZ = sz;
}
out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
(xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) |
(desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
(xfer->max_size << DOEPCTL_MPSIZ_Pos);
dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
dev->DAINTMSK |= (1 << (DAINTMSK_OEPM_Pos + epnum));
}
else
{
@ -602,15 +586,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
// DIEPTXF starts at FIFO #1.
// Both TXFD and TXSA are in unit of 32-bit words.
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
(desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
(xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
(epnum << DIEPCTL_TXFNUM_Pos) |
(desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
(desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
(xfer->max_size << DIEPCTL_MPSIZ_Pos);
dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
dev->DAINTMSK |= (1 << (DAINTMSK_IEPM_Pos + epnum));
}
return true;
@ -627,7 +611,7 @@ void dcd_edpt_close_all (uint8_t rhport)
dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
// Disable non-control interrupt
dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
for(uint8_t n = 1; n < EP_MAX; n++)
{
@ -719,42 +703,42 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
if(dir == TUSB_DIR_IN) {
// Only disable currently enabled non-control endpoint
if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ){
in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
} else {
// Stop transmitting packets and NAK IN xfers.
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK;
while((in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0);
// Disable the endpoint.
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
while((in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0);
in_ep[epnum].DIEPINT = DIEPINT_EPDISD;
}
// Flush the FIFO, and wait until we have confirmed it cleared.
usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH;
while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
} else {
// Only disable currently enabled non-control endpoint
if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){
out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0;
} else {
// Asserting GONAK is required to STALL an OUT endpoint.
// Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
// anyway, and it can't be cleared by user code. If this while loop never
// finishes, we have bigger problems than just the stack.
dev->DCTL |= USB_OTG_DCTL_SGONAK;
while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
dev->DCTL |= DCTL_SGONAK;
while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
// Ditto here- disable the endpoint.
out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
while((out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0);
out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
// Allow other OUT endpoints to keep receiving.
dev->DCTL |= USB_OTG_DCTL_CGONAK;
dev->DCTL |= DCTL_CGONAK;
}
}
}
@ -776,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
if (dir == TUSB_DIR_IN)
{
uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
// For now only the last opened endpoint can be closed without fuss.
TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
_allocated_fifo_words_tx -= fifo_size;
@ -805,11 +789,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
// Clear stall and reset data toggle
if(dir == TUSB_DIR_IN) {
in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL;
in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM;
} else {
out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL;
out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM;
}
}
@ -882,9 +866,9 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
// Pop control word off FIFO
uint32_t ctl_word = usb_otg->GRXSTSP;
uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos;
uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
switch(pktsts) {
case 0x01: // Global OUT NAK (Interrupt)
@ -911,7 +895,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
// Truncate transfer length in case of short packet
if(bcnt < xfer->max_size) {
xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
xfer->total_len -= (out_ep[epnum].DOEPTSIZ & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
if(epnum == 0) {
xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
ep0_pending[TUSB_DIR_OUT] = 0;
@ -924,7 +908,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
break;
case 0x04: // Setup packet done (Interrupt)
out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
out_ep[epnum].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
break;
case 0x06: // Setup packet recvd
@ -946,16 +930,16 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t
for(uint8_t n = 0; n < EP_MAX; n++) {
xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) {
// SETUP packet Setup Phase done.
if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP;
if(out_ep[n].DOEPINT & DOEPINT_STUP) {
out_ep[n].DOEPINT = DOEPINT_STUP;
dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
}
// OUT XFER complete
if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
if(out_ep[n].DOEPINT & DOEPINT_XFRC) {
out_ep[n].DOEPINT = DOEPINT_XFRC;
// EP0 can only handle one packet
if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
@ -976,12 +960,12 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
{
xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
if ( dev->DAINT & (1 << (DAINT_IEPINT_Pos + n)) )
{
// IN XFER complete (entire xfer).
if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
if ( in_ep[n].DIEPINT & DIEPINT_XFRC )
{
in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
in_ep[n].DIEPINT = DIEPINT_XFRC;
// EP0 can only handle one packet
if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
@ -993,26 +977,26 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
}
// XFER FIFO empty
if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
{
// DIEPINT's TXFE bit is read-only, software cannot clear it.
// It will only be cleared by hardware when written bytes is more than
// - 64 bytes or
// - Half of TX FIFO size (configured by DIEPTXF)
uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
// Process every single packet (only whole packets can be written to fifo)
for(uint16_t i = 0; i < remaining_packets; i++)
{
uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
// Packet can not be larger than ep max size
uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
// It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
// EP has to be checked if the buffer can take another WHOLE packet
if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
if(packet_size > ((in_ep[n].DTXFSTS & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
// Push packet to Tx-FIFO
if (xfer->ff)
@ -1030,7 +1014,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
}
// Turn off TXFE if all bytes are written.
if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
{
dev->DIEPEMPMSK &= ~(1 << n);
}
@ -1048,18 +1032,18 @@ void dcd_int_handler(uint8_t rhport)
uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
if(int_status & USB_OTG_GINTSTS_USBRST)
if(int_status & GINTSTS_USBRST)
{
// USBRST is start of reset.
usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
usb_otg->GINTSTS = GINTSTS_USBRST;
bus_reset(rhport);
}
if(int_status & USB_OTG_GINTSTS_ENUMDNE)
if(int_status & GINTSTS_ENUMDNE)
{
// ENUMDNE is the end of reset where speed of the link is detected
usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
usb_otg->GINTSTS = GINTSTS_ENUMDNE;
tusb_speed_t const speed = get_speed(rhport);
@ -1067,27 +1051,27 @@ void dcd_int_handler(uint8_t rhport)
dcd_event_bus_reset(rhport, speed, true);
}
if(int_status & USB_OTG_GINTSTS_USBSUSP)
if(int_status & GINTSTS_USBSUSP)
{
usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
usb_otg->GINTSTS = GINTSTS_USBSUSP;
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
}
if(int_status & USB_OTG_GINTSTS_WKUINT)
if(int_status & GINTSTS_WKUINT)
{
usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
usb_otg->GINTSTS = GINTSTS_WKUINT;
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
}
// TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
// if(int_status & USB_OTG_GINTSTS_DISCINT)
// TODO check GINTSTS_DISCINT for disconnect detection
// if(int_status & GINTSTS_DISCINT)
if(int_status & USB_OTG_GINTSTS_OTGINT)
if(int_status & GINTSTS_OTGINT)
{
// OTG INT bit is read-only
uint32_t const otg_int = usb_otg->GOTGINT;
if (otg_int & USB_OTG_GOTGINT_SEDET)
if (otg_int & GOTGINT_SEDET)
{
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
}
@ -1095,29 +1079,29 @@ void dcd_int_handler(uint8_t rhport)
usb_otg->GOTGINT = otg_int;
}
if(int_status & USB_OTG_GINTSTS_SOF)
if(int_status & GINTSTS_SOF)
{
usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
usb_otg->GINTSTS = GINTSTS_SOF;
// Disable SOF interrupt since currently only used for remote wakeup detection
usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
usb_otg->GINTMSK &= ~GINTMSK_SOFM;
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
}
// RxFIFO non-empty interrupt handling.
if(int_status & USB_OTG_GINTSTS_RXFLVL)
if(int_status & GINTSTS_RXFLVL)
{
// RXFLVL bit is read-only
// Mask out RXFLVL while reading data from FIFO
usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM;
// Loop until all available packets were handled
do
{
handle_rxflvl_ints(rhport, out_ep);
} while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
} while(usb_otg->GINTSTS & GINTSTS_RXFLVL);
// Manage RX FIFO size
if (_out_ep_closed)
@ -1128,25 +1112,25 @@ void dcd_int_handler(uint8_t rhport)
_out_ep_closed = false;
}
usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
usb_otg->GINTMSK |= GINTMSK_RXFLVLM;
}
// OUT endpoint interrupt handling.
if(int_status & USB_OTG_GINTSTS_OEPINT)
if(int_status & GINTSTS_OEPINT)
{
// OEPINT is read-only
handle_epout_ints(rhport, dev, out_ep);
}
// IN endpoint interrupt handling.
if(int_status & USB_OTG_GINTSTS_IEPINT)
if(int_status & GINTSTS_IEPINT)
{
// IEPINT bit read-only
handle_epin_ints(rhport, dev, in_ep);
}
// // Check for Incomplete isochronous IN transfer
// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
// if(int_status & GINTSTS_IISOIXFR) {
// printf(" IISOIXFR!\r\n");
//// TU_LOG2(" IISOIXFR!\r\n");
// }

7
src/portable/synopsys/dwc2/dwc2_gd32.h
View File

@ -32,9 +32,10 @@
#define __NOP() __asm volatile ("nop")
// These numbers are the same for the whole GD32VF103 family.
#define OTG_FS_IRQn 86
#define EP_MAX_FS 4
#define EP_FIFO_SIZE_FS 1280
#define RHPORT_IRQn 86
#define EP_MAX 4
#define EP_FIFO_SIZE 1280
#define DWC2_REG_BASE 0x50000000UL
// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
// Interrupt Controller by Nuclei. It is nearly API compatible to the

15
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@ -69,4 +69,19 @@
#error "Unsupported MCUs"
#endif
// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
#if TUD_OPT_RHPORT == 0
#define EP_MAX EP_MAX_FS
#define EP_FIFO_SIZE EP_FIFO_SIZE_FS
#define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE
#define RHPORT_IRQn OTG_FS_IRQn
#else
#define EP_MAX EP_MAX_HS
#define EP_FIFO_SIZE EP_FIFO_SIZE_HS
#define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE
#define RHPORT_IRQn OTG_HS_IRQn
#endif
#endif /* DWC2_STM32_H_ */

2578
src/portable/synopsys/dwc2/dwc2_type.h
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