Enhance EP FIFO allocation for both Fullspeed and Highspeed
- Update shared RX FIFO calculation with FS/HS - IN FIFO EP - Interrupt -> use EPSize - Bulk/ISO -> use max(EPSize, remaining-fifo / non-opened-EPIN)
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hathach
parent
e89fea8237
commit
2dd1be13e5
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@ -116,7 +116,6 @@ enum
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DCD_FULL_SPEED = 3, // Full speed with internal PHY
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};
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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@ -138,6 +137,8 @@ typedef volatile uint32_t * usb_fifo_t;
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xfer_ctl_t xfer_status[EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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// FIFO RAM allocation so far in words
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static uint16_t _allocated_fifo_words;
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// Setup the control endpoint 0.
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static void bus_reset(uint8_t rhport)
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@ -147,6 +148,8 @@ static void bus_reset(uint8_t rhport)
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
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tu_memclr(xfer_status, sizeof(xfer_status));
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for(uint8_t n = 0; n < EP_MAX; n++) {
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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}
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@ -177,17 +180,36 @@ static void bus_reset(uint8_t rhport)
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// - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
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//
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// - All EP OUT shared a unique OUT FIFO which uses
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// * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
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// * 2 locations for OUT endpoint control words.
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// * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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// * 1 location for global NAK (not required/used here).
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// * It is recommended to allocate 2 times the largest packet size, therefore
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// Recommended value = 10 + 1 + 2 x (16+2) = 47. To make it scale better with large FIFO size
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// and work better with Highspeed. We use 1/5 of total FIFO size
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usb_otg->GRXFSIZ = (EP_FIFO_SIZE/4)/5;
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// - 13 for setup packets + control words (up to 3 setup packets).
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// - 1 for global NAK (not required/used here).
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// - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
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// - 2 for each used OUT endpoint
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//
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// Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
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// - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX
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// - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
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//
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// NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
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// of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
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//
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// FIXME: for Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
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// are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
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// overwrite this.
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#if TUD_OPT_HIGH_SPEED
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_allocated_fifo_words = 271 + 2*EP_MAX;
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#else
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_allocated_fifo_words = 47 + 2*EP_MAX;
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#endif
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usb_otg->GRXFSIZ = _allocated_fifo_words;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (usb_otg->GRXFSIZ & 0x0000ffffUL);
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usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += 16;
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// TU_LOG2_INT(_allocated_fifo_words);
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// Fixed control EP0 size to 64 bytes
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in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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@ -221,7 +243,6 @@ static tusb_speed_t get_speed(USB_OTG_DeviceTypeDef* dev)
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return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
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}
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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@ -242,9 +263,11 @@ void dcd_init (uint8_t rhport)
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usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
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// On selected MCUs HS port1 can be used with external PHY via ULPI interface
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// Select ULPI highspeed PHY with default external VBUS Indicator and Drive
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL |
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USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
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// Init ULPI Interface
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
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// Select default internal VBUS Indicator and Drive for ULPI
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usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
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set_turnaround(usb_otg, TUSB_SPEED_HIGH);
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}
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@ -303,7 +326,6 @@ void dcd_init (uint8_t rhport)
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USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM |
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USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
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// Enable global interrupt
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usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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}
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@ -397,10 +419,40 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// | ( Shared ) |
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// --------------- 0
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//
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// Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
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// - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
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// - Offset: GRXFSIZ + 16 + Size*(epnum-1)
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// In FIFO is allocated by following rules:
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// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
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// - Offset: allocated so far
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// - Size
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// - Interrupt is EPSize
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// - Bulk/ISO is max(EPSize, remaining-fifo / non-opened-EPIN)
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uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
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uint16_t fifo_size = desc_edpt->wMaxPacketSize.size / 4;
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if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
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{
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uint8_t opened = 0;
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for(uint8_t i = 0; i < EP_MAX; i++)
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{
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if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
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}
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// EP Size or equally divided of remaining whichever is larger
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fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
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}
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// FIFO overflows, we probably need a better allocating scheme
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TU_ASSERT(fifo_size <= fifo_remaining);
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// DIEPTXF starts at FIFO #1.
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// Both TXFD and TXSA are in unit of 32-bit words.
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
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_allocated_fifo_words += fifo_size;
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//TU_LOG2_INT(fifo_size);
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//TU_LOG2_INT(_allocated_fifo_words);
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
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(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
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@ -409,15 +461,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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(desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
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dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
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// Both TXFD and TXSA are in unit of 32-bit words.
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// IN FIFO 0 was configured during enumeration, hence the "+ 16".
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uint16_t const allocated_size = (usb_otg->GRXFSIZ & 0x0000ffff) + 16;
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uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
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uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
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// DIEPTXF starts at FIFO #1.
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usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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}
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return true;
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@ -433,8 +476,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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uint16_t num_packets = (total_bytes / xfer->max_size);
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uint8_t short_packet_size = total_bytes % xfer->max_size;
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@ -533,20 +576,16 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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if(dir == TUSB_DIR_IN) {
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in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
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uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> \
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USB_OTG_DIEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
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// and bulk endpoints.
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uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> USB_OTG_DIEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
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if(eptype == 2 || eptype == 3) {
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in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
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}
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} else {
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out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
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uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> \
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USB_OTG_DOEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
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// and bulk endpoints.
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uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> USB_OTG_DOEPCTL_EPTYP_Pos;
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// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
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if(eptype == 2 || eptype == 3) {
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out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
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}
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