fomu: csr: sync csr
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
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f087cb1580
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25d5628063
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@ -1,5 +1,5 @@
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-01 12:04:21
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// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49
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//--------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------
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#ifndef __GENERATED_CSR_H
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#ifndef __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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#define __GENERATED_CSR_H
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@ -57,41 +57,6 @@ static inline unsigned int ctrl_bus_errors_read(void) {
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return r;
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return r;
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}
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}
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/* lxspi */
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#define CSR_LXSPI_BASE 0xe0007800L
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#define CSR_LXSPI_BITBANG_ADDR 0xe0007800L
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#define CSR_LXSPI_BITBANG_SIZE 1
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static inline unsigned char lxspi_bitbang_read(void) {
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unsigned char r = csr_readl(0xe0007800L);
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return r;
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}
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static inline void lxspi_bitbang_write(unsigned char value) {
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csr_writel(value, 0xe0007800L);
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}
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#define CSR_LXSPI_BITBANG_MOSI_OFFSET 0
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#define CSR_LXSPI_BITBANG_MOSI_SIZE 1
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#define CSR_LXSPI_BITBANG_CLK_OFFSET 1
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#define CSR_LXSPI_BITBANG_CLK_SIZE 1
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#define CSR_LXSPI_BITBANG_CS_N_OFFSET 2
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#define CSR_LXSPI_BITBANG_CS_N_SIZE 1
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#define CSR_LXSPI_BITBANG_DIR_OFFSET 3
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#define CSR_LXSPI_BITBANG_DIR_SIZE 1
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#define CSR_LXSPI_MISO_ADDR 0xe0007804L
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#define CSR_LXSPI_MISO_SIZE 1
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static inline unsigned char lxspi_miso_read(void) {
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unsigned char r = csr_readl(0xe0007804L);
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return r;
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}
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#define CSR_LXSPI_BITBANG_EN_ADDR 0xe0007808L
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#define CSR_LXSPI_BITBANG_EN_SIZE 1
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static inline unsigned char lxspi_bitbang_en_read(void) {
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unsigned char r = csr_readl(0xe0007808L);
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return r;
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}
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static inline void lxspi_bitbang_en_write(unsigned char value) {
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csr_writel(value, 0xe0007808L);
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}
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/* messible */
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/* messible */
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#define CSR_MESSIBLE_BASE 0xe0008000L
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#define CSR_MESSIBLE_BASE 0xe0008000L
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#define CSR_MESSIBLE_IN_ADDR 0xe0008000L
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#define CSR_MESSIBLE_IN_ADDR 0xe0008000L
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@ -120,6 +85,89 @@ static inline unsigned char messible_status_read(void) {
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#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
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#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
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#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
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#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
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/* picorvspi */
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#define CSR_PICORVSPI_BASE 0xe0005000L
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#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L
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#define CSR_PICORVSPI_CFG1_SIZE 1
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static inline unsigned char picorvspi_cfg1_read(void) {
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unsigned char r = csr_readl(0xe0005000L);
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return r;
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}
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static inline void picorvspi_cfg1_write(unsigned char value) {
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csr_writel(value, 0xe0005000L);
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}
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#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0
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#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4
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#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4
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#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1
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#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5
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#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1
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#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L
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#define CSR_PICORVSPI_CFG2_SIZE 1
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static inline unsigned char picorvspi_cfg2_read(void) {
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unsigned char r = csr_readl(0xe0005004L);
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return r;
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}
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static inline void picorvspi_cfg2_write(unsigned char value) {
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csr_writel(value, 0xe0005004L);
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}
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#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0
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#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4
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#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L
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#define CSR_PICORVSPI_CFG3_SIZE 1
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static inline unsigned char picorvspi_cfg3_read(void) {
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unsigned char r = csr_readl(0xe0005008L);
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return r;
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}
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static inline void picorvspi_cfg3_write(unsigned char value) {
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csr_writel(value, 0xe0005008L);
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}
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#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0
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#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4
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#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4
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#define CSR_PICORVSPI_CFG3_CRM_SIZE 1
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#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5
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#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1
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#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6
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#define CSR_PICORVSPI_CFG3_DDR_SIZE 1
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#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL
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#define CSR_PICORVSPI_CFG4_SIZE 1
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static inline unsigned char picorvspi_cfg4_read(void) {
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unsigned char r = csr_readl(0xe000500cL);
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return r;
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}
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static inline void picorvspi_cfg4_write(unsigned char value) {
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csr_writel(value, 0xe000500cL);
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}
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#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7
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#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1
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#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L
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#define CSR_PICORVSPI_STAT1_SIZE 1
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static inline unsigned char picorvspi_stat1_read(void) {
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unsigned char r = csr_readl(0xe0005010L);
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return r;
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}
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#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0
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#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4
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#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L
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#define CSR_PICORVSPI_STAT2_SIZE 1
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static inline unsigned char picorvspi_stat2_read(void) {
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unsigned char r = csr_readl(0xe0005014L);
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return r;
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}
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#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L
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#define CSR_PICORVSPI_STAT3_SIZE 1
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static inline unsigned char picorvspi_stat3_read(void) {
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unsigned char r = csr_readl(0xe0005018L);
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return r;
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}
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#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL
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#define CSR_PICORVSPI_STAT4_SIZE 1
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static inline unsigned char picorvspi_stat4_read(void) {
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unsigned char r = csr_readl(0xe000501cL);
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return r;
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}
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/* reboot */
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/* reboot */
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#define CSR_REBOOT_BASE 0xe0006000L
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#define CSR_REBOOT_BASE 0xe0006000L
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#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
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#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
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@ -393,8 +441,6 @@ static inline unsigned char usb_setup_ctrl_read(void) {
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static inline void usb_setup_ctrl_write(unsigned char value) {
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static inline void usb_setup_ctrl_write(unsigned char value) {
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csr_writel(value, 0xe0004810L);
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csr_writel(value, 0xe0004810L);
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}
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}
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#define CSR_USB_SETUP_CTRL_ACK_OFFSET 1
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#define CSR_USB_SETUP_CTRL_ACK_SIZE 1
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#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
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#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
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#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
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#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
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#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L
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#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L
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@ -660,14 +706,6 @@ static inline int timer0_interrupt_read(void) {
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static inline int usb_interrupt_read(void) {
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static inline int usb_interrupt_read(void) {
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return 3;
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return 3;
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}
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}
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#define SPI_BOOT 1
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static inline int spi_boot_read(void) {
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return 1;
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}
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#define SPI_ENTRYPOINT 536977408
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static inline int spi_entrypoint_read(void) {
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return 536977408;
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}
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#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870
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#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870
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static inline int config_bitstream_sync_header1_read(void) {
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static inline int config_bitstream_sync_header1_read(void) {
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return 2123999870;
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return 2123999870;
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