kingkevin
/
espressif_tinyusb
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fomu: csr: sync csr 

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-11-12 20:21:17 -08:00
parent f087cb1580
commit 25d5628063
1 changed files with 84 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

130
hw/bsp/fomu/include/csr.h
View File

@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-01 12:04:21
// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49
//--------------------------------------------------------------------------------
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
@ -57,41 +57,6 @@ static inline unsigned int ctrl_bus_errors_read(void) {
return r;
}
/* lxspi */
#define CSR_LXSPI_BASE 0xe0007800L
#define CSR_LXSPI_BITBANG_ADDR 0xe0007800L
#define CSR_LXSPI_BITBANG_SIZE 1
static inline unsigned char lxspi_bitbang_read(void) {
unsigned char r = csr_readl(0xe0007800L);
return r;
}
static inline void lxspi_bitbang_write(unsigned char value) {
csr_writel(value, 0xe0007800L);
}
#define CSR_LXSPI_BITBANG_MOSI_OFFSET 0
#define CSR_LXSPI_BITBANG_MOSI_SIZE 1
#define CSR_LXSPI_BITBANG_CLK_OFFSET 1
#define CSR_LXSPI_BITBANG_CLK_SIZE 1
#define CSR_LXSPI_BITBANG_CS_N_OFFSET 2
#define CSR_LXSPI_BITBANG_CS_N_SIZE 1
#define CSR_LXSPI_BITBANG_DIR_OFFSET 3
#define CSR_LXSPI_BITBANG_DIR_SIZE 1
#define CSR_LXSPI_MISO_ADDR 0xe0007804L
#define CSR_LXSPI_MISO_SIZE 1
static inline unsigned char lxspi_miso_read(void) {
unsigned char r = csr_readl(0xe0007804L);
return r;
}
#define CSR_LXSPI_BITBANG_EN_ADDR 0xe0007808L
#define CSR_LXSPI_BITBANG_EN_SIZE 1
static inline unsigned char lxspi_bitbang_en_read(void) {
unsigned char r = csr_readl(0xe0007808L);
return r;
}
static inline void lxspi_bitbang_en_write(unsigned char value) {
csr_writel(value, 0xe0007808L);
}
/* messible */
#define CSR_MESSIBLE_BASE 0xe0008000L
#define CSR_MESSIBLE_IN_ADDR 0xe0008000L
@ -120,6 +85,89 @@ static inline unsigned char messible_status_read(void) {
#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
/* picorvspi */
#define CSR_PICORVSPI_BASE 0xe0005000L
#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L
#define CSR_PICORVSPI_CFG1_SIZE 1
static inline unsigned char picorvspi_cfg1_read(void) {
unsigned char r = csr_readl(0xe0005000L);
return r;
}
static inline void picorvspi_cfg1_write(unsigned char value) {
csr_writel(value, 0xe0005000L);
}
#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0
#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4
#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4
#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1
#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5
#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1
#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L
#define CSR_PICORVSPI_CFG2_SIZE 1
static inline unsigned char picorvspi_cfg2_read(void) {
unsigned char r = csr_readl(0xe0005004L);
return r;
}
static inline void picorvspi_cfg2_write(unsigned char value) {
csr_writel(value, 0xe0005004L);
}
#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0
#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4
#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L
#define CSR_PICORVSPI_CFG3_SIZE 1
static inline unsigned char picorvspi_cfg3_read(void) {
unsigned char r = csr_readl(0xe0005008L);
return r;
}
static inline void picorvspi_cfg3_write(unsigned char value) {
csr_writel(value, 0xe0005008L);
}
#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0
#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4
#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4
#define CSR_PICORVSPI_CFG3_CRM_SIZE 1
#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5
#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1
#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6
#define CSR_PICORVSPI_CFG3_DDR_SIZE 1
#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL
#define CSR_PICORVSPI_CFG4_SIZE 1
static inline unsigned char picorvspi_cfg4_read(void) {
unsigned char r = csr_readl(0xe000500cL);
return r;
}
static inline void picorvspi_cfg4_write(unsigned char value) {
csr_writel(value, 0xe000500cL);
}
#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7
#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1
#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L
#define CSR_PICORVSPI_STAT1_SIZE 1
static inline unsigned char picorvspi_stat1_read(void) {
unsigned char r = csr_readl(0xe0005010L);
return r;
}
#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0
#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4
#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L
#define CSR_PICORVSPI_STAT2_SIZE 1
static inline unsigned char picorvspi_stat2_read(void) {
unsigned char r = csr_readl(0xe0005014L);
return r;
}
#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L
#define CSR_PICORVSPI_STAT3_SIZE 1
static inline unsigned char picorvspi_stat3_read(void) {
unsigned char r = csr_readl(0xe0005018L);
return r;
}
#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL
#define CSR_PICORVSPI_STAT4_SIZE 1
static inline unsigned char picorvspi_stat4_read(void) {
unsigned char r = csr_readl(0xe000501cL);
return r;
}
/* reboot */
#define CSR_REBOOT_BASE 0xe0006000L
#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
@ -393,8 +441,6 @@ static inline unsigned char usb_setup_ctrl_read(void) {
static inline void usb_setup_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0004810L);
}
#define CSR_USB_SETUP_CTRL_ACK_OFFSET 1
#define CSR_USB_SETUP_CTRL_ACK_SIZE 1
#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L
@ -660,14 +706,6 @@ static inline int timer0_interrupt_read(void) {
static inline int usb_interrupt_read(void) {
return 3;
}
#define SPI_BOOT 1
static inline int spi_boot_read(void) {
return 1;
}
#define SPI_ENTRYPOINT 536977408
static inline int spi_entrypoint_read(void) {
return 536977408;
}
#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870
static inline int config_bitstream_sync_header1_read(void) {
return 2123999870;