dcd: same70: trim trailling spaces
Signed-off-by: Rafael Silva <perigoso@riseup.net>
This commit is contained in:
Rafael Silva
parent
28875c431b
commit
2196991df3
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@ -1,4 +1,4 @@
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/*
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018, hathach (tinyusb.org)
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@ -137,7 +137,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
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(void) dev_addr;
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// DCD can only set address after status for this request is complete
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// do it at dcd_edpt0_status_complete()
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// Response with zlp status
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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}
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@ -234,7 +234,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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dcd_event_setup_received(0, ptr, true);
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}
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// Acknowledge the interrupt
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// Acknowledge the interrupt
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USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
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}
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if (int_status & USBHS_DEVEPTISR_RXOUTI)
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@ -251,34 +251,34 @@ static void dcd_ep_handler(uint8_t ep_ix)
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}
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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// Acknowledge the interrupt
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// Acknowledge the interrupt
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USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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// RX COMPLETE
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// RX COMPLETE
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dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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// Disable the interrupt
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
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// Though the host could still send, we don't know.
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}
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}
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if (int_status & USBHS_DEVEPTISR_TXINI)
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{
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// Disable the interrupt
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// Disable the interrupt
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
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xfer_ctl_t * xfer = &xfer_status[EP_MAX];
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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// TX not complete
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dcd_transmit_packet(xfer, 0);
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} else {
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// TX complete
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// TX complete
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dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
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}
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}
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} else {
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if (int_status & USBHS_DEVEPTISR_RXOUTI)
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{
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{
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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if (count)
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{
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@ -291,27 +291,27 @@ static void dcd_ep_handler(uint8_t ep_ix)
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}
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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// Acknowledge the interrupt
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// Acknowledge the interrupt
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USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
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// Clear the FIFO control flag to receive more data.
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USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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// RX COMPLETE
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// RX COMPLETE
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dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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// Disable the interrupt
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USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
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// Though the host could still send, we don't know.
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}
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}
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if (int_status & USBHS_DEVEPTISR_TXINI)
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{
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// Acknowledge the interrupt
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// Acknowledge the interrupt
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USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
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xfer_ctl_t * xfer = &xfer_status[ep_ix];;
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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// TX not complete
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dcd_transmit_packet(xfer, ep_ix);
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} else {
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// TX complete
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@ -331,7 +331,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
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}
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// Disable DMA interrupt
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USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
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if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
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@ -346,10 +346,10 @@ void dcd_int_handler(uint8_t rhport)
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{
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(void) rhport;
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uint32_t int_status = USBHS->USBHS_DEVISR;
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// End of reset interrupt
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// End of reset interrupt
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if (int_status & USBHS_DEVISR_EORST)
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{
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// Unfreeze USB clock
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// Unfreeze USB clock
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USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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// Reset all endpoints
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@ -363,10 +363,10 @@ void dcd_int_handler(uint8_t rhport)
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USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
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USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
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dcd_event_bus_reset(rhport, get_speed(), true);
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}
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// End of Wakeup interrupt
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// End of Wakeup interrupt
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if (int_status & USBHS_DEVISR_WAKEUP)
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{
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USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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@ -374,31 +374,31 @@ void dcd_int_handler(uint8_t rhport)
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USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
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USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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}
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// Suspend interrupt
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// Suspend interrupt
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if (int_status & USBHS_DEVISR_SUSP)
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{
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// Unfreeze USB clock
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// Unfreeze USB clock
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USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
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USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
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USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
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USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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}
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#if USE_SOF
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if(int_status & USBHS_DEVISR_SOF)
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{
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USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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#endif
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// Endpoints interrupt
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#endif
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// Endpoints interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
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{
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if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix))
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@ -406,7 +406,7 @@ void dcd_int_handler(uint8_t rhport)
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dcd_ep_handler(ep_ix);
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}
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}
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// Endpoints DMA interrupt
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// Endpoints DMA interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
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{
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if (EP_DMA_SUPPORT(ep_ix))
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@ -433,7 +433,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
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request->bRequest == TUSB_REQ_SET_ADDRESS )
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{
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uint8_t const dev_addr = (uint8_t) request->wValue;
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USBHS->USBHS_DEVCTRL |= dev_addr | USBHS_DEVCTRL_ADDEN;
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}
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}
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@ -446,9 +446,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
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uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
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tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
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uint8_t fifoSize = 0; // FIFO size
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uint16_t defaultEndpointSize = 8; // Default size of Endpoint
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// Find upper 2 power number of epMaxPktSize
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uint8_t fifoSize = 0; // FIFO size
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uint16_t defaultEndpointSize = 8; // Default size of Endpoint
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// Find upper 2 power number of epMaxPktSize
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if (epMaxPktSize)
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{
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while (defaultEndpointSize < epMaxPktSize)
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@ -458,16 +458,16 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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}
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}
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xfer_status[epnum].max_packet_size = epMaxPktSize;
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USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
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USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
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if (epnum == 0)
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if (epnum == 0)
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{
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xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
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// Enable the control endpoint - Endpoint 0
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// Enable the control endpoint - Endpoint 0
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USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
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// Configure the Endpoint 0 configuration register
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// Configure the Endpoint 0 configuration register
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USBHS->USBHS_DEVEPTCFG[0] =
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(
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USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
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@ -479,20 +479,20 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
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if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
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{
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// Endpoint configuration is successful
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// Endpoint configuration is successful
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USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
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// Enable Endpoint 0 Interrupts
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// Enable Endpoint 0 Interrupts
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USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
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return true;
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} else {
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// Endpoint configuration is not successful
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// Endpoint configuration is not successful
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return false;
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}
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} else {
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// Enable the endpoint
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// Enable the endpoint
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USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
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// Set up the maxpacket size, fifo start address fifosize
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// and enable the interrupt. CLear the data toggle.
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// and enable the interrupt. CLear the data toggle.
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// AUTOSW is needed for DMA ack !
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USBHS->USBHS_DEVEPTCFG[epnum] =
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(
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@ -504,12 +504,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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);
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if (eptype == TUSB_XFER_ISOCHRONOUS)
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{
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
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}
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#if USE_DUAL_BANK
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if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
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{
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
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}
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#endif
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
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@ -520,7 +520,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
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return true;
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} else {
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// Endpoint configuration is not successful
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// Endpoint configuration is not successful
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return false;
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}
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}
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@ -546,7 +546,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
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{
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// Control endpoint: clear the interrupt flag to send the data
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USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
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} else {
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// Other endpoint types: clear the FIFO control flag to send the data
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USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
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@ -560,16 +560,16 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t * xfer = &xfer_status[epnum];
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if(ep_addr == 0x80)
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xfer = &xfer_status[EP_MAX];
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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xfer->queued_len = 0;
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xfer->fifo = NULL;
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if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
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{
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uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
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@ -618,16 +618,16 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t * xfer = &xfer_status[epnum];
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if(epnum == 0x80)
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xfer = &xfer_status[EP_MAX];
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xfer->buffer = NULL;
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xfer->total_len = total_bytes;
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xfer->queued_len = 0;
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xfer->fifo = ff;
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if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
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{
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tu_fifo_buffer_info_t info;
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@ -646,13 +646,13 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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}
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udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
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}
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
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if (info.len_wrap)
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{
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dma_desc[epnum - 1].next_desc = 0;
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dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
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dma_desc[epnum - 1].chnl_ctrl =
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dma_desc[epnum - 1].chnl_ctrl =
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udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
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udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
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__DSB();
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