add support for the QMTech ATMSAME70N19A board
This commit is contained in:
Hans Baier
parent
8f0cfc8d44
commit
196a0da813
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DEPS_SUBMODULES += hw/mcu/microchip
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m7 \
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-mfloat-abi=hard \
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-mfpu=fpv4-sp-d16 \
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-nostdlib -nostartfiles \
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-D__SAME70N19B__ \
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-DCFG_TUSB_MCU=OPT_MCU_SAMX7X
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# suppress following warnings from mcu driver
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CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
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ASF_DIR = hw/mcu/microchip/same70
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# All source paths should be relative to the top level.
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LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
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SRC_C += \
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src/portable/microchip/samx7x/dcd_samx7x.c \
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$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
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$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
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$(ASF_DIR)/hpl/core/hpl_init.c \
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$(ASF_DIR)/hpl/usart/hpl_usart.c \
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$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
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$(ASF_DIR)/hal/src/hal_usart_async.c \
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$(ASF_DIR)/hal/src/hal_io.c \
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$(ASF_DIR)/hal/src/hal_atomic.c \
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$(ASF_DIR)/hal/utils/src/utils_ringbuffer.c
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INC += \
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$(TOP)/hw/bsp/$(BOARD) \
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$(TOP)/$(ASF_DIR) \
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$(TOP)/$(ASF_DIR)/config \
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$(TOP)/$(ASF_DIR)/same70b/include \
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$(TOP)/$(ASF_DIR)/hal/include \
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$(TOP)/$(ASF_DIR)/hal/utils/include \
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$(TOP)/$(ASF_DIR)/hpl/core \
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$(TOP)/$(ASF_DIR)/hpl/pio \
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$(TOP)/$(ASF_DIR)/hpl/pmc \
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$(TOP)/$(ASF_DIR)/hri \
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$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM7
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# For flash-jlink target
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JLINK_DEVICE = SAME70N19B
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# flash using edbg from https://github.com/ataradov/edbg
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# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
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# edbg -t same70 -F w0,1,1
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flash: $(BUILD)/$(PROJECT).bin
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edbg --verbose -t same70 -pv -f $<
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,215 @@
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/* Auto-generated config file hpl_usart_config.h */
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#ifndef HPL_USART_CONFIG_H
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#define HPL_USART_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_USART_1_ENABLE
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#define CONF_USART_1_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <o> Frame parity
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// <0x0=>Even parity
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// <0x1=>Odd parity
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// <0x2=>Parity forced to 0
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// <0x3=>Parity forced to 1
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// <0x4=>No parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_USART_1_PARITY
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#define CONF_USART_1_PARITY 0x4
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#endif
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// <o> Character Size
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// <0x0=>5 bits
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// <0x1=>6 bits
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// <0x2=>7 bits
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// <0x3=>8 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_USART_1_CHSIZE
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#define CONF_USART_1_CHSIZE 0x3
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#endif
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// <o> Stop Bit
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// <0=>1 stop bit
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// <1=>1.5 stop bits
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// <2=>2 stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_USART_1_SBMODE
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#define CONF_USART_1_SBMODE 0
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#endif
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// <o> Clock Output Select
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// <0=>The USART does not drive the SCK pin
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// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
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// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
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// <id> usart_clock_output_select
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#ifndef CONF_USART_1_CLKO
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#define CONF_USART_1_CLKO 0
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#endif
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// <o> Baud rate <1-3000000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_USART_1_BAUD
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#define CONF_USART_1_BAUD 9600
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_USART_1_ADVANCED_CONFIG
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#define CONF_USART_1_ADVANCED_CONFIG 0
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#endif
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// <o> Channel Mode
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// <0=>Normal Mode
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// <1=>Automatic Echo
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// <2=>Local Loopback
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// <3=>Remote Loopback
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// <i> Channel mode in USART frame
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// <id> usart_channel_mode
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#ifndef CONF_USART_1_CHMODE
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#define CONF_USART_1_CHMODE 0
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#endif
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// <q> 9 bits character enable
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// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
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// <id> usart_9bits_enable
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#ifndef CONF_USART_1_MODE9
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#define CONF_USART_1_MODE9 0
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#endif
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// <o> Variable Sync
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// <0=>User defined configuration
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// <1=>sync field is updated when a character is written into US_THR
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// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
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// <id> variable_sync
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#ifndef CONF_USART_1_VAR_SYNC
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#define CONF_USART_1_VAR_SYNC 0
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#endif
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// <o> Oversampling Mode
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// <0=>16 Oversampling
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// <1=>8 Oversampling
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// <i> Oversampling Mode in UART mode
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// <id> usart__oversampling_mode
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#ifndef CONF_USART_1_OVER
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#define CONF_USART_1_OVER 0
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#endif
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// <o> Inhibit Non Ack
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// <0=>The NACK is generated
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// <1=>The NACK is not generated
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// <i> Inhibit Non Acknowledge
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// <id> usart__inack
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#ifndef CONF_USART_1_INACK
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#define CONF_USART_1_INACK 1
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#endif
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// <o> Disable Successive NACK
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// <0=>NACK is sent on the ISO line as soon as a parity error occurs
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// <1=>Many parity errors generate a NACK on the ISO line
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// <i> Disable Successive NACK
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// <id> usart_dsnack
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#ifndef CONF_USART_1_DSNACK
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#define CONF_USART_1_DSNACK 0
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#endif
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// <o> Inverted Data
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// <0=>Data isn't inverted, nomal mode
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// <1=>Data is inverted
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// <i> Inverted Data
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// <id> usart_invdata
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#ifndef CONF_USART_1_INVDATA
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#define CONF_USART_1_INVDATA 0
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#endif
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// <o> Maximum Number of Automatic Iteration <0-7>
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// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
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// <id> usart_max_iteration
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#ifndef CONF_USART_1_MAX_ITERATION
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#define CONF_USART_1_MAX_ITERATION 0
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#endif
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// <q> Receive Line Filter enable
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// <i> whether the USART filters the receive line using a three-sample filter
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// <id> usart_receive_filter_enable
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#ifndef CONF_USART_1_FILTER
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#define CONF_USART_1_FILTER 0
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#endif
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// <q> Manchester Encoder/Decoder Enable
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// <i> whether the USART Manchester Encoder/Decoder
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// <id> usart_manchester_filter_enable
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#ifndef CONF_USART_1_MAN
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#define CONF_USART_1_MAN 0
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#endif
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// <o> Manchester Synchronization Mode
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// <0=>The Manchester start bit is a 0 to 1 transition
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// <1=>The Manchester start bit is a 1 to 0 transition
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// <i> Manchester Synchronization Mode
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// <id> usart_manchester_synchronization_mode
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#ifndef CONF_USART_1_MODSYNC
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#define CONF_USART_1_MODSYNC 0
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#endif
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// <o> Start Frame Delimiter Selector
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// <0=>Start frame delimiter is COMMAND or DATA SYNC
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// <1=>Start frame delimiter is one bit
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// <i> Start Frame Delimiter Selector
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// <id> usart_start_frame_delimiter
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#ifndef CONF_USART_1_ONEBIT
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#define CONF_USART_1_ONEBIT 0
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#endif
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_USART_1_FRACTIONAL
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#define CONF_USART_1_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>LSB is transmitted first
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// <1=>MSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_msbf
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#ifndef CONF_USART_1_MSBF
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#define CONF_USART_1_MSBF 0
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#endif
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// </e>
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#define CONF_USART_1_MODE 0x0
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// Calculate BAUD register value in UART mode
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#if CONF_USART1_CK_SRC < 3
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#ifndef CONF_USART_1_BAUD_CD
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#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
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#endif
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#ifndef CONF_USART_1_BAUD_FP
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#define CONF_USART_1_BAUD_FP \
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((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
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#endif
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#elif CONF_USART1_CK_SRC == 3
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// No division is active. The value written in US_BRGR has no effect.
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#ifndef CONF_USART_1_BAUD_CD
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#define CONF_USART_1_BAUD_CD 1
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#endif
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#ifndef CONF_USART_1_BAUD_FP
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#define CONF_USART_1_BAUD_FP 1
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#endif
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_USART_CONFIG_H
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,126 @@
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/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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/**
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* \def CONF_HCLK_FREQUENCY
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* \brief HCLK's Clock frequency
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*/
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#ifndef CONF_HCLK_FREQUENCY
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#define CONF_HCLK_FREQUENCY 300000000
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#endif
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/**
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* \def CONF_FCLK_FREQUENCY
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* \brief FCLK's Clock frequency
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*/
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#ifndef CONF_FCLK_FREQUENCY
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#define CONF_FCLK_FREQUENCY 300000000
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#endif
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/**
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* \def CONF_CPU_FREQUENCY
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* \brief CPU's Clock frequency
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*/
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#ifndef CONF_CPU_FREQUENCY
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#define CONF_CPU_FREQUENCY 300000000
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#endif
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/**
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* \def CONF_SLCK_FREQUENCY
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* \brief Slow Clock frequency
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*/
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#define CONF_SLCK_FREQUENCY 0
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/**
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* \def CONF_MCK_FREQUENCY
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* \brief Master Clock frequency
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*/
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#define CONF_MCK_FREQUENCY 150000000
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/**
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* \def CONF_PCK6_FREQUENCY
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* \brief Programmable Clock Controller 6 frequency
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*/
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#define CONF_PCK6_FREQUENCY 1714285
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// <h> USART Clock Settings
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// <o> USART Clock source
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// <0=> Master Clock (MCK)
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// <1=> MCK / 8 for USART
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// <2=> Programmable Clock Controller 4 (PMC_PCK4)
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// <3=> External Clock
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// <i> This defines the clock source for the USART
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// <id> usart_clock_source
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#ifndef CONF_USART1_CK_SRC
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#define CONF_USART1_CK_SRC 0
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#endif
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// <o> USART External Clock Input on SCK <1-4294967295>
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// <i> Inputs the external clock frequency on SCK
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// <id> usart_clock_freq
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#ifndef CONF_USART1_SCK_FREQ
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#define CONF_USART1_SCK_FREQ 10000000
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#endif
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// </h>
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/**
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* \def USART FREQUENCY
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* \brief USART's Clock frequency
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*/
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#ifndef CONF_USART1_FREQUENCY
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#define CONF_USART1_FREQUENCY 150000000
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#endif
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#ifndef CONF_SRC_USB_480M
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#define CONF_SRC_USB_480M 0
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#endif
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#ifndef CONF_SRC_USB_48M
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#define CONF_SRC_USB_48M 1
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#endif
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// <y> USB Full/Low Speed Clock
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// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
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// <id> usb_fsls_clock_source
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// <i> 48MHz clock source for low speed and full speed.
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// <i> It must be available when low speed is supported by host driver.
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// <i> It must be available when low power mode is selected.
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#ifndef CONF_USBHS_FSLS_SRC
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#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M
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#endif
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// <y> USB Clock Source(Normal/Low-power Mode Selection)
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// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M)
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// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
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// <id> usb_clock_source
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// <i> Select the clock source for USB.
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// <i> In normal mode, use "USB High Speed Clock (USB_480M)".
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// <i> In low-power mode, use "USB Clock Controller (USB_48M)".
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#ifndef CONF_USBHS_SRC
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#define CONF_USBHS_SRC CONF_SRC_USB_480M
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#endif
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/**
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* \def CONF_USBHS_FSLS_FREQUENCY
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* \brief USBHS's Full/Low Speed Clock Source frequency
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*/
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#ifndef CONF_USBHS_FSLS_FREQUENCY
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#define CONF_USBHS_FSLS_FREQUENCY 48000000
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#endif
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/**
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* \def CONF_USBHS_FREQUENCY
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* \brief USBHS's Selected Clock Source frequency
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*/
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#ifndef CONF_USBHS_FREQUENCY
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#define CONF_USBHS_FREQUENCY 480000000
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H
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@ -0,0 +1,159 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019, hathach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "sam.h"
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#include "bsp/board.h"
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#include "peripheral_clk_config.h"
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#include "hpl/usart/hpl_usart_base.h"
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#include "hpl/pmc/hpl_pmc.h"
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#include "hal/include/hal_init.h"
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#include "hal/include/hal_usart_async.h"
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#include "hal/include/hal_gpio.h"
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// You can get the board here:
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// https://www.aliexpress.com/item/1005003173783268.html
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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#define LED_PIN GPIO(GPIO_PORTA, 15)
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#define BUTTON_PIN GPIO(GPIO_PORTA, 21)
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#define BUTTON_STATE_ACTIVE 0
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#define UART_TX_PIN GPIO(GPIO_PORTB, 1)
|
||||
#define UART_RX_PIN GPIO(GPIO_PORTB, 0)
|
||||
|
||||
static struct usart_async_descriptor edbg_com;
|
||||
static uint8_t edbg_com_buffer[64];
|
||||
static volatile bool uart_busy = false;
|
||||
|
||||
static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
|
||||
{
|
||||
(void) io_descr;
|
||||
uart_busy = false;
|
||||
}
|
||||
|
||||
//------------- IMPLEMENTATION -------------//
|
||||
void board_init(void)
|
||||
{
|
||||
init_mcu();
|
||||
|
||||
/* Disable Watchdog */
|
||||
hri_wdt_set_MR_WDDIS_bit(WDT);
|
||||
|
||||
// LED
|
||||
_pmc_enable_periph_clock(ID_PIOB);
|
||||
gpio_set_pin_level(LED_PIN, false);
|
||||
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
|
||||
gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// Button
|
||||
_pmc_enable_periph_clock(ID_PIOA);
|
||||
gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
|
||||
gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
|
||||
gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
|
||||
|
||||
// Uart via EDBG Com
|
||||
_pmc_enable_periph_clock(ID_USART1);
|
||||
gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
|
||||
gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
|
||||
|
||||
usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
|
||||
usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
|
||||
usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
|
||||
usart_async_enable(&edbg_com);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer (samd SystemCoreClock may not correct)
|
||||
SysTick_Config(CONF_CPU_FREQUENCY / 1000);
|
||||
#endif
|
||||
|
||||
// Enable USB clock
|
||||
_pmc_enable_periph_clock(ID_USBHS);
|
||||
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB Interrupt Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void USBHS_Handler(void)
|
||||
{
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
gpio_set_pin_level(LED_PIN, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const * buf, int len)
|
||||
{
|
||||
// while until previous transfer is complete
|
||||
while(uart_busy) {}
|
||||
uart_busy = true;
|
||||
|
||||
io_write(&edbg_com.io, buf, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Required by __libc_init_array in startup code if we are compiling using
|
||||
// -nostdlib/-nostartfiles.
|
||||
void _init(void)
|
||||
{
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue