adding new hcd api, tested working with control xfer.
- hcd_edpt_open - hcd_edpt_xfer - hcd_edpt_xfer
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hathach
parent
9b74f0e98f
commit
13d08cd636
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@ -281,6 +281,74 @@ static tusb_error_t hcd_controller_stop(uint8_t hostid)
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//--------------------------------------------------------------------+
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// CONTROL PIPE API
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//--------------------------------------------------------------------+
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)
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{
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// FIXME control only for now
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(void) rhport;
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hcd_pipe_control_open(dev_addr, ep_desc->wMaxPacketSize.size);
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return true;
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}
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bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)
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{
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// FIXME control only for now
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hcd_pipe_control_close(dev_addr);
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return true;
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}
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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// FIXME control only for now
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if ( epnum == 0 )
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{
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ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
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ehci_qtd_t *p_data = get_control_qtds(dev_addr);
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qtd_init(p_data, (uint32_t) buffer, buflen);
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// first first data toggle is always 1 (data & setup stage)
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p_data->data_toggle = 1;
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p_data->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
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p_data->int_on_complete = 1;
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p_data->next.terminate = 1;
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// sw region
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p_qhd->p_qtd_list_head = p_data;
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p_qhd->p_qtd_list_tail = p_data;
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// attach TD
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p_qhd->qtd_overlay.next.address = (uint32_t) p_data;
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}
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return true;
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}
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
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ehci_qtd_t *p_setup = get_control_qtds(dev_addr);
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qtd_init(p_setup, (uint32_t) setup_packet, 8);
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p_setup->pid = EHCI_PID_SETUP;
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p_setup->int_on_complete = 1;
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p_setup->next.terminate = 1;
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// sw region
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p_qhd->p_qtd_list_head = p_setup;
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p_qhd->p_qtd_list_tail = p_setup;
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// attach TD
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p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
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return true;
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}
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tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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{
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ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
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@ -297,46 +365,46 @@ tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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return TUSB_ERROR_NONE;
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}
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bool hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
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{
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ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
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ehci_qtd_t *p_setup = get_control_qtds(dev_addr);
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ehci_qtd_t *p_data = p_setup + 1;
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ehci_qtd_t *p_status = p_setup + 2;
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//------------- SETUP Phase -------------//
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qtd_init(p_setup, (uint32_t) p_request, 8);
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p_setup->pid = EHCI_PID_SETUP;
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p_setup->next.address = (uint32_t) p_data;
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//------------- DATA Phase -------------//
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if (p_request->wLength > 0)
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{
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qtd_init(p_data, (uint32_t) data, p_request->wLength);
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p_data->data_toggle = 1;
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p_data->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_IN : EHCI_PID_OUT;
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}else
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{
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p_data = p_setup;
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}
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p_data->next.address = (uint32_t) p_status;
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//------------- STATUS Phase -------------//
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qtd_init(p_status, 0, 0); // zero-length data
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p_status->int_on_complete = 1;
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p_status->data_toggle = 1;
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p_status->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_OUT : EHCI_PID_IN; // reverse direction of data phase
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p_status->next.terminate = 1;
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//------------- Attach TDs list to Control Endpoint -------------//
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p_qhd->p_qtd_list_head = p_setup;
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p_qhd->p_qtd_list_tail = p_status;
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p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
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return true;
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}
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//bool hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
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//{
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// ehci_qhd_t * const p_qhd = get_control_qhd(dev_addr);
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//
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// ehci_qtd_t *p_setup = get_control_qtds(dev_addr);
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// ehci_qtd_t *p_data = p_setup + 1;
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// ehci_qtd_t *p_status = p_setup + 2;
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//
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// //------------- SETUP Phase -------------//
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// qtd_init(p_setup, (uint32_t) p_request, 8);
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// p_setup->pid = EHCI_PID_SETUP;
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// p_setup->next.address = (uint32_t) p_data;
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//
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// //------------- DATA Phase -------------//
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// if (p_request->wLength > 0)
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// {
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// qtd_init(p_data, (uint32_t) data, p_request->wLength);
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// p_data->data_toggle = 1;
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// p_data->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_IN : EHCI_PID_OUT;
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// }else
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// {
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// p_data = p_setup;
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// }
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// p_data->next.address = (uint32_t) p_status;
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//
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// //------------- STATUS Phase -------------//
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// qtd_init(p_status, 0, 0); // zero-length data
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// p_status->int_on_complete = 1;
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// p_status->data_toggle = 1;
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// p_status->pid = p_request->bmRequestType_bit.direction ? EHCI_PID_OUT : EHCI_PID_IN; // reverse direction of data phase
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// p_status->next.terminate = 1;
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//
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// //------------- Attach TDs list to Control Endpoint -------------//
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// p_qhd->p_qtd_list_head = p_setup;
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// p_qhd->p_qtd_list_tail = p_status;
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//
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// p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
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//
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// return true;
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//}
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tusb_error_t hcd_pipe_control_close(uint8_t dev_addr)
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{
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@ -123,6 +123,15 @@ void hcd_int_disable(uint8_t rhport);
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//--------------------------------------------------------------------+
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void hcd_event_handler(hcd_event_t const* event, bool in_isr);
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//--------------------------------------------------------------------+
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// Endpoints API
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//--------------------------------------------------------------------+
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc);
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bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
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//--------------------------------------------------------------------+
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// PIPE API
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//--------------------------------------------------------------------+
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@ -193,14 +193,27 @@ bool usbh_init(void)
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bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data)
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{
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usbh_device_t* dev = &_usbh_devices[dev_addr];
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const uint8_t rhport = dev->core_id;
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TU_ASSERT(osal_mutex_lock(dev->control.mutex_hdl, OSAL_TIMEOUT_NORMAL));
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dev->control.request = *request;
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dev->control.pipe_status = 0;
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TU_ASSERT(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data));
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TU_ASSERT(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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// Setup Stage
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hcd_setup_send(rhport, dev_addr, (uint8_t*) &dev->control.request);
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TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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// Data stage : first data toggle is always 1
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if ( request->wLength )
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{
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hcd_edpt_xfer(rhport, dev_addr, edpt_addr(0, request->bmRequestType_bit.direction), data, request->wLength);
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TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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}
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// Status : data toggle is always 1
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hcd_edpt_xfer(rhport, dev_addr, edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
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TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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osal_mutex_unlock(dev->control.mutex_hdl);
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@ -219,14 +232,24 @@ tusb_error_t usbh_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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osal_semaphore_reset( _usbh_devices[dev_addr].control.sem_hdl );
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//osal_mutex_reset( usbh_devices[dev_addr].control.mutex_hdl );
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TU_ASSERT_ERR( hcd_pipe_control_open(dev_addr, max_packet_size) );
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tusb_desc_endpoint_t ep0_desc =
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{
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.bLength = sizeof(tusb_desc_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0,
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.bmAttributes = { .xfer = TUSB_XFER_CONTROL },
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.wMaxPacketSize = { .size = max_packet_size },
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.bInterval = 0
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};
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hcd_edpt_open(_usbh_devices[dev_addr].core_id, dev_addr, &ep0_desc);
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return TUSB_ERROR_NONE;
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}
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static inline tusb_error_t usbh_pipe_control_close(uint8_t dev_addr)
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{
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TU_ASSERT_ERR( hcd_pipe_control_close(dev_addr) );
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hcd_edpt_close(_usbh_devices[dev_addr].core_id, dev_addr, 0);
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return TUSB_ERROR_NONE;
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}
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