clean up
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hathach
parent
4b2f32b778
commit
04797bc5a5
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@ -108,7 +108,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
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_ctrl_xfer.stage = STAGE_DATA;
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if (request->wLength)
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{
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// Note: initial data toggle is always 1
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// DATA stage: initial data toggle is always 1
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hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
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return true;
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}
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@ -123,7 +123,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
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TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
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}
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// data toggle is always 1
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// ACK stage: toggle is always 1
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hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
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break;
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@ -44,6 +44,28 @@
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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typedef struct
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{
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ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE];
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// for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
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// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
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ehci_qhd_t period_head_arr[4];
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// Note control qhd of dev0 is used as head of async list
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struct {
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ehci_qhd_t qhd;
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ehci_qtd_t qtd;
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}control[CFG_TUSB_HOST_DEVICE_MAX+1];
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ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT];
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ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);
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ehci_registers_t* regs;
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volatile uint32_t uframe_number;
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}ehci_data_t;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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@ -67,7 +89,8 @@ static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
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static inline ehci_qhd_t* qhd_async_head(uint8_t rhport)
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{
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(void) rhport;
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return qhd_control(0); // control qhd of dev0 is used as async head
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// control qhd of dev0 is used as async head
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return qhd_control(0);
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}
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static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
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@ -296,6 +319,59 @@ static void ehci_stop(uint8_t rhport)
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// Endpoint API
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//--------------------------------------------------------------------+
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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// TODO not support ISO yet
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TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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//------------- Prepare Queue Head -------------//
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ehci_qhd_t * p_qhd;
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if ( ep_desc->bEndpointAddress == 0 )
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{
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p_qhd = qhd_control(dev_addr);
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}else
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{
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p_qhd = qhd_find_free();
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}
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TU_ASSERT(p_qhd);
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qhd_init(p_qhd, dev_addr, ep_desc);
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// control of dev0 is always present as async head
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if ( dev_addr == 0 ) return true;
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// Insert to list
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ehci_link_t * list_head = NULL;
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switch (ep_desc->bmAttributes.xfer)
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{
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case TUSB_XFER_CONTROL:
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case TUSB_XFER_BULK:
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list_head = (ehci_link_t*) qhd_async_head(rhport);
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break;
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case TUSB_XFER_INTERRUPT:
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list_head = get_period_head(rhport, p_qhd->interval_ms);
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break;
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case TUSB_XFER_ISOCHRONOUS:
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// TODO iso is not supported
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break;
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default: break;
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}
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TU_ASSERT(list_head);
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// TODO might need to disable async/period list
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list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
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return true;
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}
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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(void) rhport;
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@ -365,59 +441,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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return true;
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}
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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// TODO not support ISO yet
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TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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//------------- Prepare Queue Head -------------//
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ehci_qhd_t * p_qhd;
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if ( ep_desc->bEndpointAddress == 0 )
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{
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p_qhd = qhd_control(dev_addr);
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}else
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{
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p_qhd = qhd_find_free();
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}
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TU_ASSERT(p_qhd);
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qhd_init(p_qhd, dev_addr, ep_desc);
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// control of dev0 is always present as async head
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if ( dev_addr == 0 ) return true;
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// Insert to list
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ehci_link_t * list_head = NULL;
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switch (ep_desc->bmAttributes.xfer)
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{
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case TUSB_XFER_CONTROL:
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case TUSB_XFER_BULK:
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list_head = (ehci_link_t*) qhd_async_head(rhport);
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break;
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case TUSB_XFER_INTERRUPT:
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list_head = get_period_head(rhport, p_qhd->interval_ms);
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break;
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case TUSB_XFER_ISOCHRONOUS:
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// TODO iso is not supported
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break;
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default: break;
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}
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TU_ASSERT(list_head);
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// TODO might need to disable async/period list
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list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
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return true;
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}
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bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
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{
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ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
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@ -24,12 +24,6 @@
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* This file is part of the TinyUSB stack.
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*/
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/** \ingroup Group_HCD
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* @{
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* \defgroup EHCI
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* \brief EHCI driver. All documents sources mentioned here (eg section 3.5) is referring to EHCI Specs unless state otherwise
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* @{ */
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#ifndef _TUSB_EHCI_H_
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#define _TUSB_EHCI_H_
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@ -309,12 +303,11 @@ enum ehci_usbcmd_pos_ {
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enum ehci_portsc_change_mask_{
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EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0),
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1),
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EHCI_PORTSC_MASK_PORT_EANBLED = TU_BIT(2),
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EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3),
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5),
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EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8),
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1),
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EHCI_PORTSC_MASK_PORT_EANBLED = TU_BIT(2),
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EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3),
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5),
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EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8),
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EHCI_PORTSC_MASK_ALL =
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
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@ -425,36 +418,8 @@ typedef volatile struct
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};
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}ehci_registers_t;
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//--------------------------------------------------------------------+
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// EHCI Data Organization
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//--------------------------------------------------------------------+
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typedef struct
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{
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ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE];
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// for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
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// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
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ehci_qhd_t period_head_arr[4];
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// Note control qhd of dev0 is used as head of async list
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struct {
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ehci_qhd_t qhd;
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ehci_qtd_t qtd;
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}control[CFG_TUSB_HOST_DEVICE_MAX+1];
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ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT];
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ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);
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ehci_registers_t* regs;
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volatile uint32_t uframe_number;
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}ehci_data_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_EHCI_H_ */
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/** @} */
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/** @} */
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