Add cache clean/invalidate.
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@ -94,6 +94,18 @@ static const tusb_desc_endpoint_t ep0_desc =
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.wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE },
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.wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE },
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};
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};
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TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size)
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{
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if (SCB->CCR & SCB_CCR_DC_Msk)
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{
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SCB_CleanInvalidateDCache_by_Addr(addr, size);
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}
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else
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{
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__DSB();
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__ISB();
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}
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}
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Device API
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// Device API
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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@ -141,8 +153,6 @@ void dcd_connect(uint8_t rhport)
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{
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{
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(void) rhport;
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(void) rhport;
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dcd_int_disable(rhport);
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dcd_int_disable(rhport);
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// Enable USB clock
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PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
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// Enable the USB controller in device mode
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// Enable the USB controller in device mode
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USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
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USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
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while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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@ -602,6 +612,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
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if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
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{
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{
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
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// address to 32-byte boundaries.
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CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
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uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
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uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
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if (dir == TUSB_DIR_OUT)
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if (dir == TUSB_DIR_OUT)
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{
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{
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@ -679,16 +692,23 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
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udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
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}
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}
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// Clean invalidate cache of linear part
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CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
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if (info.len_wrap)
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if (info.len_wrap)
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{
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{
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// Clean invalidate cache of wrapped part
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CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
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dma_desc[epnum - 1].next_desc = 0;
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dma_desc[epnum - 1].next_desc = 0;
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dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
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dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
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dma_desc[epnum - 1].chnl_ctrl =
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dma_desc[epnum - 1].chnl_ctrl =
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udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
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udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
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// Clean cache of wrapped DMA descriptor
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CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
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udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
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udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
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__DSB();
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__ISB();
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
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} else {
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} else {
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udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;
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udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;
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