Merge ea81d22f18 into 868f2bcda0
This commit is contained in:
Rafael Silva
GitHub
commit
acad51f889
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@ -48,6 +48,7 @@ jobs:
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- 'mm32'
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- 'msp432e4'
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- 'nrf'
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- 'ra'
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- 'rp2040'
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- 'samd11'
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- 'samd21'
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@ -13,6 +13,7 @@ latex
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.env
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.settings/
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.idea/
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.vscode/
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.gdb_history
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/examples/*/*/build*
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test_old/
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@ -149,3 +149,6 @@
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[submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
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path = hw/mcu/raspberry_pi/Pico-PIO-USB
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url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
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[submodule "hw/mcu/renesas/fsp"]
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path = hw/mcu/renesas/fsp
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url = https://github.com/renesas/fsp
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@ -119,6 +119,7 @@ Notable contributors
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- Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board
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- Rewrite documentation in rst and setup for readthedocs
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- Generalize Renesas driver and support RA family with EK-RA4M3 board
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`Raspberry Pi Team <https://github.com/raspberrypi>`__
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@ -48,7 +48,11 @@ The stack supports the following MCUs:
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- LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
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- **Raspberry Pi:** RP2040
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- **Renesas:** RX63N, RX65N, RX72N
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- **Renesas:**
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- RX Series: 63N, 65N, 72N
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- RA Series: RA2A1, RA2E1, RA2E2, RA2l1, RA4E1, RA4M1, RA4M2, RA4M3, RA4W1, RA6E1, RA6M1, RA6M2, RA6M3, RA6M4, RA6M5, RA6T1, RA6T2
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- **Silabs:** EFM32GG
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- **Sony:** CXD56
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- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+
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@ -59,9 +59,11 @@ Supported MCUs
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| | | 55 | ✔ | | ✔ | lpc_ip3511 | |
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+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
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| Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040 | |
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+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
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| Renesas | RX 63N, 65N, 72N | ✔ | ✔ | ✖ | usba | |
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+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
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+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
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| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | link | |
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| +-----+-----------------+--------+------+-----------+-------------------+--------------+
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| | RA | XXX | ✔ | ✔ | | link | |
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+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
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| Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | |
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+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
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| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | |
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@ -4,14 +4,15 @@ include ../../../tools/top.mk
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include ../../make.mk
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FREERTOS_SRC = lib/FreeRTOS-Kernel
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FREERTOS_PORT_PATH = lib/FreeRTOS-Kernel/portable/GCC
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INC += \
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src \
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src/FreeRTOSConfig \
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$(TOP)/hw \
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$(TOP)/$(FREERTOS_SRC)/include \
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$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
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$(TOP)/$(FREERTOS_PORT)
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# Example source
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EXAMPLE_SOURCE = \
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src/freertos_hook.c \
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@ -27,7 +28,7 @@ SRC_C += \
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$(FREERTOS_SRC)/queue.c \
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$(FREERTOS_SRC)/tasks.c \
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$(FREERTOS_SRC)/timers.c \
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$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
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# Suppress FreeRTOS warnings
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CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
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@ -4,20 +4,21 @@ include ../../../tools/top.mk
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include ../../make.mk
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FREERTOS_SRC = lib/FreeRTOS-Kernel
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FREERTOS_PORT_PATH = lib/FreeRTOS-Kernel/portable/GCC
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INC += \
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src \
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src/FreeRTOSConfig \
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$(TOP)/hw \
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$(TOP)/$(FREERTOS_SRC)/include \
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$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
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$(TOP)/$(FREERTOS_PORT)
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# Example source
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EXAMPLE_SOURCE = \
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src/freertos_hook.c \
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src/main.c \
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src/usb_descriptors.c
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SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
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# FreeRTOS source, all files in port folder
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@ -26,7 +27,7 @@ SRC_C += \
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$(FREERTOS_SRC)/queue.c \
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$(FREERTOS_SRC)/tasks.c \
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$(FREERTOS_SRC)/timers.c \
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$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
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# Suppress FreeRTOS warnings
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CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
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@ -133,13 +133,16 @@
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#elif CFG_TUSB_MCU == OPT_MCU_RP2040
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#include "pico.h"
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#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
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#include "em_device.h"
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#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
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// no header needed
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#elif CFG_TUSB_MCU == OPT_MCU_RAXXX
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#include "bsp_api.h"
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#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
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#include "gd32vf103.h"
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@ -52,7 +52,7 @@ INC += \
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$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM4F
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
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# For flash-jlink target
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JLINK_DEVICE = ATSAME51J19
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@ -31,7 +31,7 @@ INC += \
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$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM33_NTZ/non_secure
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
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# For flash-jlink target
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JLINK_DEVICE = DA14695
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@ -31,7 +31,7 @@ INC += \
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$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM33_NTZ/non_secure
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
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# For flash-jlink target
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JLINK_DEVICE = DA14699
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@ -37,7 +37,7 @@ INC += \
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$(TOP)/$(MCU_DIR)/inc
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM4F
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
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# For flash-jlink target
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JLINK_DEVICE = LPC4088
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@ -39,7 +39,7 @@ INC += \
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$(TOP)/$(MCU_DIR)/inc/config_43xx
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM4F
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
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# For flash-jlink target
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JLINK_DEVICE = LPC4357_M4
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@ -19,7 +19,7 @@ INC += \
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$(TOP)/$(FAMILY_PATH)/include
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# For freeRTOS port source
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FREERTOS_PORT = RISC-V
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
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# flash using dfu-util
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$(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
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@ -39,7 +39,7 @@ INC += \
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SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM0
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
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# For flash-jlink target
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JLINK_DEVICE = MKL25Z128xxx4
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@ -40,7 +40,7 @@ INC += \
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SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM0
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
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# For flash-jlink target
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JLINK_DEVICE = MKL25Z128xxx4
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@ -57,7 +57,7 @@ INC += \
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$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
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# For freeRTOS port source
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FREERTOS_PORT = RISC-V
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
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# For flash-jlink target
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JLINK_IF = jtag
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@ -59,5 +59,5 @@ INC += \
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SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM7/r0p1
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
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@ -40,7 +40,7 @@ INC += \
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SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
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# For freeRTOS port source
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||||
FREERTOS_PORT = ARM_CM0
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
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# For flash-jlink target
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JLINK_DEVICE = MKL25Z128xxx4
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|
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@ -36,4 +36,4 @@ INC += \
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|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
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|
|
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@ -34,4 +34,4 @@ INC += \
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|||
$(TOP)/$(MCU_DIR)/inc/config_18xx
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|
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# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
|
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@ -51,4 +51,4 @@ INC += \
|
|||
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
|
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|
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# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
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FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
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|
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|
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@ -64,4 +64,4 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
|
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LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM33_NTZ/non_secure
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
|
||||
|
|
|
|||
|
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@ -36,7 +36,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC11U37/401
|
||||
|
|
|
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|
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@ -32,7 +32,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC11U68
|
||||
|
|
|
|||
|
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@ -36,7 +36,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC1347
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC1769
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
|
|||
LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
JLINK_DEVICE = LPC51U68
|
||||
PYOCD_TARGET = LPC51U68
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC1768
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INC += \
|
|||
$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# flash target using on-board
|
||||
flash: flash-jlink
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ INC += \
|
|||
SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = MSP432E401Y
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/inc/config_43xx
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC4330
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
|
|||
ASFLAGS += -D__HEAP_SIZE=0
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = $(MCU_VARIANT)_xxaa
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = NUC121SC2AE
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = NUC125SC2AE
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = NUC126VG4AE
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = NUC120LE3
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = NUC505YO13Y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
CFLAGS += \
|
||||
-mcpu=cortex-m33 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-sp-d16 \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_RAXXX
|
||||
|
||||
FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
|
||||
FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/ek_ra4m3.ld
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA4M3AF
|
||||
JLINK_IF = SWD
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022, Rafael Silva
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "r_ioport_api.h"
|
||||
#include "renesas.h"
|
||||
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
|
||||
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
|
||||
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_05)
|
||||
#define SW2 (BSP_IO_PORT_00_PIN_06)
|
||||
#define LED1 (BSP_IO_PORT_04_PIN_15)
|
||||
#define LED3 (BSP_IO_PORT_04_PIN_00)
|
||||
#define LED2 (BSP_IO_PORT_04_PIN_04)
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
void usbfs_d0fifo_handler(void);
|
||||
void usbfs_d1fifo_handler(void);
|
||||
|
||||
BSP_DONT_REMOVE const
|
||||
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
|
||||
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
|
||||
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
|
||||
{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void usbfs_interrupt_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
void usbfs_resume_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
void usbfs_d0fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
void usbfs_d1fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Init systick */
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
|
||||
return lvl;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
int close(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
int fstat(int fd, void *pstat)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pstat;
|
||||
return 0;
|
||||
}
|
||||
off_t lseek(int fd, off_t pos, int whence)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pos;
|
||||
(void) whence;
|
||||
return 0;
|
||||
}
|
||||
int isatty(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x20000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x100000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x90000000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* This is a non-secure project if the OPTION_SETTING region is non-zero and it does not start at the base address for
|
||||
* secure option settings (meaning the secure option settings were already allocated in the secure project). */
|
||||
__TZ_NS_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) != ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* This is a secure project if the option setting base address matches the option setting base address for secure
|
||||
* option settings. This is also set for flat projects because the CPU runs in secure mode for flat projects.
|
||||
* This is not defined for projects that do not support TrustZone. */
|
||||
__TZ_S_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) == ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* If a flat (secure) project has defined RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = __TZ_S_PROJECT && DEFINED(RAM_NS_BUFFER_LENGTH);
|
||||
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
OPTION_SETTING_START_NS = 0x0100A180;
|
||||
OPTION_SETTING_START_S = 0x0100A100;
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* ROM Registers start at address 0x00000400 */
|
||||
. = __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = __ROM_Start + 0x500;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section. */
|
||||
.gnu.sgstubs : ALIGN (1024)
|
||||
{
|
||||
. = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.qspi_non_retentive : AT (__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_N = __ID_Code_End;
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING);
|
||||
|
||||
.option_setting :
|
||||
{
|
||||
__OPTION_SETTING_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = OPTION_SETTING_START_NS;
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#include "board.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
#undef RA_NOT_DEFINED
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
|
||||
#define BSP_CFG_HEAP_BYTES (0x400)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL Mul x24.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL2 Mul x24.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */
|
||||
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/* generated configuration header file through renesas e2 studio */
|
||||
#ifndef BSP_MCU_FAMILY_CFG_H_
|
||||
#define BSP_MCU_FAMILY_CFG_H_
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_info.h"
|
||||
|
||||
#define BSP_CFG_MCU_PART_SERIES (4)
|
||||
#define BSP_MCU_R7FA4M3AF3CFB
|
||||
#define BSP_ROM_SIZE_BYTES (1048576)
|
||||
#define BSP_RAM_SIZE_BYTES (131072)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (144)
|
||||
|
||||
#define BSP_MCU_GROUP_RA4M3 (1)
|
||||
#define BSP_LOCO_HZ (32768)
|
||||
#define BSP_MOCO_HZ (8000000)
|
||||
#define BSP_SUB_CLOCK_HZ (32768)
|
||||
#if BSP_CFG_HOCO_FREQUENCY == 0
|
||||
#define BSP_HOCO_HZ (16000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 1
|
||||
#define BSP_HOCO_HZ (18000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 2
|
||||
#define BSP_HOCO_HZ (20000000)
|
||||
#else
|
||||
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_FLL_ENABLE (0)
|
||||
|
||||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
|
||||
#define BSP_MCU_VBATT_SUPPORT (1)
|
||||
|
||||
#if defined(_RA_TZ_SECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (1)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#elif defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (1)
|
||||
#else
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#endif
|
||||
|
||||
/* TrustZone Settings */
|
||||
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
|
||||
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
|
||||
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
|
||||
|
||||
/* CMSIS TrustZone Settings */
|
||||
#define SCB_CSR_AIRCR_INIT (1)
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL (0)
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
|
||||
#define SCB_AIRCR_PRIS_VAL (0)
|
||||
#define TZ_FPU_NS_USAGE (1)
|
||||
#define SCB_NSACR_CP10_11_VAL (3U)
|
||||
|
||||
#define FPU_FPCCR_TS_VAL (1U)
|
||||
#define FPU_FPCCR_CLRONRETS_VAL (1)
|
||||
|
||||
#define FPU_FPCCR_CLRONRET_VAL (1)
|
||||
|
||||
/* The C-Cache line size that is configured during startup. */
|
||||
#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
|
||||
|
||||
/* Type 1 Peripheral Security Attribution */
|
||||
|
||||
/* Peripheral Security Attribution Register (PSAR) Settings */
|
||||
#define BSP_TZ_CFG_PSARB \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARC \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARD \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
|
||||
0xffae07f0) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARE \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
|
||||
#define BSP_TZ_CFG_MSSAR \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
|
||||
0xfffffffc) /* Unused */
|
||||
|
||||
/* Type 2 Peripheral Security Attribution */
|
||||
|
||||
/* Security attribution for Cache registers. */
|
||||
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for RSTSRn registers. */
|
||||
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for registers of LVD channels. */
|
||||
#define BSP_TZ_CFG_LVDSAR \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
|
||||
0xFFFFFFFCU)
|
||||
|
||||
/* Security attribution for LPM registers. */
|
||||
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
|
||||
/* Deep Standby Interrupt Factor Security Attribution Register. */
|
||||
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for CGC registers. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect all CGC registers from Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers. */
|
||||
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#define BSP_TZ_CFG_ICUSARA \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#define BSP_TZ_CFG_ICUSARC \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
// #if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
// #else
|
||||
// #define BSP_TZ_CFG_DTC_USED (1U)
|
||||
// #endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFEFEU)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings.
|
||||
*/
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL \
|
||||
(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table
|
||||
* g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
|
||||
/* Dual Mode Select Register */
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
|
||||
/* Block Protection Register 0 */
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~(0U))
|
||||
/* Block Protection Register 1 */
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~(0U))
|
||||
/* Block Protection Register 2 */
|
||||
#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
|
||||
|
||||
# Cross Compiler for RA
|
||||
CROSS_COMPILE = arm-none-eabi-
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
CFLAGS += \
|
||||
-Wno-error=undef \
|
||||
-Wno-error=strict-prototypes \
|
||||
-Wno-error=cast-align \
|
||||
-Wno-error=cast-qual \
|
||||
-Wno-error=unused-but-set-variable \
|
||||
-Wno-error=unused-variable \
|
||||
-mthumb \
|
||||
-nostdlib \
|
||||
-nostartfiles \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding
|
||||
|
||||
SRC_C += \
|
||||
src/portable/renesas/link/dcd_link.c \
|
||||
src/portable/renesas/link/hcd_link.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/r_ioport/r_ioport.c \
|
||||
$(FSP_BOARD_DIR)/board_init.c \
|
||||
$(FSP_BOARD_DIR)/board_leds.c
|
||||
|
||||
INC += \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(BOARD_PATH)/fsp_cfg \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
|
||||
$(TOP)/$(FSP_MCU_DIR) \
|
||||
$(TOP)/$(FSP_BOARD_DIR)
|
||||
|
||||
# For freeRTOS port source
|
||||
# hack to use the port provided by renesas
|
||||
FREERTOS_PORT = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
|
||||
|
|
@ -11,7 +11,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx63n
|
|||
LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = RX600
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R5F5631F
|
||||
|
|
|
|||
|
|
@ -201,6 +201,11 @@ void board_init(void)
|
|||
IEN(SCI0, RXI0) = 1;
|
||||
IEN(SCI0, TXI0) = 1;
|
||||
IEN(SCI0, TEI0) = 1;
|
||||
|
||||
/* Enable USB0 */
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(USB0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx65n
|
|||
LD_FILE = $(BOARD_PATH)/r5f565ne.ld
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = RX600
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R5F565NE
|
||||
|
|
|
|||
|
|
@ -248,6 +248,11 @@ void board_init(void)
|
|||
IEN(ICU,GROUPBL0) = 1;
|
||||
EN(SCI5, TEI5) = 1;
|
||||
|
||||
/* Enable USB0 */
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(USB0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
|
||||
/* setup USBI0 interrupt. */
|
||||
IR(USB0, USBI0) = 0;
|
||||
IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ CFLAGS += \
|
|||
CFLAGS += -Wno-error=redundant-decls
|
||||
|
||||
SRC_C += \
|
||||
src/portable/renesas/usba/dcd_usba.c \
|
||||
src/portable/renesas/usba/hcd_usba.c \
|
||||
src/portable/renesas/link/dcd_link.c \
|
||||
src/portable/renesas/link/hcd_link.c \
|
||||
$(MCU_DIR)/vects.c
|
||||
|
||||
INC += \
|
||||
|
|
|
|||
|
|
@ -37,4 +37,4 @@ INC += \
|
|||
$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# flash using bossac at least version 1.8
|
||||
# can be found in arduino15/packages/arduino/tools/bossac/
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# flash using bossac at least version 1.8
|
||||
# can be found in arduino15/packages/arduino/tools/bossac/
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ INC += \
|
|||
$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = ATSAME54P20
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ INC += \
|
|||
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM7
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = SAME70N19B
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ INC += \
|
|||
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM7
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = SAME70Q21B
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ INC += \
|
|||
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = ATSAMG55J19
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ INC += \
|
|||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# flash using bossac at least version 1.8
|
||||
# can be found in arduino15/packages/arduino/tools/bossac/
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ INC += \
|
|||
$(TOP)/hw/bsp/$(BOARD)
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = EFM32GG12B810F1024
|
||||
|
|
|
|||
|
|
@ -37,4 +37,4 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = stm32f103c8
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ INC += \
|
|||
$(TOP)/hw/bsp/$(BOARD)
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM3
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = stm32f207zg
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ INC += \
|
|||
$(TOP)/hw/bsp/$(BOARD)
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = stm32f303vc
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
|
|
|||
|
|
@ -51,4 +51,4 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM7/r0p1
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
|
|
|||
|
|
@ -53,5 +53,5 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM7/r0p1
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ INC += \
|
|||
$(TOP)/hw/bsp/$(BOARD)
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM0
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = STM32L053R8
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ INC += \
|
|||
$(TOP)/$(BOARD_PATH)
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ INC += \
|
|||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
|
|
|||
|
|
@ -33,4 +33,4 @@ SRC_C += \
|
|||
$(MCU_DIR)/Source/GCC/tm4c123_startup.c
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
|
|
|||
|
|
@ -37,4 +37,4 @@ INC += \
|
|||
$(TOP)/$(MCU_DIR)/XMCLib/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM4F
|
||||
FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 8dc14709f2a6518b43f71efad70d900b7718d9f1
|
||||
|
|
@ -233,7 +233,7 @@
|
|||
#define TUP_DCD_ENDPOINT_MAX 7
|
||||
|
||||
//------------- Renesas -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
|
||||
#define TUP_DCD_ENDPOINT_MAX 10
|
||||
|
||||
//------------- GigaDevice -------------//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2020 Koji Kitayama
|
||||
|
|
@ -31,79 +31,38 @@
|
|||
// We disable SOF for now until needed later on
|
||||
#define USE_SOF 0
|
||||
|
||||
#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX65X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX65X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RAXXX)
|
||||
|
||||
#include "device/dcd.h"
|
||||
#include "iodefine.h"
|
||||
#include "link_type.h"
|
||||
|
||||
#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
|
||||
#include "link_rx.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
|
||||
#include "link_ra.h"
|
||||
#else
|
||||
#error "Unsupported MCU"
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
#define SYSTEM_PRCR_PRC1 (1<<1)
|
||||
#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
|
||||
|
||||
#define USB_FIFOSEL_TX ((uint16_t)(1u<<5))
|
||||
#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8))
|
||||
#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10))
|
||||
#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10))
|
||||
#define USB_IS0_CTSQ ((uint16_t)(7u))
|
||||
#define USB_IS0_DVSQ ((uint16_t)(7u<<4))
|
||||
#define USB_IS0_VALID ((uint16_t)(1u<<3))
|
||||
#define USB_IS0_BRDY ((uint16_t)(1u<<8))
|
||||
#define USB_IS0_NRDY ((uint16_t)(1u<<9))
|
||||
#define USB_IS0_BEMP ((uint16_t)(1u<<10))
|
||||
#define USB_IS0_CTRT ((uint16_t)(1u<<11))
|
||||
#define USB_IS0_DVST ((uint16_t)(1u<<12))
|
||||
#define USB_IS0_SOFR ((uint16_t)(1u<<13))
|
||||
#define USB_IS0_RESM ((uint16_t)(1u<<14))
|
||||
#define USB_IS0_VBINT ((uint16_t)(1u<<15))
|
||||
#define USB_IS1_SACK ((uint16_t)(1u<<4))
|
||||
#define USB_IS1_SIGN ((uint16_t)(1u<<5))
|
||||
#define USB_IS1_EOFERR ((uint16_t)(1u<<6))
|
||||
#define USB_IS1_ATTCH ((uint16_t)(1u<<11))
|
||||
#define USB_IS1_DTCH ((uint16_t)(1u<<12))
|
||||
#define USB_IS1_BCHG ((uint16_t)(1u<<14))
|
||||
#define USB_IS1_OVRCR ((uint16_t)(1u<<15))
|
||||
/* LINK core registers */
|
||||
#if defined(__CCRX__)
|
||||
#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
|
||||
#else
|
||||
#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
|
||||
#endif
|
||||
|
||||
#define USB_IS0_CTSQ_MSK (7u)
|
||||
#define USB_IS0_CTSQ_SETUP (1u)
|
||||
#define USB_IS0_DVSQ_DEF (1u<<4)
|
||||
#define USB_IS0_DVSQ_ADDR (2u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP0 (4u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP1 (5u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP2 (6u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP3 (7u<<4)
|
||||
|
||||
#define USB_PIPECTR_PID_NAK (0u)
|
||||
#define USB_PIPECTR_PID_BUF (1u)
|
||||
#define USB_PIPECTR_PID_STALL (2u)
|
||||
#define USB_PIPECTR_CCPL (1u<<2)
|
||||
#define USB_PIPECTR_SQMON (1u<<6)
|
||||
#define USB_PIPECTR_SQCLR (1u<<8)
|
||||
#define USB_PIPECTR_ACLRM (1u<<9)
|
||||
#define USB_PIPECTR_INBUFM (1u<<14)
|
||||
#define USB_PIPECTR_BSTS (1u<<15)
|
||||
|
||||
#define USB_FIFOCTR_DTLN (0x1FF)
|
||||
#define USB_FIFOCTR_FRDY (1u<<13)
|
||||
#define USB_FIFOCTR_BCLR (1u<<14)
|
||||
#define USB_FIFOCTR_BVAL (1u<<15)
|
||||
|
||||
#define USB_PIPECFG_SHTNAK (1u<<7)
|
||||
#define USB_PIPECFG_DBLB (1u<<9)
|
||||
#define USB_PIPECFG_BULK (1u<<14)
|
||||
#define USB_PIPECFG_ISO (3u<<14)
|
||||
#define USB_PIPECFG_INT (2u<<14)
|
||||
|
||||
#define FIFO_REQ_CLR (1u)
|
||||
#define FIFO_COMPLETE (1u<<1)
|
||||
|
||||
// Start of definition of packed structs (used by the CCRX toolchain)
|
||||
/* Start of definition of packed structs (used by the CCRX toolchain) */
|
||||
TU_ATTR_PACKED_BEGIN
|
||||
TU_ATTR_BIT_FIELD_ORDER_BEGIN
|
||||
|
||||
typedef struct {
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
union {
|
||||
struct {
|
||||
uint16_t : 8;
|
||||
|
|
@ -116,7 +75,7 @@ typedef struct {
|
|||
uint16_t TRN;
|
||||
} reg_pipetre_t;
|
||||
|
||||
typedef union {
|
||||
typedef union TU_ATTR_PACKED {
|
||||
struct {
|
||||
volatile uint16_t u8: 8;
|
||||
volatile uint16_t : 0;
|
||||
|
|
@ -150,28 +109,6 @@ typedef struct
|
|||
//--------------------------------------------------------------------+
|
||||
static dcd_data_t _dcd;
|
||||
|
||||
static uint32_t disable_interrupt(void)
|
||||
{
|
||||
uint32_t pswi;
|
||||
#if defined(__CCRX__)
|
||||
pswi = get_psw() & 0x010000;
|
||||
clrpsw_i();
|
||||
#else
|
||||
pswi = __builtin_rx_mvfc(0) & 0x010000;
|
||||
__builtin_rx_clrpsw('I');
|
||||
#endif
|
||||
return pswi;
|
||||
}
|
||||
|
||||
static void enable_interrupt(uint32_t pswi)
|
||||
{
|
||||
#if defined(__CCRX__)
|
||||
set_psw(get_psw() | pswi);
|
||||
#else
|
||||
__builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
|
||||
#endif
|
||||
}
|
||||
|
||||
static unsigned find_pipe(unsigned xfer)
|
||||
{
|
||||
switch (xfer) {
|
||||
|
|
@ -202,22 +139,18 @@ static unsigned find_pipe(unsigned xfer)
|
|||
|
||||
static volatile uint16_t* get_pipectr(unsigned num)
|
||||
{
|
||||
volatile uint16_t *ctr = NULL;
|
||||
if (num) {
|
||||
ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
|
||||
ctr += num - 1;
|
||||
return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
|
||||
} else {
|
||||
ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
|
||||
return (volatile uint16_t*)&(LINK_REG->DCPCTR);
|
||||
}
|
||||
return ctr;
|
||||
}
|
||||
|
||||
static volatile reg_pipetre_t* get_pipetre(unsigned num)
|
||||
{
|
||||
volatile reg_pipetre_t* tre = NULL;
|
||||
if ((1 <= num) && (num <= 5)) {
|
||||
tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
|
||||
tre += num - 1;
|
||||
tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
|
||||
}
|
||||
return tre;
|
||||
}
|
||||
|
|
@ -225,36 +158,31 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num)
|
|||
static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
volatile uint16_t *ctr = NULL;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
if (epn) {
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned num = _dcd.ep[dir][epn];
|
||||
if (num) {
|
||||
ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
|
||||
ctr += num - 1;
|
||||
}
|
||||
return get_pipectr(num);
|
||||
} else {
|
||||
ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
|
||||
return get_pipectr(0);
|
||||
}
|
||||
return ctr;
|
||||
}
|
||||
|
||||
static unsigned edpt0_max_packet_size(void)
|
||||
{
|
||||
return USB0.DCPMAXP.BIT.MXPS;
|
||||
return LINK_REG->DCPMAXP_b.MXPS;
|
||||
}
|
||||
|
||||
static unsigned edpt_max_packet_size(unsigned num)
|
||||
{
|
||||
USB0.PIPESEL.WORD = num;
|
||||
return USB0.PIPEMAXP.WORD;
|
||||
LINK_REG->PIPESEL = num;
|
||||
return LINK_REG->PIPEMAXP;
|
||||
}
|
||||
|
||||
static inline void pipe_wait_for_ready(unsigned num)
|
||||
{
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
|
||||
while (!USB0.D0FIFOCTR.BIT.FRDY) ;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
|
||||
while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
|
||||
}
|
||||
|
||||
static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
|
||||
|
|
@ -316,13 +244,14 @@ static bool pipe0_xfer_in(void)
|
|||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
if (pipe->ff) {
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN);
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN);
|
||||
} else {
|
||||
pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
|
||||
pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
}
|
||||
if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
if (len < mps)
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
pipe->remaining = rem - len;
|
||||
return false;
|
||||
}
|
||||
|
|
@ -333,18 +262,19 @@ static bool pipe0_xfer_out(void)
|
|||
const unsigned rem = pipe->remaining;
|
||||
|
||||
const unsigned mps = edpt0_max_packet_size();
|
||||
const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
|
||||
const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
|
||||
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
if (pipe->ff) {
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT);
|
||||
} else {
|
||||
pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
|
||||
pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
}
|
||||
if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
if (len < mps)
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
pipe->remaining = rem - len;
|
||||
if ((len < mps) || (rem == len)) {
|
||||
pipe->buf = NULL;
|
||||
|
|
@ -363,22 +293,23 @@ static bool pipe_xfer_in(unsigned num)
|
|||
return true;
|
||||
}
|
||||
|
||||
USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
|
||||
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
pipe_wait_for_ready(num);
|
||||
const unsigned len = TU_MIN(rem, mps);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
if (pipe->ff) {
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN);
|
||||
} else {
|
||||
pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
|
||||
pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
}
|
||||
if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
if (len < mps)
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
return false;
|
||||
}
|
||||
|
|
@ -388,24 +319,25 @@ static bool pipe_xfer_out(unsigned num)
|
|||
pipe_state_t *pipe = &_dcd.pipe[num];
|
||||
const unsigned rem = pipe->remaining;
|
||||
|
||||
USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
|
||||
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
pipe_wait_for_ready(num);
|
||||
const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN;
|
||||
const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN;
|
||||
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
if (pipe->ff) {
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
|
||||
pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT);
|
||||
} else {
|
||||
pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
|
||||
pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
}
|
||||
if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
if (len < mps)
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
if ((len < mps) || (rem == len)) {
|
||||
pipe->buf = NULL;
|
||||
return NULL != buf;
|
||||
|
|
@ -416,13 +348,13 @@ static bool pipe_xfer_out(unsigned num)
|
|||
static void process_setup_packet(uint8_t rhport)
|
||||
{
|
||||
uint16_t setup_packet[4];
|
||||
if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return;
|
||||
USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD);
|
||||
setup_packet[1] = USB0.USBVAL;
|
||||
setup_packet[2] = USB0.USBINDX;
|
||||
setup_packet[3] = USB0.USBLENG;
|
||||
USB0.INTSTS0.WORD = ~USB_IS0_VALID;
|
||||
if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return;
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
setup_packet[0] = tu_le16toh(LINK_REG->USBREQ);
|
||||
setup_packet[1] = LINK_REG->USBVAL;
|
||||
setup_packet[2] = LINK_REG->USBINDX;
|
||||
setup_packet[3] = LINK_REG->USBLENG;
|
||||
LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk);
|
||||
dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
|
||||
}
|
||||
|
||||
|
|
@ -430,7 +362,7 @@ static void process_status_completion(uint8_t rhport)
|
|||
{
|
||||
uint8_t ep_addr;
|
||||
/* Check the data stage direction */
|
||||
if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) {
|
||||
if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) {
|
||||
/* IN transfer. */
|
||||
ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
|
||||
} else {
|
||||
|
|
@ -444,11 +376,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
|
|||
{
|
||||
/* configure fifo direction and access unit settings */
|
||||
if (ep_addr) { /* IN, 2 bytes */
|
||||
USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
|
||||
while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
|
||||
} else { /* OUT, a byte */
|
||||
USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
|
||||
while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
|
||||
LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
|
||||
(TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
|
||||
while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
|
||||
} else { /* OUT, a byte */
|
||||
LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
|
||||
while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
|
||||
}
|
||||
|
||||
pipe_state_t *pipe = &_dcd.pipe[0];
|
||||
|
|
@ -458,14 +391,14 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
|
|||
if (total_bytes) {
|
||||
pipe->buf = buffer;
|
||||
if (ep_addr) { /* IN */
|
||||
TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
|
||||
TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
|
||||
pipe0_xfer_in();
|
||||
}
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
} else {
|
||||
/* ZLP */
|
||||
pipe->buf = NULL;
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
|
||||
LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -487,11 +420,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
|
|||
if (total_bytes) {
|
||||
pipe_xfer_in(num);
|
||||
} else { /* ZLP */
|
||||
USB0.D0FIFOSEL.WORD = num;
|
||||
LINK_REG->D0FIFOSEL = num;
|
||||
pipe_wait_for_ready(num);
|
||||
USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
}
|
||||
} else {
|
||||
#if defined(__CCRX__)
|
||||
|
|
@ -502,11 +435,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
|
|||
if (pt) {
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
|
||||
if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
pt->TRE = TU_BIT(8);
|
||||
pt->TRN = (total_bytes + mps - 1) / mps;
|
||||
pt->TRENB = 1;
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
}
|
||||
// TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
|
||||
|
|
@ -558,28 +491,28 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
|
|||
|
||||
static void process_bus_reset(uint8_t rhport)
|
||||
{
|
||||
USB0.BEMPENB.WORD = 1;
|
||||
USB0.BRDYENB.WORD = 1;
|
||||
USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
USB0.D1FIFOSEL.WORD = 0;
|
||||
while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD));
|
||||
volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD));
|
||||
LINK_REG->BEMPENB = 1;
|
||||
LINK_REG->BRDYENB = 1;
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
LINK_REG->D1FIFOSEL = 0;
|
||||
while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0]));
|
||||
volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E));
|
||||
for (int i = 1; i <= 5; ++i) {
|
||||
USB0.PIPESEL.WORD = i;
|
||||
USB0.PIPECFG.WORD = 0;
|
||||
*ctr = USB_PIPECTR_ACLRM;
|
||||
LINK_REG->PIPESEL = i;
|
||||
LINK_REG->PIPECFG = 0;
|
||||
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
|
||||
*ctr = 0;
|
||||
++ctr;
|
||||
*tre = TU_BIT(8);
|
||||
tre += 2;
|
||||
}
|
||||
for (int i = 6; i <= 9; ++i) {
|
||||
USB0.PIPESEL.WORD = i;
|
||||
USB0.PIPECFG.WORD = 0;
|
||||
*ctr = USB_PIPECTR_ACLRM;
|
||||
LINK_REG->PIPESEL = i;
|
||||
LINK_REG->PIPECFG = 0;
|
||||
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
|
||||
*ctr = 0;
|
||||
++ctr;
|
||||
}
|
||||
|
|
@ -589,7 +522,7 @@ static void process_bus_reset(uint8_t rhport)
|
|||
|
||||
static void process_set_address(uint8_t rhport)
|
||||
{
|
||||
const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
|
||||
const uint32_t addr = LINK_REG->USBADDR_b.USBADDR;
|
||||
if (!addr) return;
|
||||
const tusb_control_request_t setup_packet = {
|
||||
#if defined(__CCRX__)
|
||||
|
|
@ -611,56 +544,40 @@ static void process_set_address(uint8_t rhport)
|
|||
void dcd_init(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* Enable USB0 */
|
||||
uint32_t pswi = disable_interrupt();
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(USB0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
enable_interrupt(pswi);
|
||||
USB0.SYSCFG.BIT.SCKE = 1;
|
||||
while (!USB0.SYSCFG.BIT.SCKE) ;
|
||||
USB0.SYSCFG.BIT.DRPD = 0;
|
||||
USB0.SYSCFG.BIT.DCFM = 0;
|
||||
USB0.SYSCFG.BIT.USBE = 1;
|
||||
|
||||
USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
USB0.PHYSLEW.LONG = 0x5;
|
||||
IR(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IR(USB0, USBI0) = 0;
|
||||
#endif
|
||||
LINK_REG->SYSCFG_b.SCKE = 1;
|
||||
while (!LINK_REG->SYSCFG_b.SCKE) ;
|
||||
LINK_REG->SYSCFG_b.DRPD = 0;
|
||||
LINK_REG->SYSCFG_b.DCFM = 0;
|
||||
LINK_REG->SYSCFG_b.USBE = 1;
|
||||
|
||||
// MCU specific PHY init
|
||||
link_phy_init();
|
||||
|
||||
LINK_REG->PHYSLEW = 0x5;
|
||||
LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
|
||||
|
||||
/* Setup default control pipe */
|
||||
USB0.DCPMAXP.BIT.MXPS = 64;
|
||||
USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP |
|
||||
USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM;
|
||||
USB0.BEMPENB.WORD = 1;
|
||||
USB0.BRDYENB.WORD = 1;
|
||||
LINK_REG->DCPMAXP_b.MXPS = 64;
|
||||
LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk |
|
||||
LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) |
|
||||
LINK_REG_INTSTS0_RESM_Msk;
|
||||
LINK_REG->BEMPENB = 1;
|
||||
LINK_REG->BRDYENB = 1;
|
||||
|
||||
if (USB0.INTSTS0.BIT.VBSTS) {
|
||||
if (LINK_REG->INTSTS0_b.VBSTS) {
|
||||
dcd_connect(rhport);
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 1;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 1;
|
||||
#endif
|
||||
link_int_enable(rhport);
|
||||
}
|
||||
|
||||
void dcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 0;
|
||||
#endif
|
||||
link_int_disable(rhport);
|
||||
}
|
||||
|
||||
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
||||
|
|
@ -672,19 +589,19 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
|||
void dcd_remote_wakeup(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0.DVSTCTR0.BIT.WKUP = 1;
|
||||
LINK_REG->DVSTCTR0_b.WKUP = 1;
|
||||
}
|
||||
|
||||
void dcd_connect(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0.SYSCFG.BIT.DPRPU = 1;
|
||||
LINK_REG->SYSCFG_b.DPRPU = 1;
|
||||
}
|
||||
|
||||
void dcd_disconnect(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0.SYSCFG.BIT.DPRPU = 0;
|
||||
LINK_REG->SYSCFG_b.DPRPU = 0;
|
||||
}
|
||||
|
||||
void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
|
|
@ -720,26 +637,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
|||
|
||||
/* setup pipe */
|
||||
dcd_int_disable(rhport);
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPEMAXP.WORD = mps;
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPEMAXP = mps;
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
*ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
*ctr = 0;
|
||||
unsigned cfg = (dir << 4) | epn;
|
||||
if (xfer == TUSB_XFER_BULK) {
|
||||
cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB);
|
||||
cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk);
|
||||
} else if (xfer == TUSB_XFER_INTERRUPT) {
|
||||
cfg |= USB_PIPECFG_INT;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_INT;
|
||||
} else {
|
||||
cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
|
||||
cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk);
|
||||
}
|
||||
USB0.PIPECFG.WORD = cfg;
|
||||
USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num);
|
||||
USB0.BRDYENB.WORD |= TU_BIT(num);
|
||||
LINK_REG->PIPECFG = cfg;
|
||||
LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
|
||||
LINK_REG->BRDYENB |= TU_BIT(num);
|
||||
if (dir || (xfer != TUSB_XFER_BULK)) {
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
// TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
|
||||
// TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return true;
|
||||
|
|
@ -764,11 +681,11 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
|||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned num = _dcd.ep[dir][epn];
|
||||
|
||||
USB0.BRDYENB.WORD &= ~TU_BIT(num);
|
||||
LINK_REG->BRDYENB &= ~TU_BIT(num);
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
*ctr = 0;
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPECFG.WORD = 0;
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPECFG = 0;
|
||||
_dcd.pipe[num].ep = 0;
|
||||
_dcd.ep[dir][epn] = 0;
|
||||
}
|
||||
|
|
@ -799,8 +716,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
|
|||
if (!ctr) return;
|
||||
dcd_int_disable(rhport);
|
||||
const uint32_t pid = *ctr & 0x3;
|
||||
*ctr = pid | USB_PIPECTR_PID_STALL;
|
||||
*ctr = USB_PIPECTR_PID_STALL;
|
||||
*ctr = pid | LINK_REG_PIPE_CTR_PID_STALL;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_STALL;
|
||||
dcd_int_enable(rhport);
|
||||
}
|
||||
|
||||
|
|
@ -809,15 +726,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
|||
volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
|
||||
if (!ctr) return;
|
||||
dcd_int_disable(rhport);
|
||||
*ctr = USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
|
||||
if (tu_edpt_dir(ep_addr)) { /* IN */
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
} else {
|
||||
const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
|
||||
USB0.PIPESEL.WORD = num;
|
||||
if (USB0.PIPECFG.BIT.TYPE != 1) {
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
LINK_REG->PIPESEL = num;
|
||||
if (LINK_REG->PIPECFG_b.TYPE != 1) {
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
}
|
||||
dcd_int_enable(rhport);
|
||||
|
|
@ -830,70 +747,71 @@ void dcd_int_handler(uint8_t rhport)
|
|||
{
|
||||
(void)rhport;
|
||||
|
||||
unsigned is0 = USB0.INTSTS0.WORD;
|
||||
unsigned is0 = LINK_REG->INTSTS0;
|
||||
/* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
|
||||
if (is0 & USB_IS0_VBINT) {
|
||||
if (USB0.INTSTS0.BIT.VBSTS) {
|
||||
LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk |
|
||||
LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk;
|
||||
if (is0 & LINK_REG_INTSTS0_VBINT_Msk) {
|
||||
if (LINK_REG->INTSTS0_b.VBSTS) {
|
||||
dcd_connect(rhport);
|
||||
} else {
|
||||
dcd_disconnect(rhport);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_RESM) {
|
||||
if (is0 & LINK_REG_INTSTS0_RESM_Msk) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||
#if (0==USE_SOF)
|
||||
USB0.INTENB0.BIT.SOFE = 0;
|
||||
LINK_REG->INTENB0_b.SOFE = 0;
|
||||
#endif
|
||||
}
|
||||
if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) {
|
||||
if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) {
|
||||
// USBD will exit suspended mode when SOF event is received
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||
#if (0==USE_SOF)
|
||||
USB0.INTENB0.BIT.SOFE = 0;
|
||||
#if (0 == USE_SOF)
|
||||
LINK_REG->INTENB0_b.SOFE = 0;
|
||||
#endif
|
||||
}
|
||||
if (is0 & USB_IS0_DVST) {
|
||||
switch (is0 & USB_IS0_DVSQ) {
|
||||
case USB_IS0_DVSQ_DEF:
|
||||
if (is0 & LINK_REG_INTSTS0_DVST_Msk) {
|
||||
switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) {
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_DEF:
|
||||
process_bus_reset(rhport);
|
||||
break;
|
||||
case USB_IS0_DVSQ_ADDR:
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_ADDR:
|
||||
process_set_address(rhport);
|
||||
break;
|
||||
case USB_IS0_DVSQ_SUSP0:
|
||||
case USB_IS0_DVSQ_SUSP1:
|
||||
case USB_IS0_DVSQ_SUSP2:
|
||||
case USB_IS0_DVSQ_SUSP3:
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0:
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1:
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2:
|
||||
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3:
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||
#if (0==USE_SOF)
|
||||
USB0.INTENB0.BIT.SOFE = 1;
|
||||
LINK_REG->INTENB0_b.SOFE = 1;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_CTRT) {
|
||||
if (is0 & USB_IS0_CTSQ_SETUP) {
|
||||
if (is0 & LINK_REG_INTSTS0_CTRT_Msk) {
|
||||
if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) {
|
||||
/* A setup packet has been received. */
|
||||
process_setup_packet(rhport);
|
||||
} else if (0 == (is0 & USB_IS0_CTSQ_MSK)) {
|
||||
} else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) {
|
||||
/* A ZLP has been sent/received. */
|
||||
process_status_completion(rhport);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_BEMP) {
|
||||
const unsigned s = USB0.BEMPSTS.WORD;
|
||||
USB0.BEMPSTS.WORD = 0;
|
||||
if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
|
||||
const unsigned s = LINK_REG->BEMPSTS;
|
||||
LINK_REG->BEMPSTS = 0;
|
||||
if (s & 1) {
|
||||
process_pipe0_bemp(rhport);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_BRDY) {
|
||||
const unsigned m = USB0.BRDYENB.WORD;
|
||||
unsigned s = USB0.BRDYSTS.WORD & m;
|
||||
if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
|
||||
const unsigned m = LINK_REG->BRDYENB;
|
||||
unsigned s = LINK_REG->BRDYSTS & m;
|
||||
/* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.BRDYSTS.WORD = ~s;
|
||||
LINK_REG->BRDYSTS = ~s;
|
||||
while (s) {
|
||||
#if defined(__CCRX__)
|
||||
static const int Mod37BitPosition[] = {
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021 Koji Kitayama
|
||||
|
|
@ -27,86 +27,37 @@
|
|||
|
||||
#include "tusb_option.h"
|
||||
|
||||
#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX65X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX65X || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RX72N || \
|
||||
CFG_TUSB_MCU == OPT_MCU_RAXXX)
|
||||
|
||||
#include "host/hcd.h"
|
||||
#include "iodefine.h"
|
||||
#include "link_type.h"
|
||||
|
||||
#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
|
||||
#include "link_rx.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
|
||||
#include "link_ra.h"
|
||||
#else
|
||||
#error "Unsupported MCU"
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
|
||||
//--------------------------------------------------------------------+
|
||||
#define SYSTEM_PRCR_PRC1 (1<<1)
|
||||
#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
|
||||
|
||||
#define USB_DVSTCTR0_LOW (1u)
|
||||
#define USB_DVSTCTR0_FULL (2u)
|
||||
/* LINK core registers */
|
||||
#if defined(__CCRX__)
|
||||
#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
|
||||
#else
|
||||
#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
|
||||
#endif
|
||||
|
||||
#define USB_FIFOSEL_TX ((uint16_t)(1u<<5))
|
||||
#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8))
|
||||
#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10))
|
||||
#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10))
|
||||
#define USB_IS0_CTSQ ((uint16_t)(7u))
|
||||
#define USB_IS0_DVSQ ((uint16_t)(7u<<4))
|
||||
#define USB_IS0_VALID ((uint16_t)(1u<<3))
|
||||
#define USB_IS0_BRDY ((uint16_t)(1u<<8))
|
||||
#define USB_IS0_NRDY ((uint16_t)(1u<<9))
|
||||
#define USB_IS0_BEMP ((uint16_t)(1u<<10))
|
||||
#define USB_IS0_CTRT ((uint16_t)(1u<<11))
|
||||
#define USB_IS0_DVST ((uint16_t)(1u<<12))
|
||||
#define USB_IS0_SOFR ((uint16_t)(1u<<13))
|
||||
#define USB_IS0_RESM ((uint16_t)(1u<<14))
|
||||
#define USB_IS0_VBINT ((uint16_t)(1u<<15))
|
||||
#define USB_IS1_SACK ((uint16_t)(1u<<4))
|
||||
#define USB_IS1_SIGN ((uint16_t)(1u<<5))
|
||||
#define USB_IS1_EOFERR ((uint16_t)(1u<<6))
|
||||
#define USB_IS1_ATTCH ((uint16_t)(1u<<11))
|
||||
#define USB_IS1_DTCH ((uint16_t)(1u<<12))
|
||||
#define USB_IS1_BCHG ((uint16_t)(1u<<14))
|
||||
#define USB_IS1_OVRCR ((uint16_t)(1u<<15))
|
||||
|
||||
#define USB_IS0_CTSQ_MSK (7u)
|
||||
#define USB_IS0_CTSQ_SETUP (1u)
|
||||
#define USB_IS0_DVSQ_DEF (1u<<4)
|
||||
#define USB_IS0_DVSQ_ADDR (2u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP0 (4u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP1 (5u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP2 (6u<<4)
|
||||
#define USB_IS0_DVSQ_SUSP3 (7u<<4)
|
||||
|
||||
#define USB_PIPECTR_PID_MSK (3u)
|
||||
#define USB_PIPECTR_PID_NAK (0u)
|
||||
#define USB_PIPECTR_PID_BUF (1u)
|
||||
#define USB_PIPECTR_PID_STALL (2u)
|
||||
#define USB_PIPECTR_CCPL (1u<<2)
|
||||
#define USB_PIPECTR_SQMON (1u<<6)
|
||||
#define USB_PIPECTR_SQCLR (1u<<8)
|
||||
#define USB_PIPECTR_ACLRM (1u<<9)
|
||||
#define USB_PIPECTR_INBUFM (1u<<14)
|
||||
#define USB_PIPECTR_BSTS (1u<<15)
|
||||
|
||||
#define USB_FIFOCTR_DTLN (0x1FF)
|
||||
#define USB_FIFOCTR_FRDY (1u<<13)
|
||||
#define USB_FIFOCTR_BCLR (1u<<14)
|
||||
#define USB_FIFOCTR_BVAL (1u<<15)
|
||||
|
||||
#define USB_PIPECFG_SHTNAK (1u<<7)
|
||||
#define USB_PIPECFG_DBLB (1u<<9)
|
||||
#define USB_PIPECFG_BULK (1u<<14)
|
||||
#define USB_PIPECFG_ISO (3u<<14)
|
||||
#define USB_PIPECFG_INT (2u<<14)
|
||||
|
||||
#define USB_DEVADD_LOW (1u<<6)
|
||||
#define USB_DEVADD_FULL (2u<<6)
|
||||
|
||||
#define FIFO_REQ_CLR (1u)
|
||||
#define FIFO_COMPLETE (1u<<1)
|
||||
|
||||
// Start of definition of packed structs (used by the CCRX toolchain)
|
||||
TU_ATTR_PACKED_BEGIN
|
||||
TU_ATTR_BIT_FIELD_ORDER_BEGIN
|
||||
|
||||
typedef struct {
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
union {
|
||||
struct {
|
||||
uint16_t : 8;
|
||||
|
|
@ -119,7 +70,7 @@ typedef struct {
|
|||
uint16_t TRN;
|
||||
} reg_pipetre_t;
|
||||
|
||||
typedef union {
|
||||
typedef union TU_ATTR_PACKED {
|
||||
struct {
|
||||
volatile uint16_t u8: 8;
|
||||
volatile uint16_t : 0;
|
||||
|
|
@ -127,8 +78,7 @@ typedef union {
|
|||
volatile uint16_t u16;
|
||||
} hw_fifo_t;
|
||||
|
||||
typedef struct TU_ATTR_PACKED
|
||||
{
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
void *buf; /* the start address of a transfer data buffer */
|
||||
uint16_t length; /* the number of bytes in the buffer */
|
||||
uint16_t remaining; /* the number of bytes remaining in the buffer */
|
||||
|
|
@ -156,28 +106,6 @@ typedef struct
|
|||
//--------------------------------------------------------------------+
|
||||
static hcd_data_t _hcd;
|
||||
|
||||
static uint32_t disable_interrupt(void)
|
||||
{
|
||||
uint32_t pswi;
|
||||
#if defined(__CCRX__)
|
||||
pswi = get_psw() & 0x010000;
|
||||
clrpsw_i();
|
||||
#else
|
||||
pswi = __builtin_rx_mvfc(0) & 0x010000;
|
||||
__builtin_rx_clrpsw('I');
|
||||
#endif
|
||||
return pswi;
|
||||
}
|
||||
|
||||
static void enable_interrupt(uint32_t pswi)
|
||||
{
|
||||
#if defined(__CCRX__)
|
||||
set_psw(get_psw() | pswi);
|
||||
#else
|
||||
__builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
|
||||
#endif
|
||||
}
|
||||
|
||||
static unsigned find_pipe(unsigned xfer)
|
||||
{
|
||||
switch (xfer) {
|
||||
|
|
@ -208,58 +136,49 @@ static unsigned find_pipe(unsigned xfer)
|
|||
|
||||
static volatile uint16_t* get_pipectr(unsigned num)
|
||||
{
|
||||
volatile uint16_t *ctr = NULL;
|
||||
if (num) {
|
||||
ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
|
||||
ctr += num - 1;
|
||||
return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
|
||||
} else {
|
||||
ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
|
||||
return (volatile uint16_t*)&(LINK_REG->DCPCTR);
|
||||
}
|
||||
return ctr;
|
||||
}
|
||||
|
||||
static volatile reg_pipetre_t* get_pipetre(unsigned num)
|
||||
{
|
||||
volatile reg_pipetre_t* tre = NULL;
|
||||
if ((1 <= num) && (num <= 5)) {
|
||||
tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
|
||||
tre += num - 1;
|
||||
tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
|
||||
}
|
||||
return tre;
|
||||
}
|
||||
|
||||
static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
|
||||
{
|
||||
volatile uint16_t *ctr = NULL;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
if (epn) {
|
||||
const unsigned dir_in = tu_edpt_dir(ep_addr);
|
||||
const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
|
||||
if (num) {
|
||||
ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
|
||||
ctr += num - 1;
|
||||
}
|
||||
const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
|
||||
return get_pipectr(num);
|
||||
} else {
|
||||
ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
|
||||
return get_pipectr(0);
|
||||
}
|
||||
return ctr;
|
||||
}
|
||||
|
||||
static unsigned edpt0_max_packet_size(void)
|
||||
{
|
||||
return USB0.DCPMAXP.BIT.MXPS;
|
||||
return LINK_REG->DCPMAXP_b.MXPS;
|
||||
}
|
||||
|
||||
static unsigned edpt_max_packet_size(unsigned num)
|
||||
{
|
||||
USB0.PIPESEL.WORD = num;
|
||||
return USB0.PIPEMAXP.BIT.MXPS;
|
||||
LINK_REG->PIPESEL = num;
|
||||
return LINK_REG->PIPEMAXP_b.MXPS;
|
||||
}
|
||||
|
||||
static inline void pipe_wait_for_ready(unsigned num)
|
||||
{
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
|
||||
while (!USB0.D0FIFOCTR.BIT.FRDY) ;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
|
||||
while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
|
||||
}
|
||||
|
||||
static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
|
||||
|
|
@ -290,21 +209,22 @@ static bool pipe0_xfer_in(void)
|
|||
const unsigned rem = pipe->remaining;
|
||||
|
||||
const unsigned mps = edpt0_max_packet_size();
|
||||
const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
|
||||
const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
|
||||
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
if (len < mps)
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
pipe->remaining = rem - len;
|
||||
if ((len < mps) || (rem == len)) {
|
||||
pipe->buf = NULL;
|
||||
return true;
|
||||
}
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -320,10 +240,11 @@ static bool pipe0_xfer_out(void)
|
|||
const unsigned len = TU_MIN(mps, rem);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
|
||||
pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
if (len < mps)
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
pipe->remaining = rem - len;
|
||||
return false;
|
||||
}
|
||||
|
|
@ -333,20 +254,21 @@ static bool pipe_xfer_in(unsigned num)
|
|||
pipe_state_t *pipe = &_hcd.pipe[num];
|
||||
const unsigned rem = pipe->remaining;
|
||||
|
||||
USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
|
||||
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
pipe_wait_for_ready(num);
|
||||
const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN;
|
||||
const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN;
|
||||
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
|
||||
pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
if (len < mps)
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
if ((len < mps) || (rem == len)) {
|
||||
pipe->buf = NULL;
|
||||
return NULL != buf;
|
||||
|
|
@ -364,18 +286,19 @@ static bool pipe_xfer_out(unsigned num)
|
|||
return true;
|
||||
}
|
||||
|
||||
USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
|
||||
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
pipe_wait_for_ready(num);
|
||||
const unsigned len = TU_MIN(rem, mps);
|
||||
void *buf = pipe->buf;
|
||||
if (len) {
|
||||
pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
|
||||
pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
|
||||
pipe->buf = (uint8_t*)buf + len;
|
||||
}
|
||||
if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
if (len < mps)
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
pipe->remaining = rem - len;
|
||||
return false;
|
||||
}
|
||||
|
|
@ -387,11 +310,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
|
|||
|
||||
/* configure fifo direction and access unit settings */
|
||||
if (dir_in) { /* IN, a byte */
|
||||
USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
|
||||
while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
|
||||
} else { /* OUT, 2 bytes */
|
||||
USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
|
||||
while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
|
||||
LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
|
||||
while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
|
||||
} else { /* OUT, 2 bytes */
|
||||
LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
|
||||
(TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
|
||||
while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
|
||||
}
|
||||
|
||||
pipe_state_t *pipe = &_hcd.pipe[0];
|
||||
|
|
@ -401,25 +325,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
|
|||
if (buflen) {
|
||||
pipe->buf = buffer;
|
||||
if (!dir_in) { /* OUT */
|
||||
TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
|
||||
TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
|
||||
pipe0_xfer_out();
|
||||
}
|
||||
} else { /* ZLP */
|
||||
pipe->buf = NULL;
|
||||
if (!dir_in) { /* OUT */
|
||||
USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
}
|
||||
if (dir_in == USB0.DCPCFG.BIT.DIR) {
|
||||
TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
|
||||
USB0.DCPCTR.BIT.SQSET = 1;
|
||||
USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
|
||||
if (dir_in == LINK_REG->DCPCFG_b.DIR) {
|
||||
TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
|
||||
LINK_REG->DCPCTR_b.SQSET = 1;
|
||||
LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
|
||||
}
|
||||
}
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
|
||||
static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir_in = tu_edpt_dir(ep_addr);
|
||||
|
|
@ -435,23 +359,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u
|
|||
if (buflen) {
|
||||
pipe_xfer_out(num);
|
||||
} else { /* ZLP */
|
||||
USB0.D0FIFOSEL.WORD = num;
|
||||
LINK_REG->D0FIFOSEL = num;
|
||||
pipe_wait_for_ready(num);
|
||||
USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
|
||||
}
|
||||
} else {
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
volatile reg_pipetre_t *pt = get_pipetre(num);
|
||||
if (pt) {
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
|
||||
if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
pt->TRE = TU_BIT(8);
|
||||
pt->TRN = (buflen + mps - 1) / mps;
|
||||
pt->TRENB = 1;
|
||||
}
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -485,10 +409,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
|
|||
unsigned result;
|
||||
uint16_t volatile *ctr = get_pipectr(num);
|
||||
// TU_LOG1("NRDY %d %x\n", num, *ctr);
|
||||
switch (*ctr & USB_PIPECTR_PID_MSK) {
|
||||
switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
|
||||
default: return;
|
||||
case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
|
||||
case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break;
|
||||
case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
|
||||
case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break;
|
||||
}
|
||||
pipe_state_t *pipe = &_hcd.pipe[num];
|
||||
hcd_event_xfer_complete(pipe->dev, pipe->ep,
|
||||
|
|
@ -520,78 +444,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* Host API
|
||||
*------------------------------------------------------------------*/
|
||||
bool hcd_init(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* Enable USB0 */
|
||||
uint32_t pswi = disable_interrupt();
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(USB0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
enable_interrupt(pswi);
|
||||
USB0.SYSCFG.BIT.SCKE = 1;
|
||||
while (!USB0.SYSCFG.BIT.SCKE) ;
|
||||
USB0.SYSCFG.BIT.DPRPU = 0;
|
||||
USB0.SYSCFG.BIT.DRPD = 0;
|
||||
USB0.SYSCFG.BIT.DCFM = 1;
|
||||
|
||||
USB0.DVSTCTR0.BIT.VBUSEN = 1;
|
||||
LINK_REG->SYSCFG_b.SCKE = 1;
|
||||
while (!LINK_REG->SYSCFG_b.SCKE) ;
|
||||
LINK_REG->SYSCFG_b.DPRPU = 0;
|
||||
LINK_REG->SYSCFG_b.DRPD = 0;
|
||||
LINK_REG->SYSCFG_b.DCFM = 1;
|
||||
|
||||
USB0.SYSCFG.BIT.DRPD = 1;
|
||||
LINK_REG->DVSTCTR0_b.VBUSEN = 1;
|
||||
|
||||
LINK_REG->SYSCFG_b.DRPD = 1;
|
||||
for (volatile int i = 0; i < 30000; ++i) ;
|
||||
USB0.SYSCFG.BIT.USBE = 1;
|
||||
LINK_REG->SYSCFG_b.USBE = 1;
|
||||
|
||||
USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
USB0.PHYSLEW.LONG = 0x5;
|
||||
IR(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IR(USB0, USBI0) = 0;
|
||||
#endif
|
||||
// MCU specific PHY init
|
||||
link_phy_init();
|
||||
|
||||
LINK_REG->PHYSLEW = 0x5;
|
||||
LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
|
||||
|
||||
/* Setup default control pipe */
|
||||
USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK;
|
||||
USB0.DCPMAXP.WORD = 64;
|
||||
USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
|
||||
USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
|
||||
USB_IS1_ATTCH | USB_IS1_DTCH;
|
||||
USB0.BEMPENB.WORD = 1;
|
||||
USB0.NRDYENB.WORD = 1;
|
||||
USB0.BRDYENB.WORD = 1;
|
||||
LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
|
||||
LINK_REG->DCPMAXP = 64;
|
||||
LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
|
||||
LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
|
||||
LINK_REG->BEMPENB = 1;
|
||||
LINK_REG->NRDYENB = 1;
|
||||
LINK_REG->BRDYENB = 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void hcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 1;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 1;
|
||||
#endif
|
||||
link_int_enable(rhport);
|
||||
}
|
||||
|
||||
void hcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 0;
|
||||
#endif
|
||||
link_int_disable(rhport);
|
||||
}
|
||||
|
||||
uint32_t hcd_frame_number(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* The device must be reset at least once after connection
|
||||
/* The device must be reset at least once after connection
|
||||
* in order to start the frame counter. */
|
||||
if (_hcd.need_reset) hcd_port_reset(rhport);
|
||||
return USB0.FRMNUM.BIT.FRNM;
|
||||
return LINK_REG->FRMNUM_b.FRNM;
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
|
|
@ -600,23 +506,23 @@ uint32_t hcd_frame_number(uint8_t rhport)
|
|||
bool hcd_port_connect_status(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
return USB0.INTSTS1.BIT.ATTCH ? true: false;
|
||||
return LINK_REG->INTSTS1_b.ATTCH ? true : false;
|
||||
}
|
||||
|
||||
void hcd_port_reset(uint8_t rhport)
|
||||
{
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
hcd_int_disable(rhport);
|
||||
USB0.DVSTCTR0.BIT.UACT = 0;
|
||||
if (USB0.DCPCTR.BIT.SUREQ)
|
||||
USB0.DCPCTR.BIT.SUREQCLR = 1;
|
||||
LINK_REG->DVSTCTR0_b.UACT = 0;
|
||||
if (LINK_REG->DCPCTR_b.SUREQ)
|
||||
LINK_REG->DCPCTR_b.SUREQCLR = 1;
|
||||
hcd_int_enable(rhport);
|
||||
/* Reset should be asserted 10-20ms. */
|
||||
USB0.DVSTCTR0.BIT.USBRST = 1;
|
||||
LINK_REG->DVSTCTR0_b.USBRST = 1;
|
||||
for (volatile int i = 0; i < 2400000; ++i) ;
|
||||
USB0.DVSTCTR0.BIT.USBRST = 0;
|
||||
USB0.DVSTCTR0.BIT.UACT = 1;
|
||||
LINK_REG->DVSTCTR0_b.USBRST = 0;
|
||||
LINK_REG->DVSTCTR0_b.UACT = 1;
|
||||
_hcd.need_reset = false;
|
||||
}
|
||||
|
||||
|
|
@ -628,10 +534,10 @@ void hcd_port_reset_end(uint8_t rhport)
|
|||
tusb_speed_t hcd_port_speed_get(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
switch (USB0.DVSTCTR0.BIT.RHST) {
|
||||
switch (LINK_REG->DVSTCTR0_b.RHST) {
|
||||
default: return TUSB_SPEED_INVALID;
|
||||
case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
|
||||
case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW;
|
||||
case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
|
||||
case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -647,13 +553,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
|||
unsigned num = *ep;
|
||||
if (!num || dev_addr != _hcd.pipe[num].dev) continue;
|
||||
|
||||
ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
|
||||
ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1];
|
||||
*ctr = 0;
|
||||
USB0.NRDYENB.WORD &= ~TU_BIT(num);
|
||||
USB0.BRDYENB.WORD &= ~TU_BIT(num);
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPECFG.WORD = 0;
|
||||
USB0.PIPEMAXP.WORD = 0;
|
||||
LINK_REG->NRDYENB &= ~TU_BIT(num);
|
||||
LINK_REG->BRDYENB &= ~TU_BIT(num);
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPECFG = 0;
|
||||
LINK_REG->PIPEMAXP = 0;
|
||||
|
||||
_hcd.pipe[num].ep = 0;
|
||||
_hcd.pipe[num].dev = 0;
|
||||
|
|
@ -667,36 +573,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
|||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
|
||||
{
|
||||
(void)rhport;
|
||||
// TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
|
||||
// TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR);
|
||||
|
||||
TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
|
||||
TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
|
||||
TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
|
||||
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
|
||||
_hcd.pipe[0].buf = NULL;
|
||||
_hcd.pipe[0].length = 8;
|
||||
_hcd.pipe[0].buf = NULL;
|
||||
_hcd.pipe[0].length = 8;
|
||||
_hcd.pipe[0].remaining = 0;
|
||||
_hcd.pipe[0].dev = dev_addr;
|
||||
_hcd.pipe[0].dev = dev_addr;
|
||||
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
|
||||
|
||||
/* Set direction in advance for DATA stage */
|
||||
uint8_t const bmRequesttype = setup_packet[0];
|
||||
USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
|
||||
LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
|
||||
|
||||
uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
|
||||
USB0.USBREQ.WORD = tu_htole16(p[0]);
|
||||
USB0.USBVAL = p[1];
|
||||
USB0.USBINDX = p[2];
|
||||
USB0.USBLENG = p[3];
|
||||
LINK_REG->USBREQ = tu_htole16(p[0]);
|
||||
LINK_REG->USBVAL = p[1];
|
||||
LINK_REG->USBINDX = p[2];
|
||||
LINK_REG->USBLENG = p[3];
|
||||
|
||||
USB0.DCPCTR.BIT.SUREQ = 1;
|
||||
LINK_REG->DCPCTR_b.SUREQ = 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
|
||||
{
|
||||
(void)rhport;
|
||||
TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
|
||||
|
|
@ -705,14 +611,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
|
|||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned mps = tu_edpt_packet_size(ep_desc);
|
||||
if (0 == epn) {
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
hcd_devtree_info_t devtree;
|
||||
hcd_devtree_get_info(dev_addr, &devtree);
|
||||
uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
|
||||
uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
|
||||
devadd += dev_addr;
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
|
||||
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
|
||||
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
|
||||
_hcd.ctl_mps[dev_addr] = mps;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -731,25 +637,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
|
|||
|
||||
/* setup pipe */
|
||||
hcd_int_disable(rhport);
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
*ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
*ctr = 0;
|
||||
unsigned cfg = ((1 ^ dir_in) << 4) | epn;
|
||||
if (xfer == TUSB_XFER_BULK) {
|
||||
cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
|
||||
} else if (xfer == TUSB_XFER_INTERRUPT) {
|
||||
cfg |= USB_PIPECFG_INT;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_INT;
|
||||
} else {
|
||||
cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk;
|
||||
}
|
||||
USB0.PIPECFG.WORD = cfg;
|
||||
USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num);
|
||||
USB0.NRDYENB.WORD |= TU_BIT(num);
|
||||
USB0.BRDYENB.WORD |= TU_BIT(num);
|
||||
LINK_REG->PIPECFG = cfg;
|
||||
LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
|
||||
LINK_REG->NRDYENB |= TU_BIT(num);
|
||||
LINK_REG->BRDYENB |= TU_BIT(num);
|
||||
if (!dir_in) {
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
hcd_int_enable(rhport);
|
||||
|
||||
|
|
@ -776,12 +682,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
|
|||
*ctr = pid & 2;
|
||||
*ctr = 0;
|
||||
}
|
||||
*ctr = USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
if (!epn) return true;
|
||||
|
||||
if (!tu_edpt_dir(ep_addr)) { /* OUT */
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -799,52 +705,50 @@ void hcd_int_handler(uint8_t rhport)
|
|||
20, 8, 19, 18};
|
||||
#endif
|
||||
|
||||
unsigned is1 = USB0.INTSTS1.WORD;
|
||||
unsigned is0 = USB0.INTSTS0.WORD;
|
||||
unsigned is1 = LINK_REG->INTSTS1;
|
||||
unsigned is0 = LINK_REG->INTSTS0;
|
||||
/* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
|
||||
USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
|
||||
LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
|
||||
LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
|
||||
// TU_LOG1("IS %04x %04x\n", is0, is1);
|
||||
is1 &= USB0.INTENB1.WORD;
|
||||
is0 &= USB0.INTENB0.WORD;
|
||||
is1 &= LINK_REG->INTENB1;
|
||||
is0 &= LINK_REG->INTENB0;
|
||||
|
||||
if (is1 & USB_IS1_SACK) {
|
||||
if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
|
||||
/* Set DATA1 in advance for the next transfer. */
|
||||
USB0.DCPCTR.BIT.SQSET = 1;
|
||||
hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
8, XFER_RESULT_SUCCESS, true);
|
||||
LINK_REG->DCPCTR_b.SQSET = 1;
|
||||
hcd_event_xfer_complete(
|
||||
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
if (is1 & USB_IS1_SIGN) {
|
||||
hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
8, XFER_RESULT_FAILED, true);
|
||||
if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
|
||||
hcd_event_xfer_complete(
|
||||
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
|
||||
}
|
||||
if (is1 & USB_IS1_ATTCH) {
|
||||
USB0.DVSTCTR0.BIT.UACT = 1;
|
||||
if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
|
||||
LINK_REG->DVSTCTR0_b.UACT = 1;
|
||||
_hcd.need_reset = true;
|
||||
USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
|
||||
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
|
||||
hcd_event_device_attach(rhport, true);
|
||||
}
|
||||
if (is1 & USB_IS1_DTCH) {
|
||||
USB0.DVSTCTR0.BIT.UACT = 0;
|
||||
if (USB0.DCPCTR.BIT.SUREQ)
|
||||
USB0.DCPCTR.BIT.SUREQCLR = 1;
|
||||
USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
|
||||
if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
|
||||
LINK_REG->DVSTCTR0_b.UACT = 0;
|
||||
if (LINK_REG->DCPCTR_b.SUREQ)
|
||||
LINK_REG->DCPCTR_b.SUREQCLR = 1;
|
||||
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
|
||||
hcd_event_device_remove(rhport, true);
|
||||
}
|
||||
|
||||
if (is0 & USB_IS0_BEMP) {
|
||||
const unsigned s = USB0.BEMPSTS.WORD;
|
||||
USB0.BEMPSTS.WORD = 0;
|
||||
if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
|
||||
const unsigned s = LINK_REG->BEMPSTS;
|
||||
LINK_REG->BEMPSTS = 0;
|
||||
if (s & 1) {
|
||||
process_pipe0_bemp(rhport);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_NRDY) {
|
||||
const unsigned m = USB0.NRDYENB.WORD;
|
||||
unsigned s = USB0.NRDYSTS.WORD & m;
|
||||
USB0.NRDYSTS.WORD = ~s;
|
||||
if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
|
||||
const unsigned m = LINK_REG->NRDYENB;
|
||||
unsigned s = LINK_REG->NRDYSTS & m;
|
||||
LINK_REG->NRDYSTS = ~s;
|
||||
while (s) {
|
||||
#if defined(__CCRX__)
|
||||
const unsigned num = Mod37BitPosition[(-s & s) % 37];
|
||||
|
|
@ -855,11 +759,11 @@ void hcd_int_handler(uint8_t rhport)
|
|||
s &= ~TU_BIT(num);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_BRDY) {
|
||||
const unsigned m = USB0.BRDYENB.WORD;
|
||||
unsigned s = USB0.BRDYSTS.WORD & m;
|
||||
if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
|
||||
const unsigned m = LINK_REG->BRDYENB;
|
||||
unsigned s = LINK_REG->BRDYSTS & m;
|
||||
/* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.BRDYSTS.WORD = ~s;
|
||||
LINK_REG->BRDYSTS = ~s;
|
||||
while (s) {
|
||||
#if defined(__CCRX__)
|
||||
const unsigned num = Mod37BitPosition[(-s & s) % 37];
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022 Rafael Silva (@perigoso)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _LINK_RA_H_
|
||||
#define _LINK_RA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "link_type.h"
|
||||
|
||||
/* renesas fsp api */
|
||||
#include "bsp_api.h"
|
||||
|
||||
#define LINK_REG_BASE (0x40090000)
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void link_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_EnableIRQ(TU_IRQn);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void link_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_DisableIRQ(TU_IRQn);
|
||||
}
|
||||
|
||||
// MCU specific PHY init
|
||||
static inline void link_phy_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LINK_RA_H_ */
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2020 Koji Kitayama
|
||||
* Portions copyrighted (c) 2021 Roland Winistoerfer
|
||||
* Copyright (c) 2022 Rafael Silva (@perigoso)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _LINK_RX_H_
|
||||
#define _LINK_RX_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "link_type.h"
|
||||
|
||||
#include "iodefine.h"
|
||||
|
||||
#define LINK_REG_BASE (0x000A0000)
|
||||
|
||||
static inline void link_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
|
||||
IEN(PERIB, INTB185) = 1;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void link_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
|
||||
IEN(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
// MCU specific PHY init
|
||||
static inline void link_phy_init(void)
|
||||
{
|
||||
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
|
||||
IR(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IR(USB0, USBI0) = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LINK_RX_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -129,6 +129,8 @@ typedef int make_iso_compilers_happy;
|
|||
#define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631
|
||||
#define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651
|
||||
#define OPT_MCU_RX72N 1402 ///< Renesas RX72N
|
||||
#define OPT_MCU_RAXXX 1403 ///< Renesas RAxxx families
|
||||
|
||||
|
||||
// Mind Motion
|
||||
#define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327
|
||||
|
|
|
|||
Loading…
Reference in New Issue