kingkevin
/
esp32-s2_dfu
1
0
Fork 0
Code Issues Releases Activity

style code for consistency with existing codebase

This commit is contained in:
Rafael Silva 2022-03-21 16:02:11 +00:00
parent e0220c6594
commit 60aae59eeb
7 changed files with 1074 additions and 1070 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

152
hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
View File

@ -50,35 +50,35 @@ void usbfs_d0fifo_handler(void);
void usbfs_d1fifo_handler(void);
BSP_DONT_REMOVE const
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
};
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = BSP_IO_PORT_05_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = BSP_IO_PORT_05_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
{.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = BSP_IO_PORT_05_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = BSP_IO_PORT_05_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
};
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
@ -88,78 +88,78 @@ const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_i
//--------------------------------------------------------------------+
void usbfs_interrupt_handler(void)
{
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
tuh_int_handler(0);
tuh_int_handler(0);
#endif
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
tud_int_handler(0);
tud_int_handler(0);
#endif
}
void usbfs_resume_handler(void)
{
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
tuh_int_handler(0);
tuh_int_handler(0);
#endif
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
tud_int_handler(0);
tud_int_handler(0);
#endif
}
void usbfs_d0fifo_handler(void)
{
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
tuh_int_handler(0);
tuh_int_handler(0);
#endif
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
tud_int_handler(0);
tud_int_handler(0);
#endif
}
void usbfs_d1fifo_handler(void)
{
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
tuh_int_handler(0);
tuh_int_handler(0);
#endif
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
tud_int_handler(0);
tud_int_handler(0);
#endif
}
void board_init(void)
{
/* Configure pins. */
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
/* Configure pins. */
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
/* Enable USB_BASE */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
R_MSTP->MSTPCRB &= ~(1U << 11U);
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
/* Enable USB_BASE */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
R_MSTP->MSTPCRB &= ~(1U << 11U);
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
#if CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
#if CFG_TUSB_OS == OPT_OS_NONE
/* Init systick */
SysTick_Config(SystemCoreClock / 1000);
/* Init systick */
SysTick_Config(SystemCoreClock / 1000);
#endif
}
@ -169,66 +169,66 @@ void board_init(void)
void board_led_write(bool state)
{
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
}
uint32_t board_button_read(void)
{
bsp_io_level_t lvl;
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
return lvl;
bsp_io_level_t lvl;
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
return lvl;
}
int board_uart_read(uint8_t *buf, int len)
{
(void) buf;
(void) len;
return 0;
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const *buf, int len)
{
(void) buf;
(void) len;
return 0;
(void) buf;
(void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler(void)
{
system_ticks++;
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
return system_ticks;
}
#else
#endif
int close(int fd)
{
(void) fd;
return -1;
(void) fd;
return -1;
}
int fstat(int fd, void *pstat)
{
(void) fd;
(void) pstat;
return 0;
(void) fd;
(void) pstat;
return 0;
}
off_t lseek(int fd, off_t pos, int whence)
{
(void) fd;
(void) pos;
(void) whence;
return 0;
(void) fd;
(void) pos;
(void) whence;
return 0;
}
int isatty(int fd)
{
(void) fd;
return 1;
(void) fd;
return 1;
}

112
hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
View File

@ -69,40 +69,40 @@
/* Peripheral Security Attribution Register (PSAR) Settings */
#define BSP_TZ_CFG_PSARB \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
#define BSP_TZ_CFG_PSARC \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
#define BSP_TZ_CFG_PSARD \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
0xffae07f0) /* Unused */
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
0xffae07f0) /* Unused */
#define BSP_TZ_CFG_PSARE \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
(((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
(((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
(((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
(((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
#define BSP_TZ_CFG_MSSAR \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
0xfffffffc) /* Unused */
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
0xfffffffc) /* Unused */
/* Type 2 Peripheral Security Attribution */
@ -114,9 +114,9 @@
/* Security attribution for registers of LVD channels. */
#define BSP_TZ_CFG_LVDSAR \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
0xFFFFFFFCU)
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
0xFFFFFFFCU)
/* Security attribution for LPM registers. */
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
@ -137,34 +137,34 @@
/* Security attribution for registers for IRQ channels. */
#define BSP_TZ_CFG_ICUSARA \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
(((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
(((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
/* Security attribution for NMI registers. */
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
/* Security attribution for registers for DMAC channels */
#define BSP_TZ_CFG_ICUSARC \
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
/* Security attribution registers for SELSR0. */
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
@ -222,7 +222,7 @@
/* Option Function Select Register 1 Security Attribution */
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
#define BSP_CFG_ROM_REG_OFS1_SEL \
(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
#else
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
#endif

8
src/portable/renesas/link/dcd_link.c
View File

@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Koji Kitayama
@ -31,8 +31,10 @@
// We disable SOF for now until needed later on
#define USE_SOF 0
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
CFG_TUSB_MCU == OPT_MCU_RAXXX)
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
CFG_TUSB_MCU == OPT_MCU_RX65X || \
CFG_TUSB_MCU == OPT_MCU_RX72N || \
CFG_TUSB_MCU == OPT_MCU_RAXXX)
#include "device/dcd.h"
#include "link_type.h"

10
src/portable/renesas/link/hcd_link.c
View File

@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Koji Kitayama
@ -27,8 +27,10 @@
#include "tusb_option.h"
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
CFG_TUSB_MCU == OPT_MCU_RAXXX)
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
CFG_TUSB_MCU == OPT_MCU_RX65X || \
CFG_TUSB_MCU == OPT_MCU_RX72N || \
CFG_TUSB_MCU == OPT_MCU_RAXXX)
#include "host/hcd.h"
#include "link_type.h"
@ -488,7 +490,7 @@ void hcd_int_disable(uint8_t rhport)
uint32_t hcd_frame_number(uint8_t rhport)
{
(void)rhport;
/* The device must be reset at least once after connection
/* The device must be reset at least once after connection
* in order to start the frame counter. */
if (_hcd.need_reset) hcd_port_reset(rhport);
return LINK_REG->FRMNUM_b.FRNM;

8
src/portable/renesas/link/link_ra.h
View File

@ -41,15 +41,15 @@ extern "C" {
TU_ATTR_ALWAYS_INLINE
static inline void link_int_enable(uint8_t rhport)
{
(void) rhport;
NVIC_EnableIRQ(TU_IRQn);
(void) rhport;
NVIC_EnableIRQ(TU_IRQn);
}
TU_ATTR_ALWAYS_INLINE
static inline void link_int_disable(uint8_t rhport)
{
(void) rhport;
NVIC_DisableIRQ(TU_IRQn);
(void) rhport;
NVIC_DisableIRQ(TU_IRQn);
}
// MCU specific PHY init

16
src/portable/renesas/link/link_rx.h
View File

@ -41,21 +41,21 @@ extern "C" {
static inline void link_int_enable(uint8_t rhport)
{
(void) rhport;
(void) rhport;
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
IEN(PERIB, INTB185) = 1;
IEN(PERIB, INTB185) = 1;
#else
IEN(USB0, USBI0) = 1;
IEN(USB0, USBI0) = 1;
#endif
}
static inline void link_int_disable(uint8_t rhport)
{
(void) rhport;
(void) rhport;
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
IEN(PERIB, INTB185) = 0;
IEN(PERIB, INTB185) = 0;
#else
IEN(USB0, USBI0) = 0;
IEN(USB0, USBI0) = 0;
#endif
}
@ -63,9 +63,9 @@ static inline void link_int_disable(uint8_t rhport)
static inline void link_phy_init(void)
{
#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
IR(PERIB, INTB185) = 0;
IR(PERIB, INTB185) = 0;
#else
IR(USB0, USBI0) = 0;
IR(USB0, USBI0) = 0;
#endif
}

1838
src/portable/renesas/link/link_type.h
View File

File diff suppressed because it is too large Load Diff