diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
index c2f2a0903..eab102de9 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
+++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
@@ -50,35 +50,35 @@ void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
 BSP_DONT_REMOVE const
-	fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
-		[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
-		[1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
-		[2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
-		[3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+  fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+    [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+    [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-	[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-	[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-	[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-	[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+  [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
+  [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+  [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+  [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 
 const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
-	{.pin = BSP_IO_PORT_04_PIN_07,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = BSP_IO_PORT_05_PIN_00,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = BSP_IO_PORT_05_PIN_01,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
-	{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
+  {.pin = BSP_IO_PORT_04_PIN_07,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_00,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_01,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+  {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
 
 const ioport_cfg_t g_bsp_pin_cfg = {
-	.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
-	.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+  .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
+  .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
 };
 ioport_instance_ctrl_t g_ioport_ctrl;
 const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
@@ -88,78 +88,78 @@ const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_i
 //--------------------------------------------------------------------+
 void usbfs_interrupt_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_resume_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_d0fifo_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_d1fifo_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 
 void board_init(void)
 {
-	/* Configure pins. */
-	R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+  /* Configure pins. */
+  R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
 
-	/* Enable USB_BASE */
-	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
-	R_MSTP->MSTPCRB &= ~(1U << 11U);
-	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+  /* Enable USB_BASE */
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+  R_MSTP->MSTPCRB &= ~(1U << 11U);
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-	/* Init systick */
-	SysTick_Config(SystemCoreClock / 1000);
+  /* Init systick */
+  SysTick_Config(SystemCoreClock / 1000);
 #endif
 }
 
@@ -169,66 +169,66 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
 }
 
 uint32_t board_button_read(void)
 {
-	bsp_io_level_t lvl;
-	R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
-	return lvl;
+  bsp_io_level_t lvl;
+  R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
+  return lvl;
 }
 
 int board_uart_read(uint8_t *buf, int len)
 {
-	(void) buf;
-	(void) len;
-	return 0;
+  (void) buf;
+  (void) len;
+  return 0;
 }
 
 int board_uart_write(void const *buf, int len)
 {
-	(void) buf;
-	(void) len;
-	return 0;
+  (void) buf;
+  (void) len;
+  return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void)
 {
-	system_ticks++;
+  system_ticks++;
 }
 
 uint32_t board_millis(void)
 {
-	return system_ticks;
+  return system_ticks;
 }
 #else
 #endif
 
 int close(int fd)
 {
-	(void) fd;
-	return -1;
+  (void) fd;
+  return -1;
 }
 int fstat(int fd, void *pstat)
 {
-	(void) fd;
-	(void) pstat;
-	return 0;
+  (void) fd;
+  (void) pstat;
+  return 0;
 }
 off_t lseek(int fd, off_t pos, int whence)
 {
-	(void) fd;
-	(void) pos;
-	(void) whence;
-	return 0;
+  (void) fd;
+  (void) pos;
+  (void) whence;
+  return 0;
 }
 int isatty(int fd)
 {
-	(void) fd;
-	return 1;
+  (void) fd;
+  return 1;
 }
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
index 0449bb4bc..4ecda1c66 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
@@ -69,40 +69,40 @@
 
 /* Peripheral Security Attribution Register (PSAR) Settings */
 #define BSP_TZ_CFG_PSARB                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
-	 (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
+   (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
 #define BSP_TZ_CFG_PSARC                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
 #define BSP_TZ_CFG_PSARD                                                                                               \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
-	 0xffae07f0) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
+   0xffae07f0) /* Unused */
 #define BSP_TZ_CFG_PSARE                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
-	 (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
-	 (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+   (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
+   (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
 #define BSP_TZ_CFG_MSSAR                                                                                              \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
-	 0xfffffffc) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+   0xfffffffc) /* Unused */
 
 /* Type 2 Peripheral Security Attribution */
 
@@ -114,9 +114,9 @@
 
 /* Security attribution for registers of LVD channels. */
 #define BSP_TZ_CFG_LVDSAR                                              \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
-	 0xFFFFFFFCU)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+   0xFFFFFFFCU)
 
 /* Security attribution for LPM registers. */
 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
@@ -137,34 +137,34 @@
 
 /* Security attribution for registers for IRQ channels. */
 #define BSP_TZ_CFG_ICUSARA                                                                                                    \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
-	 (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
+   (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
 
 /* Security attribution for NMI registers. */
 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
 
 /* Security attribution for registers for DMAC channels */
 #define BSP_TZ_CFG_ICUSARC                                               \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
 
 /* Security attribution registers for SELSR0. */
 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
@@ -222,7 +222,7 @@
 /* Option Function Select Register 1 Security Attribution */
 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
 #define BSP_CFG_ROM_REG_OFS1_SEL \
-	(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+  (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
 #else
 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
 #endif
diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index f2334140a..bb7e3b60a 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -31,8 +31,10 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
-      CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
+                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "device/dcd.h"
 #include "link_type.h"
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 940013c86..f60c49114 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji Kitayama
@@ -27,8 +27,10 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
-			CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
+                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "host/hcd.h"
 #include "link_type.h"
@@ -488,7 +490,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   return LINK_REG->FRMNUM_b.FRNM;
diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h
index b42def368..97618ef8f 100644
--- a/src/portable/renesas/link/link_ra.h
+++ b/src/portable/renesas/link/link_ra.h
@@ -41,15 +41,15 @@ extern "C" {
 TU_ATTR_ALWAYS_INLINE
 static inline void link_int_enable(uint8_t rhport)
 {
-	(void) rhport;
-	NVIC_EnableIRQ(TU_IRQn);
+  (void) rhport;
+  NVIC_EnableIRQ(TU_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void link_int_disable(uint8_t rhport)
 {
-	(void) rhport;
-	NVIC_DisableIRQ(TU_IRQn);
+  (void) rhport;
+  NVIC_DisableIRQ(TU_IRQn);
 }
 
 // MCU specific PHY init
diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h
index b15084bb3..62f2911c2 100644
--- a/src/portable/renesas/link/link_rx.h
+++ b/src/portable/renesas/link/link_rx.h
@@ -41,21 +41,21 @@ extern "C" {
 
 static inline void link_int_enable(uint8_t rhport)
 {
-	(void) rhport;
+  (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IEN(PERIB, INTB185) = 1;
+  IEN(PERIB, INTB185) = 1;
 #else
-	IEN(USB0, USBI0) = 1;
+  IEN(USB0, USBI0) = 1;
 #endif
 }
 
 static inline void link_int_disable(uint8_t rhport)
 {
-	(void) rhport;
+  (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IEN(PERIB, INTB185) = 0;
+  IEN(PERIB, INTB185) = 0;
 #else
-	IEN(USB0, USBI0) = 0;
+  IEN(USB0, USBI0) = 0;
 #endif
 }
 
@@ -63,9 +63,9 @@ static inline void link_int_disable(uint8_t rhport)
 static inline void link_phy_init(void)
 {
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IR(PERIB, INTB185) = 0;
+  IR(PERIB, INTB185) = 0;
 #else
-	IR(USB0, USBI0) = 0;
+  IR(USB0, USBI0) = 0;
 #endif
 }
 
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h
index f1d0130cc..eaf0b1ec4 100644
--- a/src/portable/renesas/link/link_type.h
+++ b/src/portable/renesas/link/link_type.h
@@ -42,933 +42,933 @@ TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 typedef struct TU_ATTR_PACKED {
-	union {
-		volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
+  union {
+    volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
 
-		struct {
-			uint16_t : 8;
-			volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
-			volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
-			uint16_t : 6;
-		} E_b;
-	};
+    struct {
+      uint16_t : 8;
+      volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
+      volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
+      uint16_t : 6;
+    } E_b;
+  };
 
-	union {
-		volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
+  union {
+    volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
 
-		struct {
-			volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
-		} N_b;
-	};
+    struct {
+      volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
+    } N_b;
+  };
 } LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
 
 TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
 
 /* LINK_REG Structure */
 typedef struct TU_ATTR_PACKED {
-	union {
-		volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
-
-		struct {
-			volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
-			uint16_t : 2;
-			volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
-			volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
-			volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
-			volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
-			uint16_t : 1;
-			volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
-			uint16_t : 1;
-			volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
-			uint16_t : 5;
-		} SYSCFG_b;
-	};
-
-	union {
-		volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
-
-		struct {
-			volatile uint16_t
-				BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
-			uint16_t : 12;
-		} BUSWAIT_b;
-	};
-
-	union {
-		volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
-
-		struct {
-			volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
-			volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
-			uint16_t : 2;
-			volatile const uint16_t
-				SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
-			volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
-			uint16_t : 7;
-			volatile const uint16_t
-				OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
-		} SYSSTS0_b;
-	};
-
-	union {
-		volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
-
-		struct {
-			volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
-			uint16_t : 15;
-		} PLLSTA_b;
-	};
-
-	union {
-		volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
-
-		struct {
-			volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
-			uint16_t : 1;
-			volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
-			volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
-			volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
-			volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
-			volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
-			volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
-			volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
-			volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
-			uint16_t : 4;
-		} DVSTCTR0_b;
-	};
-	volatile const uint16_t RESERVED;
-
-	union {
-		volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
-
-		struct {
-			volatile uint16_t UTST : 4; /* [3..0] Test Mode */
-			uint16_t : 12;
-		} TESTMODE_b;
-	};
-	volatile const uint16_t RESERVED1;
-	volatile const uint32_t RESERVED2;
-
-	union {
-		volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
-				volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED3;
-					volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
-				volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED4;
-					volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
-				volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED5;
-					volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
-			uint16_t : 1;
-			volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
-			uint16_t : 2;
-			volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
-			uint16_t : 2;
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} CFIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} CFIFOCTR_b;
-	};
-	volatile const uint32_t RESERVED6;
-
-	union {
-		volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-			uint16_t : 4;
-			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-			volatile uint16_t
-				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} D0FIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} D0FIFOCTR_b;
-	};
-
-	union {
-		volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-			uint16_t : 4;
-			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-			volatile uint16_t
-				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} D1FIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} D1FIFOCTR_b;
-	};
-
-	union {
-		volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
-
-		struct {
-			uint16_t : 8;
-			volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
-			volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
-			volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
-			volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
-			volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
-			volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
-			volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
-			volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
-		} INTENB0_b;
-	};
-
-	union {
-		volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
-
-		struct {
-			volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
-			uint16_t : 3;
-			volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
-			volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
-			volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
-			uint16_t : 4;
-			volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
-			volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
-			uint16_t : 1;
-			volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
-			volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
-		} INTENB1_b;
-	};
-	volatile const uint16_t RESERVED7;
-
-	union {
-		volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} BRDYENB_b;
-	};
-
-	union {
-		volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} NRDYENB_b;
-	};
-
-	union {
-		volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} BEMPENB_b;
-	};
-
-	union {
-		volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
-
-		struct {
-			uint16_t : 4;
-			volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
-			volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
-			volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
-			uint16_t : 1;
-			volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
-			uint16_t : 7;
-		} SOFCFG_b;
-	};
-
-	union {
-		volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
-
-		struct {
-			volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
-			volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
-			uint16_t : 1;
-			volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
-			volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
-			uint16_t : 2;
-			volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
-			uint16_t : 1;
-			volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
-			uint16_t : 3;
-			volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
-		} PHYSET_b;
-	};
-
-	union {
-		volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
-
-		struct {
-			volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
-			volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
-			volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
-			volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
-			volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
-			volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
-			volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
-			volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
-			volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
-			volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
-			volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
-			volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
-		} INTSTS0_b;
-	};
-
-	union {
-		volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
-
-		struct {
-			volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
-			uint16_t : 3;
-			volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
-			volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
-			volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
-			volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
-			volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
-			volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
-		} INTSTS1_b;
-	};
-	volatile const uint16_t RESERVED8;
-
-	union {
-		volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
-			uint16_t : 6;
-		} BRDYSTS_b;
-	};
-
-	union {
-		volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
-			uint16_t : 6;
-		} NRDYSTS_b;
-	};
-
-	union {
-		volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
-			uint16_t : 6;
-		} BEMPSTS_b;
-	};
-
-	union {
-		volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
-
-		struct {
-			volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
-			uint16_t : 3;
-			volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
-			volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
-		} FRMNUM_b;
-	};
-
-	union {
-		volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
-
-		struct {
-			volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
-			uint16_t : 12;
-			volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
-		} UFRMNUM_b;
-	};
-
-	union {
-		volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
-
-		struct {
-			volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
-			uint16_t : 1;
-			volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
-			uint16_t : 5;
-		} USBADDR_b;
-	};
-	volatile const uint16_t RESERVED9;
-
-	union {
-		volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
-
-		struct {
-			volatile uint16_t
-				BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
-			volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
-		} USBREQ_b;
-	};
-
-	union {
-		volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
-
-		struct {
-			volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
-		} USBVAL_b;
-	};
-
-	union {
-		volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
-
-		struct {
-			volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
-		} USBINDX_b;
-	};
-
-	union {
-		volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
-
-		struct {
-			volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
-		} USBLENG_b;
-	};
-
-	union {
-		volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
-
-		struct {
-			uint16_t : 4;
-			volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
-			uint16_t : 2;
-			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-			volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
-			uint16_t : 7;
-		} DCPCFG_b;
-	};
-
-	union {
-		volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
-
-		struct {
-			volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
-			uint16_t : 5;
-			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
-		} DCPMAXP_b;
-	};
-
-	union {
-		volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
-
-		struct {
-			volatile uint16_t PID : 2;  /* [1..0] Response PID */
-			volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
-			uint16_t : 2;
-			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
-			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
-			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-			uint16_t : 2;
-			volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
-			uint16_t : 2;
-			volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
-			volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
-		} DCPCTR_b;
-	};
-	volatile const uint16_t RESERVED10;
-
-	union {
-		volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
-
-		struct {
-			volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
-			uint16_t : 12;
-		} PIPESEL_b;
-	};
-	volatile const uint16_t RESERVED11;
-
-	union {
-		volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
-
-		struct {
-			volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
-			volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
-			uint16_t : 2;
-			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-			uint16_t : 1;
-			volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
-			volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
-			uint16_t : 3;
-			volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
-		} PIPECFG_b;
-	};
-	volatile const uint16_t RESERVED12;
-
-	union {
-		volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
-
-		struct {
-			volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
-			uint16_t : 3;
-			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
-		} PIPEMAXP_b;
-	};
-
-	union {
-		volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
-
-		struct {
-			volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
-			uint16_t : 9;
-			volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
-			uint16_t : 3;
-		} PIPEPERI_b;
-	};
-
-	union {
-		volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
-
-		struct {
-			volatile uint16_t PID : 2; /* [1..0] Response PID */
-			uint16_t : 3;
-			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
-			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
-			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-			volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
-			volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
-			uint16_t : 1;
-			volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
-			volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
-			volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
-			volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
-		} PIPE_CTR_b[9];
-	};
-	volatile const uint16_t RESERVED13;
-	volatile const uint32_t RESERVED14[3];
-	volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
-	volatile const uint32_t RESERVED15[3];
-
-	union {
-		volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
-
-		struct {
-			volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
-			volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
-			volatile uint16_t
-				IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
-			volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
-			volatile uint16_t
-				IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
-			volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
-			uint16_t : 1;
-			volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
-			volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
-			volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
-			uint16_t : 6;
-		} USBBCCTRL0_b;
-	};
-	volatile const uint16_t RESERVED16;
-	volatile const uint32_t RESERVED17[4];
-
-	union {
-		volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
-
-		struct {
-			volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
-			uint16_t : 15;
-		} UCKSEL_b;
-	};
-	volatile const uint16_t RESERVED18;
-	volatile const uint32_t RESERVED19;
-
-	union {
-		volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
-
-		struct {
-			volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
-			uint16_t : 6;
-			volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
-			uint16_t : 8;
-		} USBMC_b;
-	};
-	volatile const uint16_t RESERVED20;
-
-	union {
-		volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
-
-		struct {
-			uint16_t : 6;
-			volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
-			volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
-			volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
-			uint16_t : 1;
-		} DEVADD_b[10];
-	};
-	volatile const uint32_t RESERVED21[3];
-
-	union {
-		volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
-
-		struct {
-			volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
-			volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
-			volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
-			volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
-			uint32_t : 28;
-		} PHYSLEW_b;
-	};
-	volatile const uint32_t RESERVED22[3];
-
-	union {
-		volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
-
-		struct {
-			uint16_t : 7;
-			volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
-			uint16_t : 8;
-		} LPCTRL_b;
-	};
-
-	union {
-		volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
-
-		struct {
-			uint16_t : 14;
-			volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
-			uint16_t : 1;
-		} LPSTS_b;
-	};
-	volatile const uint32_t RESERVED23[15];
-
-	union {
-		volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
-
-		struct {
-			volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
-			volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
-			volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
-			volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
-			volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
-			volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
-			uint16_t : 2;
-			volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
-			volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
-			uint16_t : 6;
-		} BCCTRL_b;
-	};
-	volatile const uint16_t RESERVED24;
-
-	union {
-		volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
-
-		struct {
-			volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
-			volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
-			volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
-			volatile const uint16_t
-				DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
-			volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
-			uint16_t : 2;
-			volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
-			uint16_t : 1;
-		} PL1CTRL1_b;
-	};
-
-	union {
-		volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
-
-		struct {
-			uint16_t : 8;
-			volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
-			volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
-			uint16_t : 3;
-		} PL1CTRL2_b;
-	};
-
-	union {
-		volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
-
-		struct {
-			volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
-			volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
-			uint16_t : 13;
-		} HL1CTRL1_b;
-	};
-
-	union {
-		volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
-
-		struct {
-			volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
-			uint16_t : 4;
-			volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
-			volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
-			uint16_t : 2;
-			volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
-		} HL1CTRL2_b;
-	};
-	volatile const uint32_t RESERVED25[5];
-
-	union {
-		volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
-
-		struct {
-			uint32_t : 20;
-			volatile const uint32_t
-				DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
-			volatile const uint32_t
-				DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
-			uint32_t : 1;
-			volatile const uint32_t
-				DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
-			uint32_t : 8;
-		} DPUSR0R_b;
-	};
-
-	union {
-		volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			uint32_t : 4;
-			volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
-			volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
-			uint32_t : 1;
-			volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
-			uint32_t : 12;
-			volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
-			volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
-			uint32_t : 1;
-			volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
-			uint32_t : 8;
-		} DPUSR1R_b;
-	};
-
-	union {
-		volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
-			volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
-			uint16_t : 2;
-			volatile const uint16_t
-				DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
-			volatile const uint16_t
-				DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
-			uint16_t : 2;
-			volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
-			volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
-			uint16_t : 6;
-		} DPUSR2R_b;
-	};
-
-	union {
-		volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
-
-		struct {
-			volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
-			volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
-			uint16_t : 14;
-		} DPUSRCR_b;
-	};
-	volatile const uint32_t RESERVED26[165];
-
-	union {
-		volatile uint32_t
-			DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
-
-		struct {
-			volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
-			volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
-			uint32_t : 1;
-			volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
-			volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
-			uint32_t : 11;
-			volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
-			volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
-			uint32_t : 2;
-			volatile const uint32_t
-				DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
-			volatile const uint32_t
-				DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
-			uint32_t : 1;
-			volatile const uint32_t
-				DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
-			uint32_t : 8;
-		} DPUSR0R_FS_b;
-	};
-
-	union {
-		volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
-			volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
-			uint32_t : 2;
-			volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
-			volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
-			uint32_t : 1;
-			volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
-			uint32_t : 8;
-			volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
-			volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
-			uint32_t : 2;
-			volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
-			volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
-			uint32_t : 1;
-			volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
-			uint32_t : 8;
-		} DPUSR1R_FS_b;
-	};
+  union {
+    volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
+
+    struct {
+      volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
+      uint16_t : 2;
+      volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
+      volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
+      volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
+      volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
+      uint16_t : 1;
+      volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
+      uint16_t : 1;
+      volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
+      uint16_t : 5;
+    } SYSCFG_b;
+  };
+
+  union {
+    volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
+
+    struct {
+      volatile uint16_t
+        BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
+      uint16_t : 12;
+    } BUSWAIT_b;
+  };
+
+  union {
+    volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
+
+    struct {
+      volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
+      volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
+      uint16_t : 2;
+      volatile const uint16_t
+        SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
+      uint16_t : 7;
+      volatile const uint16_t
+        OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
+    } SYSSTS0_b;
+  };
+
+  union {
+    volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
+
+    struct {
+      volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
+      uint16_t : 15;
+    } PLLSTA_b;
+  };
+
+  union {
+    volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
+
+    struct {
+      volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
+      uint16_t : 1;
+      volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
+      volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
+      volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
+      volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
+      volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
+      volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
+      volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
+      volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
+      uint16_t : 4;
+    } DVSTCTR0_b;
+  };
+  volatile const uint16_t RESERVED;
+
+  union {
+    volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
+
+    struct {
+      volatile uint16_t UTST : 4; /* [3..0] Test Mode */
+      uint16_t : 12;
+    } TESTMODE_b;
+  };
+  volatile const uint16_t RESERVED1;
+  volatile const uint32_t RESERVED2;
+
+  union {
+    volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
+        volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED3;
+          volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
+        volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED4;
+          volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
+        volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED5;
+          volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
+      uint16_t : 1;
+      volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
+      uint16_t : 2;
+      volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
+      uint16_t : 2;
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } CFIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } CFIFOCTR_b;
+  };
+  volatile const uint32_t RESERVED6;
+
+  union {
+    volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t : 4;
+      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t
+        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } D0FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } D0FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t : 4;
+      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t
+        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } D1FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } D1FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
+
+    struct {
+      uint16_t : 8;
+      volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
+      volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
+      volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
+      volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
+      volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
+      volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
+      volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
+      volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
+    } INTENB0_b;
+  };
+
+  union {
+    volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
+
+    struct {
+      volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
+      uint16_t : 3;
+      volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
+      volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
+      volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
+      uint16_t : 4;
+      volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
+      volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
+      uint16_t : 1;
+      volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
+      volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
+    } INTENB1_b;
+  };
+  volatile const uint16_t RESERVED7;
+
+  union {
+    volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } BRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } NRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } BEMPENB_b;
+  };
+
+  union {
+    volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
+
+    struct {
+      uint16_t : 4;
+      volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
+      volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
+      volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
+      uint16_t : 1;
+      volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
+      uint16_t : 7;
+    } SOFCFG_b;
+  };
+
+  union {
+    volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
+
+    struct {
+      volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
+      volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
+      uint16_t : 1;
+      volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
+      volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
+      uint16_t : 2;
+      volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
+      uint16_t : 1;
+      volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
+      uint16_t : 3;
+      volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
+    } PHYSET_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
+
+    struct {
+      volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
+      volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
+      volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
+      volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
+      volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
+      volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
+      volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
+      volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
+      volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
+      volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
+      volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
+      volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
+    } INTSTS0_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
+
+    struct {
+      volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
+      uint16_t : 3;
+      volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
+      volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
+      volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
+      volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
+      volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
+      volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
+    } INTSTS1_b;
+  };
+  volatile const uint16_t RESERVED8;
+
+  union {
+    volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
+      uint16_t : 6;
+    } BRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
+      uint16_t : 6;
+    } NRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
+      uint16_t : 6;
+    } BEMPSTS_b;
+  };
+
+  union {
+    volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
+
+    struct {
+      volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
+      uint16_t : 3;
+      volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
+      volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
+    } FRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
+
+    struct {
+      volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
+      uint16_t : 12;
+      volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
+    } UFRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
+
+    struct {
+      volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
+      uint16_t : 1;
+      volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
+      uint16_t : 5;
+    } USBADDR_b;
+  };
+  volatile const uint16_t RESERVED9;
+
+  union {
+    volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
+
+    struct {
+      volatile uint16_t
+        BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
+      volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
+    } USBREQ_b;
+  };
+
+  union {
+    volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
+
+    struct {
+      volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
+    } USBVAL_b;
+  };
+
+  union {
+    volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
+
+    struct {
+      volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
+    } USBINDX_b;
+  };
+
+  union {
+    volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
+
+    struct {
+      volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
+    } USBLENG_b;
+  };
+
+  union {
+    volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
+
+    struct {
+      uint16_t : 4;
+      volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
+      uint16_t : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
+      uint16_t : 7;
+    } DCPCFG_b;
+  };
+
+  union {
+    volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+    struct {
+      volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
+      uint16_t : 5;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } DCPMAXP_b;
+  };
+
+  union {
+    volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
+
+    struct {
+      volatile uint16_t PID : 2;  /* [1..0] Response PID */
+      volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
+      uint16_t : 2;
+      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
+      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+      uint16_t : 2;
+      volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
+      uint16_t : 2;
+      volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
+      volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
+    } DCPCTR_b;
+  };
+  volatile const uint16_t RESERVED10;
+
+  union {
+    volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
+
+    struct {
+      volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
+      uint16_t : 12;
+    } PIPESEL_b;
+  };
+  volatile const uint16_t RESERVED11;
+
+  union {
+    volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
+
+    struct {
+      volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
+      volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
+      uint16_t : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      uint16_t : 1;
+      volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
+      volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
+      uint16_t : 3;
+      volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
+    } PIPECFG_b;
+  };
+  volatile const uint16_t RESERVED12;
+
+  union {
+    volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+    struct {
+      volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
+      uint16_t : 3;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } PIPEMAXP_b;
+  };
+
+  union {
+    volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
+
+    struct {
+      volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
+      uint16_t : 9;
+      volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
+      uint16_t : 3;
+    } PIPEPERI_b;
+  };
+
+  union {
+    volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
+
+    struct {
+      volatile uint16_t PID : 2; /* [1..0] Response PID */
+      uint16_t : 3;
+      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
+      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+      volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
+      volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
+      uint16_t : 1;
+      volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
+      volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
+      volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
+      volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
+    } PIPE_CTR_b[9];
+  };
+  volatile const uint16_t RESERVED13;
+  volatile const uint32_t RESERVED14[3];
+  volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
+  volatile const uint32_t RESERVED15[3];
+
+  union {
+    volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
+
+    struct {
+      volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
+      volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
+      volatile uint16_t
+        IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+      volatile uint16_t
+        IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+      uint16_t : 1;
+      volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+      volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
+      volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
+      uint16_t : 6;
+    } USBBCCTRL0_b;
+  };
+  volatile const uint16_t RESERVED16;
+  volatile const uint32_t RESERVED17[4];
+
+  union {
+    volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
+
+    struct {
+      volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
+      uint16_t : 15;
+    } UCKSEL_b;
+  };
+  volatile const uint16_t RESERVED18;
+  volatile const uint32_t RESERVED19;
+
+  union {
+    volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
+
+    struct {
+      volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
+      uint16_t : 6;
+      volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
+      uint16_t : 8;
+    } USBMC_b;
+  };
+  volatile const uint16_t RESERVED20;
+
+  union {
+    volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
+
+    struct {
+      uint16_t : 6;
+      volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
+      volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
+      volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
+      uint16_t : 1;
+    } DEVADD_b[10];
+  };
+  volatile const uint32_t RESERVED21[3];
+
+  union {
+    volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
+
+    struct {
+      volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
+      volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
+      uint32_t : 28;
+    } PHYSLEW_b;
+  };
+  volatile const uint32_t RESERVED22[3];
+
+  union {
+    volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
+
+    struct {
+      uint16_t : 7;
+      volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
+      uint16_t : 8;
+    } LPCTRL_b;
+  };
+
+  union {
+    volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
+
+    struct {
+      uint16_t : 14;
+      volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
+      uint16_t : 1;
+    } LPSTS_b;
+  };
+  volatile const uint32_t RESERVED23[15];
+
+  union {
+    volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
+
+    struct {
+      volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
+      volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
+      volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
+      volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
+      volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
+      volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
+      uint16_t : 2;
+      volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
+      volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
+      uint16_t : 6;
+    } BCCTRL_b;
+  };
+  volatile const uint16_t RESERVED24;
+
+  union {
+    volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
+
+    struct {
+      volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
+      volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
+      volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
+      volatile const uint16_t
+        DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
+      volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
+      uint16_t : 2;
+      volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
+      uint16_t : 1;
+    } PL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
+
+    struct {
+      uint16_t : 8;
+      volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
+      volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
+      uint16_t : 3;
+    } PL1CTRL2_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
+
+    struct {
+      volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
+      volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
+      uint16_t : 13;
+    } HL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
+
+    struct {
+      volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
+      uint16_t : 4;
+      volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
+      volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
+      uint16_t : 2;
+      volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
+    } HL1CTRL2_b;
+  };
+  volatile const uint32_t RESERVED25[5];
+
+  union {
+    volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct {
+      uint32_t : 20;
+      volatile const uint32_t
+        DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
+      volatile const uint32_t
+        DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
+      uint32_t : 1;
+      volatile const uint32_t
+        DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
+      uint32_t : 8;
+    } DPUSR0R_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      uint32_t : 4;
+      volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
+      volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
+      uint32_t : 1;
+      volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
+      uint32_t : 12;
+      volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
+      volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
+      uint32_t : 1;
+      volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
+      uint32_t : 8;
+    } DPUSR1R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
+      volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
+      uint16_t : 2;
+      volatile const uint16_t
+        DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
+      volatile const uint16_t
+        DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
+      uint16_t : 2;
+      volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
+      volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
+      uint16_t : 6;
+    } DPUSR2R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+    struct {
+      volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
+      volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
+      uint16_t : 14;
+    } DPUSRCR_b;
+  };
+  volatile const uint32_t RESERVED26[165];
+
+  union {
+    volatile uint32_t
+      DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct {
+      volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
+      volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
+      uint32_t : 1;
+      volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
+      volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
+      uint32_t : 11;
+      volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+      volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
+      uint32_t : 2;
+      volatile const uint32_t
+        DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
+      volatile const uint32_t
+        DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
+      uint32_t : 1;
+      volatile const uint32_t
+        DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
+      uint32_t : 8;
+    } DPUSR0R_FS_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
+      volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
+      uint32_t : 2;
+      volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
+      volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
+      uint32_t : 1;
+      volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
+      uint32_t : 8;
+      volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
+      volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
+      uint32_t : 2;
+      volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
+      volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
+      uint32_t : 1;
+      volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
+      uint32_t : 8;
+    } DPUSR1R_FS_b;
+  };
 } LINK_REG_t; /* Size = 1032 (0x408) */
 
 TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset");
@@ -1034,7 +1034,7 @@ TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offs
 TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset");
 
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
-	TU_ATTR_BIT_FIELD_ORDER_END
+TU_ATTR_BIT_FIELD_ORDER_END
 
 /*--------------------------------------------------------------------*/
 /* Register Bit Definitions                                           */