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esp32-s2_dfu
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adding lpc1549, but couldnt recieve setup packet, though setup received interrupt is triggered

This commit is contained in:
hathach 2019-10-04 13:13:51 +07:00
parent 13d37e4a36
commit 281cd858b0
No known key found for this signature in database
GPG Key ID: 2FA891220FBFD581
7 changed files with 34 additions and 34 deletions
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2
examples/device/cdc_msc/ses/lpc13xx/lpc13xx.emProject
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@ -19,7 +19,7 @@
arm_target_interface_type="SWD"
build_treat_warnings_as_errors="Yes"
c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;CFG_TUSB_MCU=OPT_MCU_LPC13XX;CFG_TUSB_MEM_SECTION= __attribute__((section(".bss3")));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))"
c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc_chip_13xx/inc;$(rootDir)/src"
c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/hw/mcu/nxp/lpc_driver/lpc13xx/lpc_chip_13xx/inc;$(rootDir)/src"
debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
debug_target_connection="J-Link"
gcc_enable_all_warnings="Yes"

4
hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
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@ -58,8 +58,6 @@ static const PINMUX_GRP_T pinmuxing[] =
{0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
};
#if 1
/* Setup system clocking */
static void SystemSetupClocking(void)
{
@ -114,13 +112,11 @@ static void SystemSetupClocking(void)
/* Wait for PLL to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
}
#endif
// Invoked by startup code
void SystemInit(void)
{
SystemSetupClocking();
// Chip_SystemInit();
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
/* Enable IOCON clock */

2
hw/bsp/lpcxpresso1347/board.mk
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@ -7,7 +7,7 @@ CFLAGS += \
-D__USE_LPCOPEN \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# startup.c and lpc_types.h cause following errors

6
hw/bsp/lpcxpresso1549/board.mk
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@ -5,13 +5,11 @@ CFLAGS += \
-nostdlib \
-DCORE_M3 \
-D__USE_LPCOPEN \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
# -DCFG_EXAMPLE_MSC_READONLY \
# startup.c and lpc_types.h cause following errors
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable
MCU_DIR = hw/mcu/nxp/lpc_driver/lpc15xx/lpc_chip_15xx

14
hw/bsp/lpcxpresso1549/lpcxpresso1549.c
View File

@ -40,24 +40,21 @@ const uint32_t RTCOscRateIn = 32768;
/* Pin muxing table, only items that need changing from their default pin
state are in this table. */
static const PINMUX_GRP_T pinmuxing[] =
static const PINMUX_GRP_T pinmuxing[] =
{
{1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, /* PIO0_3 used for USB_VBUS */
{1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, /* PIO1_11-ISP_1 (VBUS) */
};
// Invoked by startup code
void SystemInit(void)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
Chip_SYSCTL_PeriphReset(RESET_IOCON);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
Chip_SYSCTL_PeriphReset(RESET_IOCON);
// Pin Mux
// Pin Mux
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
// SWM USB
Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I, 1, 11);
Chip_SetupXtalClocking();
}
@ -82,6 +79,7 @@ void board_init(void)
Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
// USB: Setup PLL clock, and power
Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I, 1, 11);
Chip_USB_Init();
}

38
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
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@ -28,9 +28,11 @@
/* Since 2012 starting with LPC11uxx, NXP start to use common USB Device Controller with code name LPC IP3511
* for almost their new MCUs. Currently supported and tested families are
* - LPC11Uxx
* - LPC13xx
* - LPC51Uxx
* - LPC11U68, LPC11U37
* - LPC1347
* - LPC51U68
* - LPC54114
* - LPC55s69
*
* For similar controller of other families, this file may require some minimal changes to work with.
* Previous MCUs such as LPC17xx, LPC40xx, LPC18xx, LPC43xx have their own driver implementation.
@ -38,20 +40,23 @@
#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
CFG_TUSB_MCU == OPT_MCU_LPC13XX || \
CFG_TUSB_MCU == OPT_MCU_LPC15XX || \
CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
CFG_TUSB_MCU == OPT_MCU_LPC55XX)
#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX
// LPC11Uxx and LPC13xx use lpcopen
#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
// LPC 11Uxx, 13xx, 15xx use lpcopen
#include "chip.h"
#define DCD_REGS LPC_USB
#define DCD_IRQHandler USB_IRQHandler
#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
CFG_TUSB_MCU == OPT_MCU_LPC55XX // TODO 55xx has dual usb controllers
#include "fsl_device_registers.h"
#define DCD_REGS USB0
#define DCD_IRQHandler USB0_IRQHandler
#endif
#include "device/dcd.h"
@ -61,6 +66,9 @@
//--------------------------------------------------------------------+
// Number of endpoints
// - 11 13 15 51 54 has 5x2 endpoints
// - 18/43 usb0 & 55s usb1 (HS) has 6x2 endpoints
// - 18/43 usb1 & 55s usb0 (FS) has 4x2 endpoints
#define EP_COUNT 10
// only SRAM1 & USB RAM can be used for transfer.
@ -166,7 +174,7 @@ void dcd_init(uint8_t rhport)
DCD_REGS->INTSTAT = DCD_REGS->INTSTAT; // clear all pending interrupt
DCD_REGS->INTEN = INT_DEVICE_STATUS_MASK;
DCD_REGS->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
NVIC_ClearPendingIRQ(USB0_IRQn);
}
@ -270,7 +278,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
return true;
return true;
}
//--------------------------------------------------------------------+
@ -329,7 +337,7 @@ static void process_xfer_isr(uint32_t int_status)
void DCD_IRQHandler(void)
{
uint32_t const dev_cmd_stat = DCD_REGS->DEVCMDSTAT;
uint32_t const cmd_stat = DCD_REGS->DEVCMDSTAT;
uint32_t int_status = DCD_REGS->INTSTAT & DCD_REGS->INTEN;
DCD_REGS->INTSTAT = int_status; // Acknowledge handled interrupt
@ -340,16 +348,16 @@ void DCD_IRQHandler(void)
if ( int_status & INT_DEVICE_STATUS_MASK )
{
DCD_REGS->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
{
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
{
// device disconnect
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
// debouncing as this can be set when device is powering
dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
@ -357,12 +365,12 @@ void DCD_IRQHandler(void)
}
// TODO support suspend & resume
if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
{
if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
if (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
{ // suspend signal, bus idle for more than 3ms
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
}
@ -376,7 +384,7 @@ void DCD_IRQHandler(void)
}
// Setup Receive
if ( tu_bit_test(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{
// Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
_dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;

2
src/tusb_option.h
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@ -39,7 +39,7 @@
// LPC
#define OPT_MCU_LPC11UXX 1 ///< NXP LPC11Uxx
#define OPT_MCU_LPC13XX 2 ///< NXP LPC13xx
#define OPT_MCU_LPC15xx 3 ///< NXP LPC15xx
#define OPT_MCU_LPC15XX 3 ///< NXP LPC15xx
#define OPT_MCU_LPC175X_6X 4 ///< NXP LPC175x, LPC176x
#define OPT_MCU_LPC177X_8X 5 ///< NXP LPC177x, LPC178x
#define OPT_MCU_LPC18XX 6 ///< NXP LPC18xx