lpcxpresso1549 board test running
This commit is contained in:
hathach
parent
7fd68efe7b
commit
13d37e4a36
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@ -0,0 +1,47 @@
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m3 \
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-nostdlib \
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-DCORE_M3 \
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-D__USE_LPCOPEN \
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-DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
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-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
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# -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
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# -DCFG_EXAMPLE_MSC_READONLY \
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# startup.c and lpc_types.h cause following errors
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CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable
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MCU_DIR = hw/mcu/nxp/lpc_driver/lpc15xx/lpc_chip_15xx
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/lpc1549.ld
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SRC_C += \
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$(MCU_DIR)/../gcc/cr_startup_lpc15xx.c \
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$(MCU_DIR)/src/chip_15xx.c \
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$(MCU_DIR)/src/clock_15xx.c \
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$(MCU_DIR)/src/gpio_15xx.c \
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$(MCU_DIR)/src/iocon_15xx.c \
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$(MCU_DIR)/src/swm_15xx.c \
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$(MCU_DIR)/src/sysctl_15xx.c \
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$(MCU_DIR)/src/sysinit_15xx.c
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INC += \
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$(TOP)/$(MCU_DIR)/inc
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# For TinyUSB port source
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VENDOR = nxp
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CHIP_FAMILY = lpc_ip3511
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM3
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# For flash-jlink target
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JLINK_DEVICE = LPC1549
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JLINK_IF = swd
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# flash using jlink
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flash: flash-jlink
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@ -0,0 +1,246 @@
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/*
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* GENERATED FILE - DO NOT EDIT
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* Copyright (c) 2008-2013 Code Red Technologies Ltd,
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* Copyright 2015, 2018-2019 NXP
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* (c) NXP Semiconductors 2013-2019
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* Generated linker script file for LPC1549
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05] on Oct 3, 2019 2:55:18 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
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Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
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Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
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Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
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}
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/* Define a symbol for the top of each memory region */
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__base_MFlash256 = 0x0 ; /* MFlash256 */
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__base_Flash = 0x0 ; /* Flash */
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__top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
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__top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
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__base_Ram0_16 = 0x2000000 ; /* Ram0_16 */
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__base_RAM = 0x2000000 ; /* RAM */
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__top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
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__top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
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__base_Ram1_16 = 0x2004000 ; /* Ram1_16 */
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__base_RAM2 = 0x2004000 ; /* RAM2 */
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__top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
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__top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
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__base_Ram2_4 = 0x2008000 ; /* Ram2_4 */
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__base_RAM3 = 0x2008000 ; /* RAM3 */
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__top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
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__top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
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ENTRY(ResetISR)
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SECTIONS
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{
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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LONG(LOADADDR(.data_RAM3));
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LONG( ADDR(.data_RAM3));
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LONG( SIZEOF(.data_RAM3));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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LONG( ADDR(.bss_RAM3));
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LONG( SIZEOF(.bss_RAM3));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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} > MFlash256
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > MFlash256
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > MFlash256
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__exidx_start = .;
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.ARM.exidx : ALIGN(4)
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > MFlash256
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__exidx_end = .;
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_etext = .;
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/* DATA section for Ram1_16 */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$Ram1_16)
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*(.data.$RAM2)
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*(.data.$Ram1_16)
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*(.data.$RAM2.*)
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*(.data.$Ram1_16.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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} > Ram1_16 AT>MFlash256
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/* DATA section for Ram2_4 */
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.data_RAM3 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM3 = .) ;
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*(.ramfunc.$RAM3)
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*(.ramfunc.$Ram2_4)
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*(.data.$RAM3)
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*(.data.$Ram2_4)
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*(.data.$RAM3.*)
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*(.data.$Ram2_4.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM3 = .) ;
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} > Ram2_4 AT>MFlash256
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/* MAIN DATA SECTION */
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.uninit_RESERVED (NOLOAD) :
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{
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. = ALIGN(4) ;
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KEEP(*(.bss.$RESERVED*))
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. = ALIGN(4) ;
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_end_uninit_RESERVED = .;
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} > Ram0_16
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/* Main DATA section (Ram0_16) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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*(vtable)
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*(.ramfunc*)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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} > Ram0_16 AT>MFlash256
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/* BSS section for Ram1_16 */
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.bss_RAM2 :
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{
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. = ALIGN(4) ;
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PROVIDE(__start_bss_RAM2 = .) ;
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*(.bss.$RAM2)
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*(.bss.$Ram1_16)
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*(.bss.$RAM2.*)
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*(.bss.$Ram1_16.*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM2 = .) ;
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} > Ram1_16
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/* BSS section for Ram2_4 */
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.bss_RAM3 :
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{
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. = ALIGN(4) ;
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PROVIDE(__start_bss_RAM3 = .) ;
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*(.bss.$RAM3)
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*(.bss.$Ram2_4)
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*(.bss.$RAM3.*)
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*(.bss.$Ram2_4.*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM3 = .) ;
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} > Ram2_4
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/* MAIN BSS SECTION */
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.bss :
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{
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. = ALIGN(4) ;
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_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4) ;
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_ebss = .;
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PROVIDE(end = .);
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} > Ram0_16
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/* NOINIT section for Ram1_16 */
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.noinit_RAM2 (NOLOAD) :
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{
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. = ALIGN(4) ;
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*(.noinit.$RAM2)
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*(.noinit.$Ram1_16)
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*(.noinit.$RAM2.*)
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*(.noinit.$Ram1_16.*)
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. = ALIGN(4) ;
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} > Ram1_16
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/* NOINIT section for Ram2_4 */
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.noinit_RAM3 (NOLOAD) :
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{
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. = ALIGN(4) ;
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*(.noinit.$RAM3)
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*(.noinit.$Ram2_4)
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*(.noinit.$RAM3.*)
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*(.noinit.$Ram2_4.*)
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. = ALIGN(4) ;
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} > Ram2_4
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/* DEFAULT NOINIT SECTION */
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.noinit (NOLOAD):
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{
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. = ALIGN(4) ;
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_noinit = .;
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*(.noinit*)
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. = ALIGN(4) ;
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_end_noinit = .;
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} > Ram0_16
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PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
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PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
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/* ## Create checksum value (used in startup) ## */
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PROVIDE(__valid_user_code_checksum = 0 -
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(_vStackTop
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+ (ResetISR + 1)
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+ (NMI_Handler + 1)
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+ (HardFault_Handler + 1)
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+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
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+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
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+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
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) );
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/* Provide basic symbols giving location and size of main text
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* block, including initial values of RW data sections. Note that
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* these will need extending to give a complete picture with
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* complex images (e.g multiple Flash banks).
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*/
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_image_start = LOADADDR(.text);
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_image_end = LOADADDR(.data) + SIZEOF(.data);
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_image_size = _image_end - _image_start;
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}
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@ -0,0 +1,128 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "chip.h"
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#include "../board.h"
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#define LED_PORT 0
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#define LED_PIN 25
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// Wake Switch
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#define BUTTON_PORT 0
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#define BUTTON_PIN 17
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/* System oscillator rate and RTC oscillator rate */
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const uint32_t OscRateIn = 12000000;
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const uint32_t RTCOscRateIn = 32768;
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/* Pin muxing table, only items that need changing from their default pin
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state are in this table. */
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static const PINMUX_GRP_T pinmuxing[] =
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{
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{1, 11, (IOCON_MODE_PULLDOWN | IOCON_DIGMODE_EN)}, /* PIO0_3 used for USB_VBUS */
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};
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// Invoked by startup code
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void SystemInit(void)
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{
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
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Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
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Chip_SYSCTL_PeriphReset(RESET_IOCON);
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// Pin Mux
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Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
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// SWM USB
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Chip_SWM_MovablePortPinAssign(SWM_USB_VBUS_I, 1, 11);
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Chip_SetupXtalClocking();
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}
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void board_init(void)
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{
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SystemCoreClockUpdate();
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#if CFG_TUSB_OS == OPT_OS_NONE
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// 1ms tick timer
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SysTick_Config(SystemCoreClock / 1000);
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#elif CFG_TUSB_OS == OPT_OS_FREERTOS
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
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NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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#endif
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Chip_GPIO_Init(LPC_GPIO);
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// LED
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Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
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// Button
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Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
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// USB: Setup PLL clock, and power
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Chip_USB_Init();
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void SysTick_Handler (void)
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{
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system_ticks++;
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}
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uint32_t board_millis(void)
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{
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return system_ticks;
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}
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#endif
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void board_led_write(bool state)
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{
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Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
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}
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uint32_t board_button_read(void)
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{
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// active low
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return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
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}
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int board_uart_read(uint8_t* buf, int len)
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{
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(void) buf;
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(void) len;
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return 0;
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}
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int board_uart_write(void const * buf, int len)
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{
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(void) buf;
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(void) len;
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return 0;
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}
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@ -38,7 +38,8 @@
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// LPC
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#define OPT_MCU_LPC11UXX 1 ///< NXP LPC11Uxx
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#define OPT_MCU_LPC13XX 3 ///< NXP LPC13xx
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#define OPT_MCU_LPC13XX 2 ///< NXP LPC13xx
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#define OPT_MCU_LPC15xx 3 ///< NXP LPC15xx
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#define OPT_MCU_LPC175X_6X 4 ///< NXP LPC175x, LPC176x
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#define OPT_MCU_LPC177X_8X 5 ///< NXP LPC177x, LPC178x
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#define OPT_MCU_LPC18XX 6 ///< NXP LPC18xx
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