2013-10-29 05:27:25 +01:00
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/**************************************************************************/
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/*!
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@file dcd_lpc43xx.c
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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#include "tusb_option.h"
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2018-07-23 10:25:45 +02:00
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#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
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2013-10-29 05:27:25 +01:00
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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2018-03-12 16:45:35 +01:00
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#include "common/tusb_common.h"
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2018-03-02 12:43:00 +01:00
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#include "tusb_hal.h"
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2013-10-29 05:27:25 +01:00
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#include "osal/osal.h"
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2018-03-28 08:44:39 +02:00
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#include "device/dcd.h"
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2013-10-29 05:27:25 +01:00
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#include "dcd_lpc43xx.h"
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2018-03-09 17:04:53 +01:00
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#include "LPC43xx.h"
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#include "lpc43xx_cgu.h"
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2013-10-29 05:27:25 +01:00
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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2013-11-06 08:20:45 +01:00
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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2013-10-29 05:27:25 +01:00
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typedef struct {
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2018-03-30 13:36:04 +02:00
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dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
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2013-11-01 06:11:26 +01:00
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dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
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2013-10-29 05:27:25 +01:00
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}dcd_data_t;
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2018-04-14 09:08:48 +02:00
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#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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2018-11-22 11:21:07 +01:00
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
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2013-11-06 08:20:45 +01:00
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#endif
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2013-10-29 05:27:25 +01:00
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2018-04-14 09:08:48 +02:00
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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2018-11-22 11:21:07 +01:00
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
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2013-11-06 08:20:45 +01:00
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#endif
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static LPC_USB0_Type * const LPC_USB[2] = { LPC_USB0, ((LPC_USB0_Type*) LPC_USB1_BASE) };
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2018-11-22 11:21:07 +01:00
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static dcd_data_t* const dcd_data_ptr[2] =
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{
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#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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&dcd_data0,
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#else
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NULL,
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#endif
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#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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&dcd_data1
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#else
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NULL
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#endif
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};
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2013-10-29 05:27:25 +01:00
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//--------------------------------------------------------------------+
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2013-11-01 06:11:26 +01:00
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// CONTROLLER API
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2013-10-29 05:27:25 +01:00
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//--------------------------------------------------------------------+
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2018-03-28 08:47:58 +02:00
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void dcd_connect(uint8_t rhport)
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2013-10-29 05:27:25 +01:00
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{
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2018-03-23 06:17:47 +01:00
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LPC_USB[rhport]->USBCMD_D |= BIT_(0);
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2013-10-29 05:27:25 +01:00
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}
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2018-03-28 08:47:58 +02:00
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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2013-10-29 05:27:25 +01:00
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{
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2018-03-23 06:17:47 +01:00
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LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
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2013-10-29 05:27:25 +01:00
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}
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2018-03-28 08:47:58 +02:00
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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2013-10-29 05:27:25 +01:00
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{
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}
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2013-10-29 08:19:56 +01:00
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/// follows LPC43xx User Manual 23.10.3
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2018-03-23 06:17:47 +01:00
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static void bus_reset(uint8_t rhport)
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2013-10-29 05:27:25 +01:00
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{
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2018-03-23 06:17:47 +01:00
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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2013-10-29 08:19:56 +01:00
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2013-10-30 06:20:00 +01:00
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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2018-11-22 11:21:07 +01:00
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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lpc_usb->ENDPTCTRL1 = lpc_usb->ENDPTCTRL2 = lpc_usb->ENDPTCTRL3 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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2013-10-30 06:20:00 +01:00
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2013-11-06 08:20:45 +01:00
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// USB1 only has 3 non-control endpoints
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2018-03-23 06:17:47 +01:00
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if ( rhport == 0)
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2013-11-06 08:20:45 +01:00
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{
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lpc_usb->ENDPTCTRL4 = lpc_usb->ENDPTCTRL5 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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2013-10-29 08:19:56 +01:00
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//------------- Clear All Registers -------------//
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2013-11-06 08:20:45 +01:00
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lpc_usb->ENDPTNAK = lpc_usb->ENDPTNAK;
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lpc_usb->ENDPTNAKEN = 0;
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
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lpc_usb->ENDPTCOMPLETE = lpc_usb->ENDPTCOMPLETE;
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2013-10-29 08:19:56 +01:00
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2013-11-06 08:20:45 +01:00
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while (lpc_usb->ENDPTPRIME);
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lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
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while (lpc_usb->ENDPTFLUSH);
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2013-10-29 08:19:56 +01:00
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// read reset bit in portsc
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//------------- Queue Head & Queue TD -------------//
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2018-03-23 06:17:47 +01:00
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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2013-11-06 08:20:45 +01:00
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2018-10-23 07:19:32 +02:00
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tu_memclr(p_dcd, sizeof(dcd_data_t));
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2013-10-29 08:19:56 +01:00
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//------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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2013-11-06 08:20:45 +01:00
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p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
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2018-04-12 08:23:52 +02:00
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p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
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2013-11-06 08:20:45 +01:00
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p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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2013-10-29 05:27:25 +01:00
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2013-11-06 08:20:45 +01:00
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p_dcd->qhd[0].int_on_setup = 1; // OUT only
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2013-11-15 07:26:12 +01:00
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2013-10-29 05:27:25 +01:00
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}
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2018-03-28 08:47:58 +02:00
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bool dcd_init(uint8_t rhport)
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2013-10-29 05:27:25 +01:00
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{
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2018-03-23 06:17:47 +01:00
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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2013-11-06 08:20:45 +01:00
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2018-10-23 07:19:32 +02:00
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tu_memclr(p_dcd, sizeof(dcd_data_t));
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2013-11-06 08:20:45 +01:00
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lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
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2013-11-06 08:53:18 +01:00
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lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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2018-03-08 08:55:02 +01:00
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lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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2013-11-15 07:26:12 +01:00
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lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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lpc_usb->USBCMD_D |= BIT_(0); // connect
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2013-10-29 05:27:25 +01:00
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2018-03-13 10:30:53 +01:00
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// enable interrupt
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2018-03-23 06:17:47 +01:00
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NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
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2018-03-13 10:30:53 +01:00
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2018-03-02 16:46:36 +01:00
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return true;
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2013-10-29 05:27:25 +01:00
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}
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//--------------------------------------------------------------------+
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2018-11-22 15:58:06 +01:00
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// HELPER
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2013-10-29 05:27:25 +01:00
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//--------------------------------------------------------------------+
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2018-11-22 15:58:06 +01:00
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// index to bit position in register
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static inline uint8_t ep_idx2bit(uint8_t ep_idx)
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2013-10-29 05:27:25 +01:00
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{
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2018-11-22 15:58:06 +01:00
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return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
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2013-10-29 05:27:25 +01:00
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}
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static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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{
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2018-10-23 07:19:32 +02:00
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tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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2013-10-29 05:27:25 +01:00
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2013-11-01 06:11:26 +01:00
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p_qtd->next = QTD_NEXT_INVALID;
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2013-10-29 05:27:25 +01:00
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p_qtd->active = 1;
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2013-11-01 06:11:26 +01:00
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p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
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2013-10-29 05:27:25 +01:00
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if (data_ptr != NULL)
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{
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p_qtd->buffer[0] = (uint32_t) data_ptr;
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for(uint8_t i=1; i<5; i++)
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{
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2018-08-23 15:09:28 +02:00
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p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
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2013-10-29 05:27:25 +01:00
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}
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}
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}
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2018-11-22 15:58:06 +01:00
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static inline volatile uint32_t * get_endpt_ctrl_reg(uint8_t rhport, uint8_t ep_idx)
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2013-11-01 06:11:26 +01:00
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{
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2018-11-22 15:58:06 +01:00
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return &(LPC_USB[rhport]->ENDPTCTRL0) + ep_idx/2;
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2013-11-01 06:11:26 +01:00
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}
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//--------------------------------------------------------------------+
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2018-11-22 11:40:20 +01:00
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// DCD Endpoint Port
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2013-11-01 06:11:26 +01:00
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//--------------------------------------------------------------------+
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2018-03-28 08:47:58 +02:00
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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2013-11-01 06:11:26 +01:00
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{
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2018-11-22 15:58:06 +01:00
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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uint8_t const ep_idx = 2*epnum + dir;
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2013-11-01 06:11:26 +01:00
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2018-11-22 15:58:06 +01:00
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volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
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if ( epnum == 0)
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2018-03-21 10:08:42 +01:00
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{
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// Stall both Control IN and OUT
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2018-11-22 15:58:06 +01:00
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(*endpt_ctrl) |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
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2018-03-21 10:08:42 +01:00
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}else
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{
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2018-11-22 15:58:06 +01:00
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(*endpt_ctrl) |= ENDPTCTRL_MASK_STALL << (ep_idx & 0x01 ? 16 : 0);
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2018-03-21 10:08:42 +01:00
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}
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2013-10-29 05:27:25 +01:00
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}
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2018-11-22 11:21:07 +01:00
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// TOOD implement later
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bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
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{
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return false;
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}
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2018-03-28 08:47:58 +02:00
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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2013-11-01 08:44:14 +01:00
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{
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2018-11-22 15:58:06 +01:00
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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uint8_t const ep_idx = 2*epnum + dir;
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volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
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2013-11-01 08:44:14 +01:00
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2013-11-01 16:00:39 +01:00
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// data toggle also need to be reset
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2018-11-22 15:58:06 +01:00
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(*endpt_ctrl) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
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(*endpt_ctrl) &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
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2013-11-01 08:44:14 +01:00
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}
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2018-03-28 08:47:58 +02:00
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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2013-10-29 05:27:25 +01:00
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{
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// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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2018-03-06 10:50:50 +01:00
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// TODO not support ISO yet
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2018-08-13 13:10:23 +02:00
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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2013-10-29 05:27:25 +01:00
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2018-11-22 15:37:23 +01:00
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uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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2013-10-30 08:13:06 +01:00
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2013-10-29 05:27:25 +01:00
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//------------- Prepare Queue Head -------------//
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2018-03-23 06:17:47 +01:00
|
|
|
dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
|
2018-10-23 07:19:32 +02:00
|
|
|
tu_memclr(p_qhd, sizeof(dcd_qhd_t));
|
2013-10-29 05:27:25 +01:00
|
|
|
|
|
|
|
p_qhd->zero_length_termination = 1;
|
2013-11-01 06:11:26 +01:00
|
|
|
p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
|
|
|
|
p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
|
2013-10-29 05:27:25 +01:00
|
|
|
|
2013-11-06 08:20:45 +01:00
|
|
|
//------------- Endpoint Control Register -------------//
|
2018-11-22 15:37:23 +01:00
|
|
|
volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
|
2013-11-06 08:20:45 +01:00
|
|
|
|
2018-03-06 11:03:19 +01:00
|
|
|
// endpoint must not be already enabled
|
2018-11-22 15:37:23 +01:00
|
|
|
TU_VERIFY( !( (*endpt_ctrl) & (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
|
2018-03-06 11:03:19 +01:00
|
|
|
|
2018-11-22 15:37:23 +01:00
|
|
|
(*endpt_ctrl) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
|
2013-10-29 05:27:25 +01:00
|
|
|
|
2018-03-06 11:03:19 +01:00
|
|
|
return true;
|
2013-10-29 08:19:56 +01:00
|
|
|
}
|
|
|
|
|
2018-03-28 08:47:58 +02:00
|
|
|
bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
|
2013-10-29 09:09:16 +01:00
|
|
|
{
|
2018-11-22 15:37:23 +01:00
|
|
|
uint8_t const epnum = edpt_number(ep_addr);
|
|
|
|
uint8_t const dir = edpt_dir(ep_addr);
|
|
|
|
uint8_t const ep_idx = 2*epnum + dir;
|
|
|
|
|
2018-03-23 06:17:47 +01:00
|
|
|
dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
|
2018-11-22 15:37:23 +01:00
|
|
|
dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
|
2013-10-29 09:09:16 +01:00
|
|
|
|
2018-11-22 15:37:23 +01:00
|
|
|
return p_qtd->active;
|
2014-04-24 18:40:28 +02:00
|
|
|
// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
|
2013-10-29 09:09:16 +01:00
|
|
|
}
|
|
|
|
|
2018-11-26 08:56:07 +01:00
|
|
|
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
2013-10-29 08:19:56 +01:00
|
|
|
{
|
2018-11-22 15:37:23 +01:00
|
|
|
uint8_t const epnum = edpt_number(ep_addr);
|
|
|
|
uint8_t const dir = edpt_dir(ep_addr);
|
|
|
|
uint8_t const ep_idx = 2*epnum + dir;
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2018-11-22 15:37:23 +01:00
|
|
|
if ( epnum == 0 )
|
2013-11-01 06:11:26 +01:00
|
|
|
{
|
2018-11-22 15:37:23 +01:00
|
|
|
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
|
|
|
|
// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
|
|
|
|
while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
|
2013-11-01 06:11:26 +01:00
|
|
|
}
|
|
|
|
|
2018-11-26 08:56:07 +01:00
|
|
|
dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
|
|
|
|
dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2013-10-29 08:19:56 +01:00
|
|
|
//------------- Prepare qtd -------------//
|
|
|
|
qtd_init(p_qtd, buffer, total_bytes);
|
2018-11-22 15:37:23 +01:00
|
|
|
p_qtd->int_on_complete = true;
|
|
|
|
p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
|
2013-11-01 06:11:26 +01:00
|
|
|
|
2018-11-22 15:37:23 +01:00
|
|
|
// start transfer
|
2018-11-23 09:22:46 +01:00
|
|
|
LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
|
2013-10-29 08:19:56 +01:00
|
|
|
|
2018-11-23 09:22:46 +01:00
|
|
|
return true;
|
2013-10-29 08:19:56 +01:00
|
|
|
}
|
|
|
|
|
2018-11-22 11:40:20 +01:00
|
|
|
|
2018-11-22 11:21:07 +01:00
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
// ISR
|
|
|
|
//--------------------------------------------------------------------+
|
2018-03-23 06:17:47 +01:00
|
|
|
void hal_dcd_isr(uint8_t rhport)
|
2013-10-29 05:27:25 +01:00
|
|
|
{
|
2018-03-23 06:17:47 +01:00
|
|
|
LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
|
2013-11-06 08:20:45 +01:00
|
|
|
|
2014-03-23 11:33:58 +01:00
|
|
|
uint32_t const int_enable = lpc_usb->USBINTR_D;
|
|
|
|
uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
|
|
|
|
lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
|
|
|
|
|
|
|
|
if (int_status == 0) return;// disabled interrupt sources
|
|
|
|
|
2018-10-23 11:07:48 +02:00
|
|
|
|
2014-03-23 11:33:58 +01:00
|
|
|
if (int_status & INT_MASK_RESET)
|
|
|
|
{
|
2018-03-23 06:17:47 +01:00
|
|
|
bus_reset(rhport);
|
2018-10-23 11:07:48 +02:00
|
|
|
|
2018-10-23 19:44:26 +02:00
|
|
|
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
|
2018-10-23 11:07:48 +02:00
|
|
|
dcd_event_handler(&event, true);
|
2014-03-23 11:33:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (int_status & INT_MASK_SUSPEND)
|
|
|
|
{
|
|
|
|
if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
|
|
|
|
{ // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
|
|
|
if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
|
|
|
|
{
|
2018-10-23 19:44:26 +02:00
|
|
|
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPENDED };
|
2018-10-23 11:07:48 +02:00
|
|
|
dcd_event_handler(&event, true);
|
2014-03-23 11:33:58 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// TODO disconnection does not generate interrupt !!!!!!
|
2013-11-22 10:10:05 +01:00
|
|
|
// if (int_status & INT_MASK_PORT_CHANGE)
|
2013-11-22 09:16:24 +01:00
|
|
|
// {
|
2013-11-22 10:10:05 +01:00
|
|
|
// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
|
2013-11-22 09:16:24 +01:00
|
|
|
// {
|
2018-10-23 19:44:26 +02:00
|
|
|
// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
|
2018-10-23 11:07:48 +02:00
|
|
|
// dcd_event_handler(&event, true);
|
2013-11-22 09:16:24 +01:00
|
|
|
// }
|
|
|
|
// }
|
|
|
|
|
2014-03-23 11:33:58 +01:00
|
|
|
if (int_status & INT_MASK_USB)
|
|
|
|
{
|
|
|
|
uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
|
|
|
|
lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
|
|
|
|
|
2018-03-23 06:17:47 +01:00
|
|
|
dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
|
2014-03-23 11:33:58 +01:00
|
|
|
|
|
|
|
if (lpc_usb->ENDPTSETUPSTAT)
|
2018-03-21 09:32:35 +01:00
|
|
|
{
|
2018-11-22 15:37:23 +01:00
|
|
|
//------------- Set up Received -------------//
|
2018-03-21 09:32:35 +01:00
|
|
|
// 23.10.10.2 Operational model for setup transfers
|
2014-03-23 11:33:58 +01:00
|
|
|
lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
|
|
|
|
|
2018-10-23 19:44:26 +02:00
|
|
|
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
|
2018-10-23 11:07:48 +02:00
|
|
|
event.setup_received = p_dcd->qhd[0].setup_request;
|
|
|
|
|
|
|
|
dcd_event_handler(&event, true);
|
2014-03-23 11:33:58 +01:00
|
|
|
}
|
2018-03-30 13:36:04 +02:00
|
|
|
|
2018-11-22 15:37:23 +01:00
|
|
|
if ( edpt_complete )
|
2014-04-04 07:22:33 +02:00
|
|
|
{
|
2018-11-22 15:37:23 +01:00
|
|
|
for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
|
2018-03-30 13:36:04 +02:00
|
|
|
{
|
2018-11-22 15:58:06 +01:00
|
|
|
if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
|
2018-11-22 15:37:23 +01:00
|
|
|
{
|
|
|
|
// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
|
|
|
|
dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
|
|
|
|
dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
|
2018-03-30 13:36:04 +02:00
|
|
|
|
2018-11-23 09:22:46 +01:00
|
|
|
uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
|
|
|
|
( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
|
2013-10-29 05:27:25 +01:00
|
|
|
|
2018-11-22 15:58:06 +01:00
|
|
|
uint8_t ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
|
2018-11-22 15:37:23 +01:00
|
|
|
dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
|
|
|
|
}
|
|
|
|
}
|
2014-03-23 11:33:58 +01:00
|
|
|
}
|
|
|
|
}
|
2013-10-29 05:27:25 +01:00
|
|
|
|
2018-03-08 08:38:06 +01:00
|
|
|
if (int_status & INT_MASK_SOF)
|
|
|
|
{
|
2018-10-23 19:44:26 +02:00
|
|
|
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
|
2018-10-23 11:07:48 +02:00
|
|
|
dcd_event_handler(&event, true);
|
2018-03-08 08:38:06 +01:00
|
|
|
}
|
|
|
|
|
2014-03-23 11:33:58 +01:00
|
|
|
if (int_status & INT_MASK_NAK) {}
|
2018-03-28 09:49:00 +02:00
|
|
|
if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
|
2013-10-29 05:27:25 +01:00
|
|
|
}
|
2013-10-29 08:19:56 +01:00
|
|
|
|
2013-10-29 05:27:25 +01:00
|
|
|
#endif
|