clean up dcd lpc43xx
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hathach
parent
569e85a0c0
commit
a1faf5c9cb
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@ -239,7 +239,7 @@ static inline uint8_t qtd_find_free(uint8_t rhport)
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//--------------------------------------------------------------------+
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// DCD Endpoint Port
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//--------------------------------------------------------------------+
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static inline volatile uint32_t * get_reg_control_addr(uint8_t rhport, uint8_t physical_endpoint)
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static inline volatile uint32_t * get_endpt_ctrl_reg(uint8_t rhport, uint8_t physical_endpoint)
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{
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return &(LPC_USB[rhport]->ENDPTCTRL0) + edpt_phy2log(physical_endpoint);
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}
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@ -247,7 +247,7 @@ static inline volatile uint32_t * get_reg_control_addr(uint8_t rhport, uint8_t p
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
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volatile uint32_t * reg_control = get_endpt_ctrl_reg(rhport, ep_idx);
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if ( ep_addr == 0)
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{
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@ -267,7 +267,7 @@ bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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volatile uint32_t * reg_control = get_reg_control_addr(rhport, edpt_addr2phy(ep_addr));
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volatile uint32_t * reg_control = get_endpt_ctrl_reg(rhport, edpt_addr2phy(ep_addr));
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// data toggle also need to be reset
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(*reg_control) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
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@ -280,12 +280,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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// TODO not support ISO yet
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TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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tusb_dir_t dir = (p_endpoint_desc->bEndpointAddress & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
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uint8_t const dir = edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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//------------- Prepare Queue Head -------------//
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uint8_t ep_idx = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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p_qhd->zero_length_termination = 1;
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@ -293,101 +293,52 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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//------------- Endpoint Control Register -------------//
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volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
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volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
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// endpoint must not be already enabled
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TU_VERIFY( !( (*reg_control) & (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
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TU_VERIFY( !( (*endpt_ctrl) & (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
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(*reg_control) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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(*endpt_ctrl) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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uint8_t const ep_idx = 2*epnum + dir;
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dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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return p_qhd->list_qtd_idx[0] != 0; // qtd list is not empty
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return p_qtd->active;
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// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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}
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// control transfer does not need to use qtd find function
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
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dcd_qhd_t* qhd = &p_dcd->qhd[ep_phy];
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
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TU_VERIFY( !qhd->qtd_overlay.active );
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dcd_qtd_t* qtd = &p_dcd->qtd[0];
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qtd_init(qtd, p_buffer, length);
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// skip xfer complete for Status
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qtd->int_on_complete = (length > 0 ? 1 : 0);
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qhd->qtd_overlay.next = (uint32_t) qtd;
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lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_phy));
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return true;
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}
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// add only, controller virtually cannot know
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// TODO remove and merge to dcd_edpt_xfer
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static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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uint8_t qtd_idx = qtd_find_free(rhport);
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TU_ASSERT(qtd_idx != 0);
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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dcd_qhd_t * p_qhd = &p_dcd->qhd[ed_idx];
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dcd_qtd_t * p_qtd = &p_dcd->qtd[qtd_idx];
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//------------- Find free slot in qhd's array list -------------//
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uint8_t free_slot;
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for(free_slot=0; free_slot < DCD_QTD_PER_QHD_MAX; free_slot++)
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{
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if ( p_qhd->list_qtd_idx[free_slot] == 0 ) break; // found free slot
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}
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TU_ASSERT(free_slot < DCD_QTD_PER_QHD_MAX);
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p_qhd->list_qtd_idx[free_slot] = qtd_idx; // add new qtd to qhd's array list
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = int_on_complete;
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if ( free_slot > 0 ) p_dcd->qtd[ p_qhd->list_qtd_idx[free_slot-1] ].next = (uint32_t) p_qtd;
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return true;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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if ( edpt_number(ep_addr) == 0 )
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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uint8_t const ep_idx = 2*epnum + dir;
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if ( epnum == 0 )
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{
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return dcd_control_xfer(rhport, edpt_dir(ep_addr), buffer, total_bytes);
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
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}
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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dcd_qhd_t * p_qhd = &p_dcd->qhd[ep_idx];
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dcd_qtd_t * p_qtd = &p_dcd->qtd[ep_idx];
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TU_VERIFY ( pipe_add_xfer(rhport, ep_idx, buffer, total_bytes, true) );
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dcd_qhd_t* p_qhd = &dcd_data_ptr[rhport]->qhd[ ep_idx ];
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dcd_qtd_t* p_qtd = &dcd_data_ptr[rhport]->qtd[ p_qhd->list_qtd_idx[0] ];
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // attach head QTD to QHD start transferring
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = true;
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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// start transfer
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LPC_USB[rhport]->ENDPTPRIME = BIT_( edpt_phy2pos(ep_idx) ) ;
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return true;
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@ -397,39 +348,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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//--------------------------------------------------------------------+
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// ISR
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//--------------------------------------------------------------------+
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void xfer_complete_isr(uint8_t rhport, uint32_t reg_complete)
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{
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for(uint8_t ep_idx = 2; ep_idx < DCD_QHD_MAX; ep_idx++)
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{
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if ( BIT_TEST_(reg_complete, edpt_phy2pos(ep_idx)) )
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{ // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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// retire all QTDs in array list, up to 1st still-active QTD
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while( p_qhd->list_qtd_idx[0] != 0 )
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{
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dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ p_qhd->list_qtd_idx[0] ];
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if (p_qtd->active) break; // stop immediately if found still-active QTD and shift array list
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//------------- Free QTD and shift array list -------------//
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p_qtd->used = 0; // free QTD
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memmove( (void*) p_qhd->list_qtd_idx, (void*) (p_qhd->list_qtd_idx+1), DCD_QTD_PER_QHD_MAX-1);
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p_qhd->list_qtd_idx[DCD_QTD_PER_QHD_MAX-1]=0;
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if (p_qtd->int_on_complete)
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{
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uint8_t result = p_qtd->halted ? DCD_XFER_STALLED :
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( p_qtd->xact_err ||p_qtd->buffer_err ) ? DCD_XFER_FAILED : DCD_XFER_SUCCESS;
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uint8_t ep_addr = edpt_phy2addr(ep_idx);
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dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
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}
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}
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}
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}
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}
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void hal_dcd_isr(uint8_t rhport)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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@ -478,9 +396,9 @@ void hal_dcd_isr(uint8_t rhport)
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dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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//------------- Set up Received -------------//
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if (lpc_usb->ENDPTSETUPSTAT)
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{
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//------------- Set up Received -------------//
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// 23.10.10.2 Operational model for setup transfers
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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@ -490,29 +408,24 @@ void hal_dcd_isr(uint8_t rhport)
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dcd_event_handler(&event, true);
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}
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//------------- Control Request Completed -------------//
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else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
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if ( edpt_complete )
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{
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// determine Control OUT or IN
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uint8_t ep_idx = BIT_TEST_(edpt_complete, 0) ? 0 : 1;
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// TODO use the actual QTD instead of the qhd's overlay to get expected bytes for actual byte xferred
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dcd_qtd_t* const p_qtd = (dcd_qtd_t*) p_dcd->qhd[ep_idx].qtd_addr;
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if ( p_qtd->int_on_complete )
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for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
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{
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uint8_t result = p_qtd->halted ? DCD_XFER_STALLED :
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( p_qtd->xact_err ||p_qtd->buffer_err ) ? DCD_XFER_FAILED : DCD_XFER_SUCCESS;
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if ( BIT_TEST_(edpt_complete, edpt_phy2pos(ep_idx)) )
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{
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// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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dcd_event_xfer_complete(rhport, 0, p_qtd->expected_bytes - p_qtd->total_bytes, result, true);
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uint8_t result = p_qtd->halted ? DCD_XFER_STALLED :
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( p_qtd->xact_err ||p_qtd->buffer_err ) ? DCD_XFER_FAILED : DCD_XFER_SUCCESS;
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uint8_t ep_addr = edpt_phy2addr(ep_idx);
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dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
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}
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}
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}
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//------------- Transfer Complete -------------//
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if ( edpt_complete & ~(BIT_(0) | BIT_(16)) )
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{
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xfer_complete_isr(rhport, edpt_complete);
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}
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}
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if (int_status & INT_MASK_SOF)
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