USBCMD_ADD_QTD_TRIPWIRE=TU_BIT(14)///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
// Interrupt Threshold bit 23:16
};
// PORTSC1
#define PORTSC1_PORT_SPEED_POS 26
enum{
PORTSC1_CURRENT_CONNECT_STATUS=TU_BIT(0),
PORTSC1_FORCE_PORT_RESUME=TU_BIT(6),
PORTSC1_SUSPEND=TU_BIT(7),
PORTSC1_FORCE_FULL_SPEED=TU_BIT(24),
PORTSC1_PORT_SPEED=TU_BIT(26)|TU_BIT(27)
};
// OTGSC
enum{
OTGSC_VBUS_DISCHARGE=TU_BIT(0),
OTGSC_VBUS_CHARGE=TU_BIT(1),
// OTGSC_HWASSIST_AUTORESET = TU_BIT(2),
OTGSC_OTG_TERMINATION=TU_BIT(3),///< Must set to 1 when OTG go to device mode
OTGSC_DATA_PULSING=TU_BIT(4),
OTGSC_ID_PULLUP=TU_BIT(5),
// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6),
// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7),
OTGSC_ID=TU_BIT(8),///< 0 = A device, 1 = B Device
OTGSC_A_VBUS_VALID=TU_BIT(9),
OTGSC_A_SESSION_VALID=TU_BIT(10),
OTGSC_B_SESSION_VALID=TU_BIT(11),
OTGSC_B_SESSION_END=TU_BIT(12),
OTGSC_1MS_TOGGLE=TU_BIT(13),
OTGSC_DATA_BUS_PULSING_STATUS=TU_BIT(14),
};
// USBMode
enum{
USBMODE_CM_DEVICE=2,
USBMODE_CM_HOST=3,
USBMODE_SLOM=TU_BIT(3),
USBMODE_SDIS=TU_BIT(4),
USBMODE_VBUS_POWER_SELECT=TU_BIT(5),// Need to be enabled for LPC18XX/43XX in host mode
};
// Device Registers
typedefstruct
{
//------------- ID + HW Parameter Registers-------------//