more ci abstract
This commit is contained in:
hathach
parent
0612433eef
commit
61a9e125db
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@ -28,7 +28,9 @@ LDFLAGS += \
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-Wl,--defsym,__stack_size__=0x800 \
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SRC_C += \
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src/portable/nxp/transdimension/dcd_transdimension.c \
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src/portable/chipidea/ci_hs/dcd_ci_hs.c \
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src/portable/chipidea/ci_hs/hcd_ci_hs.c \
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src/portable/ehci/ehci.c \
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$(MCU_DIR)/system_$(MCU_VARIANT).c \
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$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
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$(MCU_DIR)/project_template/clock_config.c \
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@ -0,0 +1,61 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _CI_HS_IMXRT_H_
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#define _CI_HS_IMXRT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "fsl_device_registers.h"
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static const dcd_controller_t _dcd_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .regs = (ci_hs_regs_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
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#else
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{ .regs = (ci_hs_regs_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
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{ .regs = (ci_hs_regs_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
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#endif
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};
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,57 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _CI_HS_LPC18_43_H_
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#define _CI_HS_LPC18_43_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (ci_hs_regs_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
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{ .regs = (ci_hs_regs_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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};
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -85,49 +85,57 @@ enum {
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typedef struct
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{
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//------------- ID + HW Parameter Registers-------------//
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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volatile uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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volatile uint8_t CAPLENGTH; ///< Capability Registers Length
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volatile uint8_t TU_RESERVED[1];
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volatile uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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volatile uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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volatile uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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volatile uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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volatile uint16_t DCIVERSION; ///< Device Controller Interface Version
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volatile uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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volatile uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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volatile uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t, hcd_registers_t;
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volatile uint32_t USBCMD; ///< USB Command Register
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volatile uint32_t USBSTS; ///< USB Status Register
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volatile uint32_t USBINTR; ///< Interrupt Enable Register
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volatile uint32_t FRINDEX; ///< USB Frame Index
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volatile uint32_t TU_RESERVED;
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volatile uint32_t DEVICEADDR; ///< Device Address
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volatile uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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volatile uint32_t TU_RESERVED;
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volatile uint32_t BURSTSIZE; ///< Programmable Burst Size
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volatile uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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volatile uint32_t ENDPTNAK; ///< Endpoint NAK
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volatile uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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volatile uint32_t TU_RESERVED;
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volatile uint32_t PORTSC1; ///< Port Status & Control
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volatile uint32_t TU_RESERVED[7];
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volatile uint32_t OTGSC; ///< On-The-Go Status & control
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volatile uint32_t USBMODE; ///< USB Device Mode
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volatile uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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volatile uint32_t ENDPTPRIME; ///< Endpoint Prime
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volatile uint32_t ENDPTFLUSH; ///< Endpoint Flush
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volatile uint32_t ENDPTSTAT; ///< Endpoint Status
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volatile uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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volatile uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} ci_hs_regs_t, hcd_registers_t;
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typedef struct
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{
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ci_hs_regs_t* regs;
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const uint32_t irqnum;
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const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_controller_t;
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#ifdef __cplusplus
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}
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@ -25,25 +25,24 @@
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*/
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#include "tusb_option.h"
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#include "device/dcd_attr.h"
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#if TUSB_OPT_DEVICE_ENABLED && \
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(CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
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#if TUSB_OPT_DEVICE_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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#define INCLUDE_FSL_DEVICE_REGISTERS
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#else
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#endif
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#include "common/tusb_common.h"
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#include "device/dcd.h"
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#include "ci_hs_type.h"
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "ci_hs_imxrt.h"
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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#include "ci_hs_lpc18_43.h"
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#else
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#error "Unsupported MCUs"
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#endif
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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@ -144,33 +143,6 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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// Variables
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//--------------------------------------------------------------------+
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_controller_t;
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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static const dcd_controller_t _dcd_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
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#else
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{ .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
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{ .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
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#endif
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};
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#else
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
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{ .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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};
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#endif
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#define QTD_NEXT_INVALID 0x01
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typedef struct {
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@ -191,7 +163,7 @@ static dcd_data_t _dcd_data;
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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@ -231,7 +203,7 @@ void dcd_init(uint8_t rhport)
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{
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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// Reset controller
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dcd_reg->USBCMD |= USBCMD_RESET;
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@ -255,40 +227,30 @@ void dcd_init(uint8_t rhport)
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dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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}
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_remote_wakeup(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
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}
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void dcd_connect(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->USBCMD |= USBCMD_RUN_STOP;
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}
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void dcd_disconnect(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
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}
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@ -334,7 +296,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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// flush to abort any primed buffer
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@ -347,7 +309,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// data toggle also need to be reset
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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}
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@ -376,7 +338,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
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@ -393,7 +355,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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void dcd_edpt_close_all (uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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// Disable all non-control endpoints
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for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
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@ -411,7 +373,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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||||
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||||
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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||||
ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
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||||
_dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
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@ -426,7 +388,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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|
||||
static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
|
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{
|
||||
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
|
||||
dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
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||||
|
||||
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|
@ -542,7 +504,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
|
|||
|
||||
if ( result != XFER_RESULT_SUCCESS )
|
||||
{
|
||||
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
// flush to abort error buffer
|
||||
dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
|
||||
}
|
||||
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|
@ -566,7 +528,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
|
|||
|
||||
void dcd_int_handler(uint8_t rhport)
|
||||
{
|
||||
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
|
||||
uint32_t const int_enable = dcd_reg->USBINTR;
|
||||
uint32_t const int_status = dcd_reg->USBSTS & int_enable;
|
||||
|
|
|
|||
Loading…
Reference in New Issue