template and source for hardware projects
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King Kévin bbd69a3784 brd: complete first routing 2023-02-06 07:03:39 +01:00
kicad lib: add test point 2023-02-06 07:03:16 +01:00
library@0028ca2570 lib: update repo 2022-12-24 03:08:33 +01:00
.gitignore rake: add panelization target 2022-06-10 19:32:19 +02:00
.gitmodules update library 2022-03-07 14:42:51 +01:00
.qeda.yaml lib: add test point 2023-02-06 07:03:16 +01:00
CHANGELOG.md doc: add empty changelog file 2022-06-10 19:14:56 +02:00
DEVELOPMENT.md doc: replace rake with make 2022-08-10 12:37:46 +02:00
JLCPCB_CORRECTION.csv lib: add JLCPCB corrections for USB connectors 2022-12-24 03:05:45 +01:00
LICENSE.txt add CERN-OHL-S license 2021-07-22 12:22:58 +02:00
Makefile set project name 2023-02-02 06:36:09 +01:00
README.md README: development moved to other file 2022-03-23 10:49:07 +01:00
bom.ini rake: use custom bom generator configuration 2022-06-10 19:32:19 +02:00
fp-lib-table lib: add logos 2023-02-05 01:33:30 +01:00
refdes2fab.py add script to put refdes in fab layer 2022-09-13 12:14:21 +02:00
rsim.kicad_pcb brd: complete first routing 2023-02-06 07:03:39 +01:00
rsim.kicad_pro brd: complete first routing 2023-02-06 07:03:39 +01:00
rsim.kicad_sch sch: rename EN and RST 2023-02-05 01:55:42 +01:00
rsim_esp32s2.kicad_sch sch: optimise for routing 2023-02-06 07:02:23 +01:00
rsim_esp32s3.kicad_sch sch: optimise for routing 2023-02-06 07:02:23 +01:00
rsim_power.kicad_sch sch: add SIM_VCC 2023-02-05 01:51:05 +01:00
rsim_serial.kicad_sch sch: optimise for routing 2023-02-06 07:02:23 +01:00
rsim_sim.kicad_sch sch: optimise for routing 2023-02-06 07:02:23 +01:00
sym-lib-table lib: add partdb library 2023-02-03 11:06:43 +01:00
version add output generation script 2021-07-22 12:34:35 +02:00

README.md

these are the hardware design files for insert project name here.

purpose

usage