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usb_bug_de
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546ab7fafd |
@ -7,3 +7,11 @@ config:
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preferManufacturer: false
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smoothPadCorners: false
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library:
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- resistor/r0603
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- capacitor/c0603
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- diode/led0603
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- ic/nor-gate_ti_sn74hc02@soic
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- ic/nor-gate_ti_sn74lvc1g02@dbv
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- ic/nor-gate_ti_sn74lvc1g02@dck
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- mechanical/smd-button_hyp_1ts002e
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- connector/usb-a-2.0-receptacle
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12
CHANGELOG.md
Normal file
12
CHANGELOG.md
Normal file
@ -0,0 +1,12 @@
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v1
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==
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uses smaller coin cell (CR1220).
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use only one type of NOR-gate.
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remove READY LED.
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v0
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==
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||||
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working proof of concept prototype.
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it allows populating NOR gates in different packages.
|
1
DEVELOPMENT.md
Normal file
1
DEVELOPMENT.md
Normal file
@ -0,0 +1 @@
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the JSON files are the source schematic and board layout made using [EasyEDA](https://easyeda.com/).
|
119
README.md
119
README.md
@ -1,96 +1,51 @@
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these are the hardware design files for **insert project name here**.
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The USB bug detector identifies USB type-A cables (or devices) with integrated circuits.
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purpose
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=======
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<img src="picture/v1_front.webp" title="front" height="250"/>
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<img src="picture/v1_back.webp" title="back" height="250"/>
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usage
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=====
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requirements
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============
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To use the USB bug detector, follow the steps provided on the back of the board:
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to be able to generate the outputs you need following software:
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- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
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- [QEDA](http://qeda.org/): to generate footprints for the parts
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- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture
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- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout
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the output generation is automatized.
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- insert a CR1220 coin cell battery in the USB bug detector for it to be operational
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- press on the RESET button to arm the test
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- the BUGGED LED should be off
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- plug the USB cable in the USB receptacle
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- if the BUGGED LED switches on, the USB cable embeds an integrated circuit (e.g. a bug)
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- if the BUGGED LED remains off, the cable is same to use
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schematic
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=========
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After the test, to save power, press again on the RESET button.
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library
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-------
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To ensure that the USB bug detector works, after pressing on the RESET button, press on the SIMULATE button.
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This will simulate a USB plug with integrated circuit.
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The BUGGED LED should switch on.
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This also ensures the battery is not empty.
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almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
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the `library` folder contains the QEDA parts definitions.
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When the LED is on, the USB bug detector draws 3 mA.
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When the LED is off, the USB bug detector draws 64 nA.
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This results in a idle battery life of 62 years (for a typical 35 mAh CR1220 battery).
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This is on par with the self life of the battery (~ 1%/year).
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to install QEDA using NPM from the official repository:
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~~~
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sudo npm install -g qeda
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~~~
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mode of operation
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=================
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to install QEDA from the sources:
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~~~
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git clone https://github.com/qeda/qeda
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cd qeda
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npm install
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sudo npm install --global
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~~~
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An NOR-gate-based SR-latch is used.
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The RESET button triggers the R signal to reset the latch.
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When a USB cable is plugged, power is provided by the battery to the cable.
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If an integrated circuits is present, current will flow through.
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A 1 kOhm resistor on the low side (e.g. ground) will create a voltage.
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If the plug draws more than 1.6 mA, the resulting 1.6 V will trigger the S signal to set the latch.
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The BUG LED will indicate when the SR-latch is set.
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The latch remains set until the RESET button is present.
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Thus, even if the plug stops drawing power, the LED remains on.
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to generate the parts:
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~~~
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rake library
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~~~
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This minimum 1.6 mA current draw is often caused by the decoupling/bypass capacitor required by integrated circuit, or accompanying voltage regulator.
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When charging, the capacitor acts as a short for a small time, allowing current to flow.
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On USB plugs with just resistors, or LEDs, the resulting current flow is not large enough.
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this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder.
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only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes.
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all other parts are custom and written for this project.
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schematic
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---------
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the `.sch` file is the schematic source file.
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it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda).
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it uses standard symbols, and the ones in the `geda/symbols/` folder.
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most symbols are generated by QEDA as described above.
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to export the netlist (in tEDAx format):
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~~~
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rake netlist
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~~~
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to export as pdf:
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~~~
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rake print
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~~~
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BOM
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---
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to export the bill of material (as CSV):
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~~~
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rake bom
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~~~
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board
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=====
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the `.lht` file is the board layout source file.
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it has been drawn using [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/).
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it uses the symbols from the `coraleda/subc/` folder.
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most symbols are generated by QEDA as described above.
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`oshw_logo.lht` is just the Open Source Hardware Logo.
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it been generated from https://oshwlogo.cuvoodoo.info/.
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to export gerber files for PCB manufacturer (and photo preview + overview document):
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~~~
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rake fabrication
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~~~
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fabrication
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===========
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The SIMULATE circuit simulates an integrated circuit by putting a 100 nF capacitor across the USB receptacle.
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Because of the 1 kOhm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug.
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This is often not enough to power up integrated circuit properly, particularly if they use a radio interface.
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Thus it is safe to use the USB bug detector on bugs, without activating it.
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|
181
Rakefile
181
Rakefile
@ -1,181 +0,0 @@
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# encoding: utf-8
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# ruby: 2.1.0
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=begin
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Rakefile to manage hardware projects
|
||||
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uses Lepton EDA for schematic and pcb-rnd for board layouts.
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Rakefile instead of Makefile for better text file parsing capabilities.
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=end
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require 'rake/clean'
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require 'csv' # to export BOM and costs
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# =================
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# project variables
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# =================
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# common name used for file names
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name = "template"
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# project version, read from "version" file
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raise "define project version in 'version' file" unless File.exist? "version"
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version = IO.read("version").split("\n")[0]
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# current date for stamping output
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date = Time.now.strftime("%Y-%m-%d")
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# revision based on number of changes on schematic or board layout and current git commit
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changes = `git log --pretty=oneline "#{name}.sch" "#{name}.lht" | wc -l`.chomp.to_i
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commit = `git rev-parse --short HEAD`.chomp
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revision = "#{changes} (#{commit})"
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# path to qeda"
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qeda = "qeda"
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# ==========
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# main tasks
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# ==========
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||||
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desc "main building task"
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task :default => [:print, :fabrication, :bom]
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desc "print schematic and layout (as pdf)"
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prints = [ "#{name}.sch.pdf", "#{name}.brd.pdf", "#{name}.brd-top.svg", "#{name}.brd-bottom.svg" ]
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task :print => prints
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CLEAN.include([ "#{name}.versioned.sch", "#{name}.versioned.lht" ])
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CLOBBER.include(prints)
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desc "generate fabrication gerbers (as archive)"
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gerbers = [ "#{name}.brd.asb", "#{name}.brd.ast", "#{name}.brd.gbl", "#{name}.brd.gbo", "#{name}.brd.gbp", "#{name}.brd.gbs", "#{name}.brd.gko", "#{name}.brd.gtl", "#{name}.brd.gto", "#{name}.brd.gtp", "#{name}.brd.gts", "#{name}.brd.xln", "#{name}.brd.g2l", "#{name}.brd.g3l" ]
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fab = [ "#{name}.brd.zip" ]
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task :fabrication => fab
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CLEAN.include(gerbers)
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CLOBBER.include(fab)
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desc "generate symbols and footprints from parts"
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task :library do
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sh "#{qeda} config output geda"
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sh "#{qeda} generate ."
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sh "#{qeda} config output coraleda"
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sh "#{qeda} generate ."
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end
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desc "export netlist from schematic"
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net = [ "#{name}.tdx" ]
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task :netlist => net
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CLOBBER.include(net)
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desc "export notes from schematic"
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notes = [ "#{name}.notes.txt" ]
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task :notes => notes
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CLOBBER.include(notes)
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desc "export BOMs from schematic"
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boms = [ "#{name}.bom.csv" ]
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task :bom => boms
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CLOBBER.include(boms)
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# ===============
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# file generation
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||||
# ===============
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||||
|
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desc "generate schematic with version information all symbols embedded"
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rule ".versioned.sch" => ".sch" do |t|
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sh "cp #{t.source} #{t.name}"
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sh "lepton-embed --embed #{t.name} 2> /dev/null"
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sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
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sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
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sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
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end
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desc "generate board layout with version information"
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rule ".versioned.lht" => ".lht" do |t|
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sh "cp #{t.source} #{t.name}"
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sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
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||||
sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
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||||
sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
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||||
end
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||||
|
||||
desc "generate printable version (PDF) of schematic"
|
||||
rule ".sch.pdf" => ".versioned.sch" do |t|
|
||||
sh "lepton-cli export --color --paper iso_a4 --layout landscape --output #{t.name} #{t.source} 2> /dev/null"
|
||||
end
|
||||
|
||||
desc "generate printable version (PostScript) of board layout"
|
||||
rule ".brd.ps" => ".versioned.lht" do |t|
|
||||
sh "pcb-rnd -x ps --ps-color --media A4 --psfile #{t.name} #{t.source} 2> /dev/null"
|
||||
end
|
||||
|
||||
desc "generate printable version (PDF) of board layout"
|
||||
rule ".brd.pdf" => ".brd.ps" do |t|
|
||||
sh "ps2pdf -sPAPERSIZE=a4 -dEPSCrop #{t.source} #{t.name}"
|
||||
end
|
||||
|
||||
desc "generate photo realistic picture from layout (top side)"
|
||||
rule ".brd-top.svg" => ".versioned.lht" do |t|
|
||||
sh "pcb-rnd -x svg --photo-mode --outfile #{t.name} #{t.source} 2> /dev/null"
|
||||
end
|
||||
|
||||
desc "generate photo realistic picture from layout (bottom side)"
|
||||
rule ".brd-bottom.svg" => ".versioned.lht" do |t|
|
||||
sh "pcb-rnd -x svg --photo-mode --flip --outfile #{t.name} #{t.source} 2> /dev/null"
|
||||
end
|
||||
|
||||
desc "archive gerbers"
|
||||
rule ".brd.zip" => ".versioned.lht" do |t|
|
||||
base = File.basename(t.source, ".versioned.lht")
|
||||
puts base
|
||||
sh "pcb-rnd -x cam gerber:JLC_PCB --outfile #{base}.brd #{t.source} 2> /dev/null"
|
||||
sh "zip --quiet #{t.name} #{base}.brd.xln #{base}.brd.a* #{base}.brd.g*"
|
||||
end
|
||||
|
||||
desc "export netlist from schematic"
|
||||
rule ".tdx" => ".sch" do |t|
|
||||
sh "lepton-netlist -g tEDAx -o #{t.name} #{t.source} 2> /dev/null"
|
||||
end
|
||||
|
||||
desc "generate BOM file from schematic"
|
||||
rule ".bom.csv" => ".sch" do |t|
|
||||
attributes = ["device", "value", "description", "footprint", "manufacturer", "mpn", "datasheet", "lcsc-sku", "digikey-sku", "aliexpress-sku"]
|
||||
bom_data = bom2(t.prerequisites[0],attributes)
|
||||
CSV.open(t.name, "wb") do |csv|
|
||||
all_attributes = ["refdes","qty"]+attributes
|
||||
csv << all_attributes
|
||||
bom_data.each do |line|
|
||||
csv << all_attributes.collect{|attribute| line[attribute]}
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
# ================
|
||||
# helper functions
|
||||
# ================
|
||||
|
||||
# generate gnetlist bom2 and parse them
|
||||
# arguments: schematic=schematic to use, attributes=attributes to use for generating bom2
|
||||
# returns an array of hash. key is the attribute name, value is the attribute value
|
||||
def bom2(schematic, attributes)
|
||||
to_return = []
|
||||
# force attributes to be an array
|
||||
attributes = case attributes
|
||||
when String
|
||||
[attributes]
|
||||
when Array
|
||||
attributes
|
||||
else
|
||||
[attributes.to_s]
|
||||
end
|
||||
# generate bom2
|
||||
list = `lepton-netlist --backend bom2 --backend-option attribs=#{attributes*','} --quiet --output - #{schematic} 2> /dev/null`
|
||||
list = list.each_line {|l| '"' + l + '"' + '\n' }
|
||||
list.gsub!(/^(.+)/, '"\1')
|
||||
list.gsub!(/(.+)$/, '\1"')
|
||||
list.gsub!(/(?!http):(?!\/\/)/, '\1":"\2') # protect the values between ':' (such as URLs)
|
||||
# parse bom2
|
||||
csv = CSV.parse(list, col_sep: ":", quote_char: '"')
|
||||
csv[1..-1].each do |row|
|
||||
line = {}
|
||||
row.each_index do |col|
|
||||
line[csv[0][col]] = row[col] unless row[col] == "unknown"
|
||||
end
|
||||
to_return << line
|
||||
end
|
||||
return to_return
|
||||
end
|
||||
|
@ -1,421 +0,0 @@
|
||||
# footprint generated from CuVoodoo Land Pattern
|
||||
# author: King Kévin
|
||||
# version: 1
|
||||
# date: 2019-05-13
|
||||
li:pcb-rnd-subcircuit-v6 {
|
||||
ha:subc.1 {
|
||||
uid = any_24_ASCII_characters_
|
||||
ha:attributes {
|
||||
footprint = open source hardware logo
|
||||
}
|
||||
ha:data {
|
||||
li:padstack_prototypes {
|
||||
}
|
||||
li:objects {
|
||||
}
|
||||
li:layers {
|
||||
ha:top-silkscreen {
|
||||
lid = 1
|
||||
ha:type {
|
||||
top = 1
|
||||
silk = 1
|
||||
}
|
||||
li:objects {
|
||||
ha:line.2{
|
||||
clearance = 0
|
||||
x1 = 0.15mm
|
||||
y1 = 1.8mm
|
||||
x2 = 0.75mm
|
||||
y2 = 1.8mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.3{
|
||||
clearance = 0
|
||||
x1 = 1.8mm
|
||||
y1 = 5.8500000000000005mm
|
||||
x2 = 1.8mm
|
||||
y2 = 6.45mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.4{
|
||||
clearance = 0
|
||||
x1 = 5.8500000000000005mm
|
||||
y1 = 1.8mm
|
||||
x2 = 6.45mm
|
||||
y2 = 1.8mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.5{
|
||||
clearance = 0
|
||||
x1 = 1.8mm
|
||||
y1 = 0.15mm
|
||||
x2 = 1.8mm
|
||||
y2 = 0.75mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.6{
|
||||
clearance = 0
|
||||
x1 = 0.15mm
|
||||
y1 = 2.4mm
|
||||
x2 = 0.75mm
|
||||
y2 = 2.4mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.7{
|
||||
clearance = 0
|
||||
x1 = 2.4mm
|
||||
y1 = 5.8500000000000005mm
|
||||
x2 = 2.4mm
|
||||
y2 = 6.45mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.8{
|
||||
clearance = 0
|
||||
x1 = 5.8500000000000005mm
|
||||
y1 = 2.4mm
|
||||
x2 = 6.45mm
|
||||
y2 = 2.4mm
|
||||
thickness = 0.3mm
|
||||
}
|
||||
ha:line.9{
|
||||
clearance = 0
|
||||
x1 = 2.4mm
|
||||
y1 = 0.15mm
|
||||
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ha:line.28{
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ha:line.36{
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ha:line.42{
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ha:line.43{
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ha:line.45{
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ha:line.46{
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ha:line.47{
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ha:line.48{
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ha:line.49{
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x1 = 4.799999999999999mm
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BIN
picture/v0_back.webp
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BIN
picture/v0_front.webp
Normal file
BIN
picture/v0_front.webp
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BIN
picture/v1_back.webp
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BIN
picture/v1_back.webp
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BIN
picture/v1_front.webp
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BIN
picture/v1_front.webp
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After Width: | Height: | Size: 440 KiB |
587
template.lht
587
template.lht
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|
||||
clearance = 12.0mil
|
||||
}
|
||||
}
|
||||
|
||||
ha:meta {
|
||||
ha:size {
|
||||
thermal_scale = 0.500000
|
||||
x = 100.0mm
|
||||
y = 100.0mm
|
||||
}
|
||||
ha:grid {
|
||||
spacing = 0.5mm
|
||||
offs_x = 0.0
|
||||
offs_y = 0.0
|
||||
}
|
||||
}
|
||||
|
||||
ha:data {
|
||||
li:padstack_prototypes {
|
||||
|
||||
ha:ps_proto_v6.0 {
|
||||
hdia=0.3mm; hplated=1; htop=0; hbottom=0;
|
||||
li:shape {
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
top = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
bottom = 1
|
||||
copper = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.6mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
intern = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ha:ps_proto_v6.1 {
|
||||
hdia=0.5mm; hplated=1; htop=0; hbottom=0;
|
||||
li:shape {
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
top = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
bottom = 1
|
||||
copper = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=0.8mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
intern = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ha:ps_proto_v6.2 {
|
||||
hdia=1.2mm; hplated=1; htop=0; hbottom=0;
|
||||
li:shape {
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
top = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
bottom = 1
|
||||
copper = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=3.5mm; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
intern = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ha:ps_proto_v6.3 {
|
||||
hdia=0.8mm; hplated=1; htop=0; hbottom=0;
|
||||
li:shape {
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
top = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
bottom = 1
|
||||
copper = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
|
||||
ha:ps_shape_v4 {
|
||||
ha:ps_circ { x=0.0; y=0.0; dia=64.0mil; }
|
||||
ha:combining { }
|
||||
ha:layer_mask {
|
||||
copper = 1
|
||||
intern = 1
|
||||
}
|
||||
clearance=0.0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
li:objects {
|
||||
}
|
||||
li:layers {
|
||||
|
||||
ha:top-sig {
|
||||
lid=0
|
||||
group=3
|
||||
ha:combining { }
|
||||
|
||||
ha:attributes {
|
||||
{pcb-rnd::key::vis}={<Key>l; Shift<Key>t}
|
||||
{pcb-rnd::key::select}={<Key>l; <Key>t}
|
||||
}
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#238b27}
|
||||
}
|
||||
|
||||
ha:bottom-sig {
|
||||
lid=1
|
||||
group=10
|
||||
ha:combining { }
|
||||
|
||||
ha:attributes {
|
||||
{pcb-rnd::key::vis}={<Key>l; Shift<Key>b}
|
||||
{pcb-rnd::key::select}={<Key>l; <Key>b}
|
||||
}
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#38ee39}
|
||||
}
|
||||
|
||||
ha:top-gnd {
|
||||
lid=2
|
||||
group=3
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#104e8b}
|
||||
}
|
||||
|
||||
ha:bottom-gnd {
|
||||
lid=3
|
||||
group=10
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#6164ff}
|
||||
}
|
||||
|
||||
ha:outline {
|
||||
lid=4
|
||||
group=7
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#00868b}
|
||||
}
|
||||
|
||||
ha:bottom-silk {
|
||||
lid=5
|
||||
group=12
|
||||
ha:combining { auto=1; }
|
||||
|
||||
ha:attributes {
|
||||
{pcb-rnd::key::vis}={<Key>l; Shift<Key>x}
|
||||
{pcb-rnd::key::select}={<Key>l; <Key>x}
|
||||
}
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#000000}
|
||||
}
|
||||
|
||||
ha:top-silk {
|
||||
lid=6
|
||||
group=1
|
||||
ha:combining { auto=1; }
|
||||
|
||||
ha:attributes {
|
||||
{pcb-rnd::key::vis}={<Key>l; Shift<Key>s}
|
||||
{pcb-rnd::key::select}={<Key>l; <Key>s}
|
||||
}
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#000000}
|
||||
}
|
||||
|
||||
ha:top-paste {
|
||||
lid=7
|
||||
group=0
|
||||
ha:combining { auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#cd00cd}
|
||||
}
|
||||
|
||||
ha:top-mask {
|
||||
lid=8
|
||||
group=2
|
||||
ha:combining { sub=1; auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#ff0000}
|
||||
}
|
||||
|
||||
ha:bottom-mask {
|
||||
lid=9
|
||||
group=11
|
||||
ha:combining { sub=1; auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#ff0000}
|
||||
}
|
||||
|
||||
ha:bottom-paste {
|
||||
lid=10
|
||||
group=13
|
||||
ha:combining { auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#cd00cd}
|
||||
}
|
||||
|
||||
ha:slot-plated {
|
||||
lid=11
|
||||
group=14
|
||||
ha:combining { auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#8b7355}
|
||||
}
|
||||
|
||||
ha:slot-unplated {
|
||||
lid=12
|
||||
group=15
|
||||
ha:combining { auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#00868b}
|
||||
}
|
||||
|
||||
ha:top-assy {
|
||||
lid=13
|
||||
group=16
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#444444}
|
||||
}
|
||||
|
||||
ha:bot-assy {
|
||||
lid=14
|
||||
group=17
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#444444}
|
||||
}
|
||||
|
||||
ha:fab {
|
||||
lid=15
|
||||
group=18
|
||||
ha:combining { auto=1; }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#222222}
|
||||
}
|
||||
|
||||
ha:top-courtyard {
|
||||
lid=16
|
||||
group=8
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#104e8b}
|
||||
}
|
||||
|
||||
ha:bot-courtyard {
|
||||
lid=17
|
||||
group=9
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#cd3700}
|
||||
}
|
||||
|
||||
ha:top-pwr {
|
||||
lid=18
|
||||
group=3
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#c24744}
|
||||
}
|
||||
|
||||
ha:bottom-pwr {
|
||||
lid=19
|
||||
group=10
|
||||
ha:combining { }
|
||||
|
||||
li:objects {
|
||||
}
|
||||
color = {#ff5759}
|
||||
}
|
||||
}
|
||||
}
|
||||
ha:layer_stack {
|
||||
li:groups {
|
||||
ha:0 {
|
||||
name = top_paste
|
||||
ha:type { top=1; paste=1; }
|
||||
li:layers { 7; }
|
||||
}
|
||||
ha:1 {
|
||||
name = top_silk
|
||||
ha:type { silk=1; top=1; }
|
||||
li:layers { 6; }
|
||||
}
|
||||
ha:2 {
|
||||
name = top_mask
|
||||
ha:type { top=1; mask=1; }
|
||||
li:layers { 8; }
|
||||
}
|
||||
ha:3 {
|
||||
name = top_copper
|
||||
ha:type { copper=1; top=1; }
|
||||
li:layers { 0; 18; 2; }
|
||||
}
|
||||
ha:4 {
|
||||
name = grp_4
|
||||
ha:type { substrate=1; intern=1; }
|
||||
li:layers { }
|
||||
ha:attributes {
|
||||
thickness={0.7375mm }
|
||||
}
|
||||
}
|
||||
ha:5 {
|
||||
name = grp_6
|
||||
ha:type { substrate=1; intern=1; }
|
||||
li:layers { }
|
||||
ha:attributes {
|
||||
thickness={0.125mm }
|
||||
}
|
||||
}
|
||||
ha:6 {
|
||||
name = grp_8
|
||||
ha:type { substrate=1; intern=1; }
|
||||
li:layers { }
|
||||
ha:attributes {
|
||||
thickness={0.7375mm }
|
||||
}
|
||||
}
|
||||
ha:7 {
|
||||
name = global_outline
|
||||
ha:type { boundary=1; }
|
||||
li:layers { 4; }
|
||||
purpose = uroute
|
||||
}
|
||||
ha:8 {
|
||||
name = top-courtyard
|
||||
ha:type { top=1; doc=1; }
|
||||
li:layers { 16; }
|
||||
ha:attributes {
|
||||
init-invis=true
|
||||
}
|
||||
purpose = ko.courtyard
|
||||
}
|
||||
ha:9 {
|
||||
name = bot-courtyard
|
||||
ha:type { bottom=1; doc=1; }
|
||||
li:layers { 17; }
|
||||
ha:attributes {
|
||||
init-invis=true
|
||||
}
|
||||
purpose = ko.courtyard
|
||||
}
|
||||
ha:10 {
|
||||
name = bottom_copper
|
||||
ha:type { bottom=1; copper=1; }
|
||||
li:layers { 1; 19; 3; }
|
||||
}
|
||||
ha:11 {
|
||||
name = bottom_mask
|
||||
ha:type { bottom=1; mask=1; }
|
||||
li:layers { 9; }
|
||||
}
|
||||
ha:12 {
|
||||
name = bottom_silk
|
||||
ha:type { silk=1; bottom=1; }
|
||||
li:layers { 5; }
|
||||
}
|
||||
ha:13 {
|
||||
name = bottom_paste
|
||||
ha:type { bottom=1; paste=1; }
|
||||
li:layers { 10; }
|
||||
}
|
||||
ha:14 {
|
||||
name = pmech
|
||||
ha:type { mech=1; }
|
||||
li:layers { 11; }
|
||||
purpose = proute
|
||||
}
|
||||
ha:15 {
|
||||
name = umech
|
||||
ha:type { mech=1; }
|
||||
li:layers { 12; }
|
||||
purpose = uroute
|
||||
}
|
||||
ha:16 {
|
||||
name = top_assy
|
||||
ha:type { top=1; doc=1; }
|
||||
li:layers { 13; }
|
||||
ha:attributes {
|
||||
init-invis=1
|
||||
}
|
||||
purpose = assy
|
||||
}
|
||||
ha:17 {
|
||||
name = bot_assy
|
||||
ha:type { bottom=1; doc=1; }
|
||||
li:layers { 14; }
|
||||
ha:attributes {
|
||||
init-invis=1
|
||||
}
|
||||
purpose = assy
|
||||
}
|
||||
ha:18 {
|
||||
name = fab
|
||||
ha:type { top=1; doc=1; }
|
||||
li:layers { 15; }
|
||||
ha:attributes {
|
||||
init-invis=1
|
||||
}
|
||||
purpose = fab
|
||||
}
|
||||
}
|
||||
}
|
||||
li:pcb-rnd-conf-v1 {
|
||||
ha:overwrite {
|
||||
ha:design {
|
||||
via_proto = 1
|
||||
text_font_id = 0
|
||||
text_scale = 100
|
||||
min_slk = 0.15240000 mm
|
||||
text_thickness = 0
|
||||
line_thickness = 10.00 mil
|
||||
ha:drc {
|
||||
min_ring = 0.15 mm
|
||||
min_copper_overlap = 6.0 mil
|
||||
min_drill = 0.3 mm
|
||||
}
|
||||
min_wid = 0.15240000 mm
|
||||
bloat = 0.15240000 mm
|
||||
clearance = 10.00 mil
|
||||
}
|
||||
ha:editor {
|
||||
grid_unit = mm
|
||||
grids_idx = 11
|
||||
grid = 500.00 um
|
||||
}
|
||||
ha:rc {
|
||||
li:library_search_paths {
|
||||
$(rc.path.design)/coraleda/subc
|
||||
$(rc.path.design)/coraleda/subc
|
||||
?../pcblib
|
||||
?~/pcblib/
|
||||
$(rc.path.share)/pcblib
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
ha:pixmaps {
|
||||
}
|
||||
}
|
22
template.sch
22
template.sch
@ -1,22 +0,0 @@
|
||||
v 20210626 2
|
||||
C 0 0 1 0 0 title.sym
|
||||
{
|
||||
T 1000 700 5 10 1 1 0 0 1
|
||||
date=$date$
|
||||
T 4300 700 5 10 1 1 0 0 1
|
||||
org=CuVoodoo
|
||||
T 4300 400 5 10 1 1 0 0 1
|
||||
authors=King Kévin
|
||||
T 3000 1200 5 14 1 1 0 4 1
|
||||
title=TITLE
|
||||
T 1000 400 5 10 1 1 0 0 1
|
||||
version=$version$
|
||||
T 1000 100 5 10 1 1 0 0 1
|
||||
revision=$revision$
|
||||
T 4300 100 5 10 1 1 0 0 1
|
||||
licence=CERN-OHL-S
|
||||
T 0 1800 5 10 0 0 0 0 1
|
||||
device=none
|
||||
T 0 2000 5 10 0 0 0 0 1
|
||||
footprint=none
|
||||
}
|
215
usb_bug_detector.brd.json
Normal file
215
usb_bug_detector.brd.json
Normal file
File diff suppressed because one or more lines are too long
109
usb_bug_detector.sch.json
Normal file
109
usb_bug_detector.sch.json
Normal file
File diff suppressed because one or more lines are too long
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Reference in New Issue
Block a user