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29 Commits

Author SHA1 Message Date
King Kévin 39dbceee73 doc: add smaller picutres 2022-06-27 15:27:52 +02:00
King Kévin 57cdeed762 doc: capitalize 2022-06-27 15:22:50 +02:00
King Kévin f1b16e644a doc: add v1 changes 2022-06-27 15:21:34 +02:00
King Kévin 832af46f21 doc: add pictures 2022-06-27 15:19:45 +02:00
King Kévin 9c6284cdde doc: update for v1 2022-06-27 15:19:28 +02:00
King Kévin 2006dc0a0a doc: mention EasyEDA 2022-06-27 15:13:52 +02:00
King Kévin 4b1abc9f33 brd: add completed EasyEDA board export 2022-06-27 15:11:51 +02:00
King Kévin 41cad366a6 sch: add completed EasyEDA schematic export 2022-06-27 15:09:35 +02:00
King Kévin 6ebc12417b remove geda settings 2022-06-27 15:05:10 +02:00
King Kévin af07a497fc switch to version 1 2022-06-27 15:02:31 +02:00
King Kévin e28a91654e doc: remove ununsed notes 2022-06-27 14:34:50 +02:00
King Kévin 909e6e1b58 doc: fix typo 2022-06-27 14:33:03 +02:00
King Kévin 11d0b83a0b doc add picture 2022-06-27 14:25:40 +02:00
King Kévin 734fe1d991 doc: add v0 details 2022-06-27 14:14:32 +02:00
King Kévin 52ed0b685c doc: add type-A information 2022-06-27 14:10:15 +02:00
King Kévin 02566303d8 doc: put development instructions in seperate file 2022-06-27 14:05:42 +02:00
King Kévin 930ef658b1 lib: update CR2032 footprint 2022-06-27 13:57:47 +02:00
King Kévin 3820f2cb43 readme: add power consumption 2021-07-22 18:35:20 +02:00
King Kévin 8191a4bf03 describe project in README 2021-07-22 18:13:40 +02:00
King Kévin 6038861fa2 use correct schematic and board 2021-07-22 13:19:34 +02:00
King Kévin 84e591ca4a sch: fix R/S swap 2021-07-22 13:13:20 +02:00
King Kévin 387d010064 brd: fix R/S swap 2021-07-22 13:13:03 +02:00
King Kévin d17f1843f8 sch: fix title symbol text for automatic substitution 2021-07-22 13:13:00 +02:00
King Kévin 6b664dfbb5 brd: fix typo 2021-07-22 13:11:46 +02:00
King Kévin 598455d14d brd: add initial completed layout 2021-07-22 13:11:40 +02:00
King Kévin e1bb7f4fba sch: add initial completed draft 2021-07-22 13:11:38 +02:00
King Kévin b1d0702c72 lib: add generated symbols and footprints 2021-07-22 13:11:32 +02:00
King Kévin 44601f120b lib: add hand made footprint (CR2032 battery holder) 2021-07-22 13:11:03 +02:00
King Kévin 546ab7fafd lib: add used parts 2021-07-22 13:10:45 +02:00
42 changed files with 402 additions and 8430 deletions

36
.gitignore vendored
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@ -1,37 +1,17 @@
# schematic lepton-EDA
*.sch
# board layout pcb-rnd
*.lht
*.lht.*
# KiCAD
*.kicad_prl
*.kicad_pro-bak
*.xml
fp-info-cache
# temporary files
*.versioned.lht
*~
\#*\#
~*.lck
# outputs
*.versioned.sch
*.svg
*.png
*.pdf
*.ps
*.zip
*.brd.*
*.tdx
\#*\#
*.notes.txt
*.bom.csv
*.cpl.csv
*.3d.step
*.versioned.*
fabrication
# scripts and utilities
*.cost.csv
*.json
*.rb
# panel files
panel.*
panel
geda/footprints/

2
.gitmodules vendored
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@ -1,3 +1,3 @@
[submodule "library"]
path = library
url = https://git.cuvoodoo.info/kingkevin/qeda_library
url = http://git.cuvoodoo.info/qeda_library

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@ -1,16 +1,17 @@
config:
nodate: true
output: kicad7
symbol:
pinIcon: false
output: coraleda
pattern:
densityLevel: 'N'
lineWidth:
silkscreen: 0.2
polarityMark: none
preferManufacturer: false
smoothPadCorners: false
library:
- resistor/r0603
- capacitor/c0603
- diode/led0805
- diode/led0603
- ic/nor-gate_ti_sn74hc02@soic
- ic/nor-gate_ti_sn74lvc1g02@dbv
- ic/nor-gate_ti_sn74lvc1g02@dck
- mechanical/smd-button_hyp_1ts002e
- connector/usb-a-2.0-receptacle

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@ -0,0 +1,12 @@
v1
==
uses smaller coin cell (CR1220).
use only one type of NOR-gate.
remove READY LED.
v0
==
working proof of concept prototype.
it allows populating NOR gates in different packages.

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@ -1,108 +1 @@
this will describe how to generate the output files form the sources.
requirements
============
to be able to generate the outputs, you need following software:
- [QEDA](http://qeda.org/): to generate footprints for the parts
- [KiCad v8](https://www.kicad.org/): EDA software used for schematic capture and board layout
- [PcbDraw](https://github.com/yaqwsx/PcbDraw): to generate board layout rendering
- [KiKit](https://github.com/yaqwsx/KiKit): to generate fabrications files (Gerber, Excellon)
- [KiBoM](https://github.com/SchrodingersGat/KiBoM): to generate Bill of Material (CSV)
- [Interactive HTML BOM](https://github.com/openscopeproject/InteractiveHtmlBom): to generate placement guide
install Interactive HTML BOM using KiCad's Plugin and Content Manager.
for the others:
~~~
npm install qeda
pip install pcbdraw kibom kikit
~~~
you can additionally install KiKit using KiCad's Plugin and Content Manager for an integrated GUI.
compiling
=========
to generate schematic, BoM, board render, and fabrication output, run `make`.
library
-------
almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
the `library` folder contains the QEDA parts definitions.
to install QEDA using NPM from the official repository:
~~~
sudo npm install -g qeda
~~~
to install QEDA from the sources:
~~~
git clone https://github.com/qeda/qeda
cd qeda
npm install
sudo npm install --global
~~~
to generate the parts:
~~~
make lib
~~~
this will use the parts definition (.yaml files) in the `library` to generate the symbols (.sym files) and footprints used by KiCAD in the `kicad` folder.
schematic
---------
the `.kicad_sch` file is the schematic source file.
it has been drawn using the [KiCAD eeschema](https://www.kicad.org/) schematic editor.
it uses standard symbols, and the ones in the `kicad/` folder.
most symbols are generated by QEDA as described above.
to export as pdf:
~~~
make print
~~~
BOM
---
to export the bill of material (as CSV):
~~~
make bom
~~~
board
-----
the `.kicad_brd` file is the board layout source file.
it has been drawn using the [KiCAD pcbnew](https://docs.kicad.org/6.0/en/pcbnew/pcbnew.html) PCB editor.
it uses the footprints from the `kicad/` folder.
most symbols are generated by QEDA as described above.
to export gerber files for PCB manufacturer (and photo preview + overview document):
~~~
make fabrication
~~~
versioning
----------
the source schematic and board layout do not include version information.
when generating schematic or board fabrication output, a copy of the source files with date and version information is done as `.versioned.` files.
the date corresponds to the last changes (i.e. commit).
the version is formatted as `v.r`:
- `v` corresponds to the major version information defined in `version`
- `r` corresponds to the total number of changes done to the source files
the JSON files are the source schematic and board layout made using [EasyEDA](https://easyeda.com/).

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#!/usr/bin/env python3
"""
@package
KiBOM - Bill of Materials generation for KiCad
Generate BOM in xml, csv, txt, tsv, html or xlsx formats.
- Components are automatically grouped into BoM rows (grouping is configurable)
- Component groups count number of components and list component designators
- Rows are automatically sorted by component reference(s)
- Supports board variants
Extended options are available in the "bom.ini" config file in the PCB directory
(this file is auto-generated with default options the first time the script is executed).
For usage help:
python KiBOM_CLI.py -h
"""
import sys
import os
here = os.path.abspath(os.path.dirname(__file__))
sys.path.insert(0, here)
from kibom.__main__ import main # noqa: E402
main()

112
Makefile
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# project file name (use for schematic and board layout)
NAME ?= template
SUBSHEET ?=
# path to KiCad CLI
KICAD = kicad-cli
# path to qeda
QEDA := qeda
# path to KiBOM
KIBOM := kibom
# path to InteractiveHtmlBom
IBOMGEN := ~/.local/share/kicad/8.0/3rdparty/plugins/org_openscopeproject_InteractiveHtmlBom/generate_interactive_bom.py
# read project version
VERSION := $(shell cat version)
# current date for stamping output
DATE = $(shell date +%Y-%m-%d)
# revision based on number of changes on schematic or board layout
REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l)
# generate file with version information
VERSIONED_EXT = kicad_sch kicad_pcb kicad_pro json
define version_rule
%.versioned.$1: %.$1
cp $$< $$@
sed --in-place 's/\$$$$version\$$$$/${VERSION}/g' $$@
sed --in-place 's/\$$$$date\$$$$/${DATE}/g' $$@
sed --in-place 's/\$$$$revision\$$$$/${REVISION}/g' $$@
sed --in-place 's/\.kicad_sch/.versioned.kicad_sch/g' $$@
endef
$(foreach EXT,$(VERSIONED_EXT),$(eval $(call version_rule,$(EXT))))
VERSIONED_SHEET = $(foreach SHEET,$(NAME) $(SUBSHEET),$(SHEET).versioned.kicad_sch)
FABRICATION_DIR := fabrication
IBOM := ${FABRICATION_DIR}/ibom.html
all: $(VERSIONED_SHEET) ${NAME}.sch.pdf ${NAME}.bom.csv render fab
fab: ${FABRICATION_DIR} ${IBOM}
render: ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.3d.step
# generate fabrication files (gerbers/drill/BoM/PnP)
${FABRICATION_DIR}: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
kikit fab jlcpcb --no-drc --assembly --field JLCPCB,LCSC --schematic $^ $@
# generate fabrication files (gerbers/drill/uncorrected PnP)
#${FABRICATION_DIR}: ${NAME}.versioned.kicad_pcb
# mkdir -p ${FABRICATION_DIR}
# $(KICAD) pcb export gerbers --output ${FABRICATION_DIR} $<
# $(KICAD) pcb export drill --output ${FABRICATION_DIR}/ $<
# $(KICAD) pcb export pos --output ${FABRICATION_DIR}/${NAME}.versioned.pos $<
# generate interactive BoM
${IBOM}: ${NAME}.versioned.kicad_pcb
python $(IBOMGEN) --no-browser --dest-dir `dirname $@` --name-format `basename $@ ".html"` --show-fields "Value" $< &>/dev/null
# generate symbols and footprints from parts
lib:
$(QEDA) generate qeda
# generate printable version (PDF) of schematic
%.sch.pdf: %.versioned.kicad_sch %.versioned.kicad_pro
$(KICAD) sch export pdf --output $@ $<
# generate render from layout (top side)
%.brd-top.png: %.versioned.kicad_pcb
pcbdraw plot --silent --no-components --dpi 600 --side front $< $@
# generate render from layout (bottom side)
%.brd-bot.png: %.versioned.kicad_pcb
pcbdraw plot --silent --no-components --dpi 600 --side back $< $@
# generate render from layout (top side)
%.brd-top.svg: %.versioned.kicad_pcb
$(KICAD) pcb export svg --layers F.Cu,F.Paste,F.Silkscreen,Edge.Cuts --page-size-mode 2 --exclude-drawing-sheet --output $@ $<
# generate render from layout (bottom side)
%.brd-bot.svg: %.versioned.kicad_pcb
$(KICAD) pcb export svg --layers B.Cu,B.Paste,B.Silkscreen,Edge.Cuts --mirror --page-size-mode 2 --exclude-drawing-sheet --output $@ $<
# export Bill of Material (as CSV)
%.bom.xml: %.versioned.kicad_sch %.versioned.kicad_pro
$(KICAD) sch export python-bom --output $@ $<
# export 3D model
%.3d.step: %.versioned.kicad_pcb
$(KICAD) pcb export step --output $@ $<
# export Bill of Material (as CSV)
%.bom.csv: %.bom.xml
$(KIBOM) $< $@
# generate panel
PANEL_DIR := panel_fab
panel: panel.kicad_pcb panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png ${PANEL_DIR}
panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch panel.versioned.json
kikit panelize -p panel.versioned.json ${NAME}.versioned.kicad_pcb $@
sed --in-place 's/\"missing_courtyard\": \"warning\"/\"missing_courtyard\": \"ignore\"/g' $(patsubst %.kicad_pcb,%.kicad_pro,$@) # the mouse bites don't have a courtyard
${PANEL_DIR}: ${NAME}.versioned.kicad_sch panel.kicad_pcb
kikit fab jlcpcb --assembly --missingError --field JLCPCB,LCSC --schematic $^ $@
clean:
rm -f $(foreach EXT,$(VERSIONED_EXT),${NAME}.versioned.$(EXT))
rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.versioned.xml ${NAME}.bom.csv
rm -f ${NAME}.versioned.kicad_prl ${NAME}.versioned.kicad_pro-bak ${NAME}.versioned.xml ${NAME}.versioned.csv
rm -f ${IBOM}
rm -rf ${FABRICATION_DIR}
rm -f panel.versioned.json panel.kicad_pcb panel.kicad_pro panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png
rm -rf ${PANEL_DIR}

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these are the hardware design files for **insert project name here**.
The USB bug detector identifies USB type-A cables (or devices) with integrated circuits.
purpose
=======
<img src="picture/v1_front.webp" title="front" height="250"/>
<img src="picture/v1_back.webp" title="back" height="250"/>
usage
=====
To use the USB bug detector, follow the steps provided on the back of the board:
- insert a CR1220 coin cell battery in the USB bug detector for it to be operational
- press on the RESET button to arm the test
- the BUGGED LED should be off
- plug the USB cable in the USB receptacle
- if the BUGGED LED switches on, the USB cable embeds an integrated circuit (e.g. a bug)
- if the BUGGED LED remains off, the cable is same to use
After the test, to save power, press again on the RESET button.
To ensure that the USB bug detector works, after pressing on the RESET button, press on the SIMULATE button.
This will simulate a USB plug with integrated circuit.
The BUGGED LED should switch on.
This also ensures the battery is not empty.
When the LED is on, the USB bug detector draws 3 mA.
When the LED is off, the USB bug detector draws 64 nA.
This results in a idle battery life of 62 years (for a typical 35 mAh CR1220 battery).
This is on par with the self life of the battery (~ 1%/year).
mode of operation
=================
An NOR-gate-based SR-latch is used.
The RESET button triggers the R signal to reset the latch.
When a USB cable is plugged, power is provided by the battery to the cable.
If an integrated circuits is present, current will flow through.
A 1 kOhm resistor on the low side (e.g. ground) will create a voltage.
If the plug draws more than 1.6 mA, the resulting 1.6 V will trigger the S signal to set the latch.
The BUG LED will indicate when the SR-latch is set.
The latch remains set until the RESET button is present.
Thus, even if the plug stops drawing power, the LED remains on.
This minimum 1.6 mA current draw is often caused by the decoupling/bypass capacitor required by integrated circuit, or accompanying voltage regulator.
When charging, the capacitor acts as a short for a small time, allowing current to flow.
On USB plugs with just resistors, or LEDs, the resulting current flow is not large enough.
The SIMULATE circuit simulates an integrated circuit by putting a 100 nF capacitor across the USB receptacle.
Because of the 1 kOhm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug.
This is often not enough to power up integrated circuit properly, particularly if they use a radio interface.
Thus it is safe to use the USB bug detector on bugs, without activating it.

108
bom.ini
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[BOM_OPTIONS]
; General BoM options here
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
ignore_dnf = 0
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
html_generate_dnf = 1
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
use_alt = 0
; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
alt_wrap = 0
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
number_rows = 1
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
group_connectors = 1
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
test_regex = 1
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
merge_blank_fields = 1
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
output_file_name = %O%V
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
variant_file_name_format = _(%V)
; Field name used to determine if a particular part is to be fitted
fit_field = Config
; Make a backup of the bom before generating the new one, using the following template
;make_backup = %O.tmp
; Default number of boards to produce if none given on CLI with -n
number_boards = 1
; Default PCB variant if none given on CLI with -r
board_variant = ['default']
; Whether to hide headers from output file
hide_headers = False
; Whether to hide PCB info from output file
hide_pcb_info = False
[IGNORE_COLUMNS]
; Any column heading that appears here will be excluded from the Generated BoM
; Titles are case-insensitive
Part
Part Lib
Footprint
Footprint Lib
Build Quantity
sheetpath
qeda_part
qeda_variant
name
JLCPCB_CORRECTION
Rating
[COLUMN_ORDER]
; Columns will appear in the order they are listed here
; Titles are case-insensitive
References
Value
Quantity Per PCB
Description
Part
Part Lib
Footprint
Footprint Lib
Build Quantity
Manufacturer
MPN
DigiKey
LCSC
JLCPCB
Datasheet
[GROUP_FIELDS]
; List of fields used for sorting individual components into groups
; Components which match (comparing *all* fields) will be grouped together
; Field names are case-insensitive
Value
Footprint
Footprint Lib
[COMPONENT_ALIASES]
; A series of values which are considered to be equivalent for the part name
; Each line represents a list of equivalent component name values separated by white space
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
; Aliases are case-insensitive
c c_small cap capacitor
r r_small res resistor
sw switch
l l_small inductor
zener zenersmall
d diode d_small
[REGEX_INCLUDE]
; A series of regular expressions used to include parts in the BoM
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
[REGEX_EXCLUDE]
; A series of regular expressions used to exclude parts from the BoM
; If a component matches ANY of these, it will be excluded from the BoM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (white-space separated)
References ^TP[0-9]*
References ^FID
Part mount.*hole
Part solder.*bridge
Part test.*point
Footprint test.*point
Footprint mount.*hole
Footprint fiducial

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@ -1,6 +0,0 @@
(fp_lib_table
(version 7)
(lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.pretty")(options "")(descr ""))
(lib (name "kikit")(type "KiCad")(uri "${KIPRJMOD}/kicad/kikit.pretty")(options "")(descr ""))
(lib (name "logo")(type "KiCad")(uri "${KIPRJMOD}/kicad/logo.pretty")(options "")(descr ""))
)

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(module Board (layer F.Cu) (tedit 605A21C1)
(descr "Mark board for extraction")
(attr virtual)
(fp_text reference REF** (at -4.5 -5) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
(fp_text value Board (at -7.25 -5) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0 0) (end -1.25 -4) (layer Dwgs.User) (width 0.2))
(fp_line (start -1.25 -4) (end -9.25 -4) (layer Dwgs.User) (width 0.2))
(fp_line (start 0 0) (end 0.5 -1) (layer Dwgs.User) (width 0.2))
(fp_line (start 0 0) (end -1 -0.5) (layer Dwgs.User) (width 0.2))
)

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@ -1,13 +0,0 @@
(module Fiducial:Fiducial (layer F.Cu) (tedit 5EA93A7C)
(descr "Circular Fiducial")
(tags fiducial)
(attr smd)
(fp_text reference REF** (at 0 -1.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Fiducial (at 0 1.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd circle (at 0 0) (size 0.5 0.5) (layers F.Cu F.Mask)
(solder_mask_margin 0.25) (clearance 0.25))
)

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@ -1,9 +0,0 @@
(module NPTH (layer F.Cu) (tedit 618E7E16)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value NPTH (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 1) (layers *.Cu *.Mask))
)

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@ -1,17 +0,0 @@
(module Tab (layer F.Cu) (tedit 60708B1A)
(descr "A symbol representing annotation for tab placement")
(attr virtual)
(fp_text reference REF** (at 0 -2) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Tab (at -2.75 -1) (layer Dwgs.User)
(effects (font (size 1.2 1.2) (thickness 0.2)))
)
(fp_line (start 0.25 0) (end -0.75 1) (layer Dwgs.User) (width 0.3))
(fp_line (start 0.25 0) (end -0.75 -1) (layer Dwgs.User) (width 0.3))
(fp_line (start 0.25 0) (end -2.75 0) (layer Dwgs.User) (width 0.3))
(fp_line (start 0.25 1) (end 0.25 -1) (layer Dwgs.User) (width 0.3))
(fp_text user "KIKIT: width: 3mm" (at -5.5 0 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.15)))
)
)

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@ -1,950 +0,0 @@
(footprint "CuVoodoo_copper" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "CuVoodoo logo")
(attr smd board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
(fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp f846a54a-9ddc-4bbc-be16-9ad293284767)
)
(fp_text value "CuVoodoo_copper" (at 0 1 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp a2d5c5b6-08b2-4c1d-af6a-961acdb63b34)
)
(fp_line (start 6 5) (end 6 4)
(stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp db907c8a-7c13-47f0-8576-f8342c6fc43f))
(fp_line (start 8.75 3.75) (end 6.25 3.75)
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