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usb_bug_de
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36
.gitignore
vendored
36
.gitignore
vendored
@ -1,37 +1,17 @@
|
||||
# schematic lepton-EDA
|
||||
*.sch
|
||||
|
||||
# board layout pcb-rnd
|
||||
*.lht
|
||||
*.lht.*
|
||||
|
||||
# KiCAD
|
||||
*.kicad_prl
|
||||
*.kicad_pro-bak
|
||||
*.xml
|
||||
fp-info-cache
|
||||
|
||||
# temporary files
|
||||
*.versioned.lht
|
||||
*~
|
||||
\#*\#
|
||||
~*.lck
|
||||
|
||||
# outputs
|
||||
*.versioned.sch
|
||||
*.svg
|
||||
*.png
|
||||
*.pdf
|
||||
*.ps
|
||||
*.zip
|
||||
*.brd.*
|
||||
*.tdx
|
||||
\#*\#
|
||||
*.notes.txt
|
||||
*.bom.csv
|
||||
*.cpl.csv
|
||||
*.3d.step
|
||||
*.versioned.*
|
||||
fabrication
|
||||
|
||||
# scripts and utilities
|
||||
*.cost.csv
|
||||
*.json
|
||||
*.rb
|
||||
|
||||
# panel files
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||||
panel.*
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||||
panel
|
||||
geda/footprints/
|
||||
|
2
.gitmodules
vendored
2
.gitmodules
vendored
@ -1,3 +1,3 @@
|
||||
[submodule "library"]
|
||||
path = library
|
||||
url = https://git.cuvoodoo.info/kingkevin/qeda_library
|
||||
url = http://git.cuvoodoo.info/qeda_library
|
||||
|
13
.qeda.yaml
13
.qeda.yaml
@ -1,16 +1,17 @@
|
||||
config:
|
||||
nodate: true
|
||||
output: kicad7
|
||||
symbol:
|
||||
pinIcon: false
|
||||
output: coraleda
|
||||
pattern:
|
||||
densityLevel: 'N'
|
||||
lineWidth:
|
||||
silkscreen: 0.2
|
||||
polarityMark: none
|
||||
preferManufacturer: false
|
||||
smoothPadCorners: false
|
||||
library:
|
||||
- resistor/r0603
|
||||
- capacitor/c0603
|
||||
- diode/led0805
|
||||
- diode/led0603
|
||||
- ic/nor-gate_ti_sn74hc02@soic
|
||||
- ic/nor-gate_ti_sn74lvc1g02@dbv
|
||||
- ic/nor-gate_ti_sn74lvc1g02@dck
|
||||
- mechanical/smd-button_hyp_1ts002e
|
||||
- connector/usb-a-2.0-receptacle
|
||||
|
12
CHANGELOG.md
12
CHANGELOG.md
@ -0,0 +1,12 @@
|
||||
v1
|
||||
==
|
||||
|
||||
uses smaller coin cell (CR1220).
|
||||
use only one type of NOR-gate.
|
||||
remove READY LED.
|
||||
|
||||
v0
|
||||
==
|
||||
|
||||
working proof of concept prototype.
|
||||
it allows populating NOR gates in different packages.
|
109
DEVELOPMENT.md
109
DEVELOPMENT.md
@ -1,108 +1 @@
|
||||
this will describe how to generate the output files form the sources.
|
||||
|
||||
requirements
|
||||
============
|
||||
|
||||
to be able to generate the outputs, you need following software:
|
||||
|
||||
- [QEDA](http://qeda.org/): to generate footprints for the parts
|
||||
- [KiCad v8](https://www.kicad.org/): EDA software used for schematic capture and board layout
|
||||
- [PcbDraw](https://github.com/yaqwsx/PcbDraw): to generate board layout rendering
|
||||
- [KiKit](https://github.com/yaqwsx/KiKit): to generate fabrications files (Gerber, Excellon)
|
||||
- [KiBoM](https://github.com/SchrodingersGat/KiBoM): to generate Bill of Material (CSV)
|
||||
- [Interactive HTML BOM](https://github.com/openscopeproject/InteractiveHtmlBom): to generate placement guide
|
||||
|
||||
install Interactive HTML BOM using KiCad's Plugin and Content Manager.
|
||||
|
||||
for the others:
|
||||
|
||||
~~~
|
||||
npm install qeda
|
||||
pip install pcbdraw kibom kikit
|
||||
~~~
|
||||
|
||||
you can additionally install KiKit using KiCad's Plugin and Content Manager for an integrated GUI.
|
||||
|
||||
compiling
|
||||
=========
|
||||
|
||||
to generate schematic, BoM, board render, and fabrication output, run `make`.
|
||||
|
||||
library
|
||||
-------
|
||||
|
||||
almost all of the symbols and footprints used in the schematic and board layout are defined in the [QEDA](http://qeda.org/) format and generated for the CAD software.
|
||||
the `library` folder contains the QEDA parts definitions.
|
||||
|
||||
to install QEDA using NPM from the official repository:
|
||||
|
||||
~~~
|
||||
sudo npm install -g qeda
|
||||
~~~
|
||||
|
||||
to install QEDA from the sources:
|
||||
|
||||
~~~
|
||||
git clone https://github.com/qeda/qeda
|
||||
cd qeda
|
||||
npm install
|
||||
sudo npm install --global
|
||||
~~~
|
||||
|
||||
to generate the parts:
|
||||
|
||||
~~~
|
||||
make lib
|
||||
~~~
|
||||
|
||||
this will use the parts definition (.yaml files) in the `library` to generate the symbols (.sym files) and footprints used by KiCAD in the `kicad` folder.
|
||||
|
||||
schematic
|
||||
---------
|
||||
|
||||
the `.kicad_sch` file is the schematic source file.
|
||||
it has been drawn using the [KiCAD eeschema](https://www.kicad.org/) schematic editor.
|
||||
|
||||
it uses standard symbols, and the ones in the `kicad/` folder.
|
||||
most symbols are generated by QEDA as described above.
|
||||
|
||||
to export as pdf:
|
||||
|
||||
~~~
|
||||
make print
|
||||
~~~
|
||||
|
||||
BOM
|
||||
---
|
||||
|
||||
to export the bill of material (as CSV):
|
||||
|
||||
~~~
|
||||
make bom
|
||||
~~~
|
||||
|
||||
board
|
||||
-----
|
||||
|
||||
the `.kicad_brd` file is the board layout source file.
|
||||
it has been drawn using the [KiCAD pcbnew](https://docs.kicad.org/6.0/en/pcbnew/pcbnew.html) PCB editor.
|
||||
|
||||
it uses the footprints from the `kicad/` folder.
|
||||
most symbols are generated by QEDA as described above.
|
||||
|
||||
to export gerber files for PCB manufacturer (and photo preview + overview document):
|
||||
|
||||
~~~
|
||||
make fabrication
|
||||
~~~
|
||||
|
||||
versioning
|
||||
----------
|
||||
|
||||
the source schematic and board layout do not include version information.
|
||||
when generating schematic or board fabrication output, a copy of the source files with date and version information is done as `.versioned.` files.
|
||||
the date corresponds to the last changes (i.e. commit).
|
||||
the version is formatted as `v.r`:
|
||||
|
||||
- `v` corresponds to the major version information defined in `version`
|
||||
- `r` corresponds to the total number of changes done to the source files
|
||||
the JSON files are the source schematic and board layout made using [EasyEDA](https://easyeda.com/).
|
||||
|
28
KiBOM_CLI.py
28
KiBOM_CLI.py
@ -1,28 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
@package
|
||||
KiBOM - Bill of Materials generation for KiCad
|
||||
|
||||
Generate BOM in xml, csv, txt, tsv, html or xlsx formats.
|
||||
|
||||
- Components are automatically grouped into BoM rows (grouping is configurable)
|
||||
- Component groups count number of components and list component designators
|
||||
- Rows are automatically sorted by component reference(s)
|
||||
- Supports board variants
|
||||
|
||||
Extended options are available in the "bom.ini" config file in the PCB directory
|
||||
(this file is auto-generated with default options the first time the script is executed).
|
||||
|
||||
For usage help:
|
||||
python KiBOM_CLI.py -h
|
||||
"""
|
||||
|
||||
import sys
|
||||
import os
|
||||
|
||||
here = os.path.abspath(os.path.dirname(__file__))
|
||||
sys.path.insert(0, here)
|
||||
|
||||
from kibom.__main__ import main # noqa: E402
|
||||
|
||||
main()
|
104
Makefile
104
Makefile
@ -1,104 +0,0 @@
|
||||
# project file name (use for schematic and board layout)
|
||||
NAME ?= template
|
||||
SUBSHEET ?=
|
||||
# path to KiCad CLI
|
||||
KICAD = kicad-cli
|
||||
# path to qeda
|
||||
QEDA := qeda
|
||||
# path to KiBOM
|
||||
KIBOM := kibom
|
||||
# path to InteractiveHtmlBom
|
||||
IBOMGEN := ~/.local/share/kicad/8.0/3rdparty/plugins/org_openscopeproject_InteractiveHtmlBom/generate_interactive_bom.py
|
||||
|
||||
# read project version
|
||||
VERSION := $(shell cat version)
|
||||
# current date for stamping output
|
||||
DATE = $(shell date +%Y-%m-%d)
|
||||
# revision based on number of changes on schematic or board layout
|
||||
REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l)
|
||||
|
||||
# generate file with version information
|
||||
VERSIONED_EXT = kicad_sch kicad_pcb kicad_pro json
|
||||
define version_rule
|
||||
%.versioned.$1: %.$1
|
||||
cp $$< $$@
|
||||
sed --in-place 's/\$$$$version\$$$$/${VERSION}/g' $$@
|
||||
sed --in-place 's/\$$$$date\$$$$/${DATE}/g' $$@
|
||||
sed --in-place 's/\$$$$revision\$$$$/${REVISION}/g' $$@
|
||||
sed --in-place 's/\.kicad_sch/.versioned.kicad_sch/g' $$@
|
||||
endef
|
||||
$(foreach EXT,$(VERSIONED_EXT),$(eval $(call version_rule,$(EXT))))
|
||||
VERSIONED_SHEET = $(foreach SHEET,$(NAME) $(SUBSHEET),$(SHEET).versioned.kicad_sch)
|
||||
|
||||
FABRICATION_DIR := fabrication
|
||||
IBOM := ${FABRICATION_DIR}/ibom.html
|
||||
|
||||
all: $(VERSIONED_SHEET) ${NAME}.sch.pdf ${NAME}.bom.csv render fab
|
||||
|
||||
fab: ${FABRICATION_DIR} ${IBOM}
|
||||
|
||||
render: ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.3d.step
|
||||
|
||||
# generate fabrication files (gerbers/drill/BoM/PnP)
|
||||
${FABRICATION_DIR}: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
|
||||
kikit fab jlcpcb --no-drc --assembly --field JLCPCB,LCSC --schematic $^ $@
|
||||
|
||||
# generate fabrication files (gerbers/drill/uncorrected PnP)
|
||||
#${FABRICATION_DIR}: ${NAME}.versioned.kicad_pcb
|
||||
# mkdir -p ${FABRICATION_DIR}
|
||||
# $(KICAD) pcb export gerbers --output ${FABRICATION_DIR} $<
|
||||
# $(KICAD) pcb export drill --output ${FABRICATION_DIR}/ $<
|
||||
# $(KICAD) pcb export pos --output ${FABRICATION_DIR}/${NAME}.versioned.pos $<
|
||||
|
||||
# generate interactive BoM
|
||||
${IBOM}: ${NAME}.versioned.kicad_pcb
|
||||
python $(IBOMGEN) --no-browser --dest-dir `dirname $@` --name-format `basename $@ ".html"` --show-fields "Value" $< &>/dev/null
|
||||
|
||||
# generate symbols and footprints from parts
|
||||
lib:
|
||||
$(QEDA) generate qeda
|
||||
|
||||
# generate printable version (PDF) of schematic
|
||||
%.sch.pdf: %.versioned.kicad_sch %.versioned.kicad_pro
|
||||
$(KICAD) sch export pdf --output $@ $<
|
||||
|
||||
# generate render from layout (top side)
|
||||
%.brd-top.svg: %.versioned.kicad_pcb
|
||||
$(KICAD) pcb export svg --layers F.Cu,F.Paste,F.Silkscreen,Edge.Cuts --page-size-mode 2 --exclude-drawing-sheet --output $@ $<
|
||||
|
||||
# generate render from layout (bottom side)
|
||||
%.brd-bot.svg: %.versioned.kicad_pcb
|
||||
$(KICAD) pcb export svg --layers B.Cu,B.Paste,B.Silkscreen,Edge.Cuts --mirror --page-size-mode 2 --exclude-drawing-sheet --output $@ $<
|
||||
|
||||
# export Bill of Material (as CSV)
|
||||
%.bom.xml: %.versioned.kicad_sch %.versioned.kicad_pro
|
||||
$(KICAD) sch export python-bom --output $@ $<
|
||||
|
||||
# export 3D model
|
||||
%.3d.step: %.versioned.kicad_pcb
|
||||
$(KICAD) pcb export step --output $@ $<
|
||||
|
||||
# export Bill of Material (as CSV)
|
||||
%.bom.csv: %.bom.xml
|
||||
$(KIBOM) $< $@
|
||||
|
||||
# generate panel
|
||||
PANEL_DIR := panel_fab
|
||||
|
||||
panel: panel.kicad_pcb panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png ${PANEL_DIR}
|
||||
|
||||
panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch panel.versioned.json
|
||||
kikit panelize -p panel.versioned.json ${NAME}.versioned.kicad_pcb $@
|
||||
sed --in-place 's/\"missing_courtyard\": \"warning\"/\"missing_courtyard\": \"ignore\"/g' $(patsubst %.kicad_pcb,%.kicad_pro,$@) # the mouse bites don't have a courtyard
|
||||
|
||||
${PANEL_DIR}: ${NAME}.versioned.kicad_sch panel.kicad_pcb
|
||||
kikit fab jlcpcb --assembly --missingError --field JLCPCB,LCSC --schematic $^ $@
|
||||
|
||||
clean:
|
||||
rm -f $(foreach EXT,$(VERSIONED_EXT),${NAME}.versioned.$(EXT))
|
||||
rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.brd-top.svg ${NAME}.brd-bot.svg ${NAME}.versioned.xml ${NAME}.bom.csv
|
||||
rm -f ${NAME}.versioned.kicad_prl ${NAME}.versioned.kicad_pro-bak ${NAME}.versioned.xml ${NAME}.versioned.csv
|
||||
rm -f ${IBOM}
|
||||
rm -rf ${FABRICATION_DIR}
|
||||
rm -f panel.versioned.json panel.kicad_pcb panel.kicad_pro panel.brd-top.svg panel.brd-bot.svg panel.brd-top.png panel.brd-bot.png
|
||||
rm -rf ${PANEL_DIR}
|
50
README.md
50
README.md
@ -1,7 +1,51 @@
|
||||
these are the hardware design files for **insert project name here**.
|
||||
The USB bug detector identifies USB type-A cables (or devices) with integrated circuits.
|
||||
|
||||
purpose
|
||||
=======
|
||||
<img src="picture/v1_front.webp" title="front" height="250"/>
|
||||
<img src="picture/v1_back.webp" title="back" height="250"/>
|
||||
|
||||
usage
|
||||
=====
|
||||
|
||||
To use the USB bug detector, follow the steps provided on the back of the board:
|
||||
|
||||
- insert a CR1220 coin cell battery in the USB bug detector for it to be operational
|
||||
- press on the RESET button to arm the test
|
||||
- the BUGGED LED should be off
|
||||
- plug the USB cable in the USB receptacle
|
||||
- if the BUGGED LED switches on, the USB cable embeds an integrated circuit (e.g. a bug)
|
||||
- if the BUGGED LED remains off, the cable is same to use
|
||||
|
||||
After the test, to save power, press again on the RESET button.
|
||||
|
||||
To ensure that the USB bug detector works, after pressing on the RESET button, press on the SIMULATE button.
|
||||
This will simulate a USB plug with integrated circuit.
|
||||
The BUGGED LED should switch on.
|
||||
This also ensures the battery is not empty.
|
||||
|
||||
When the LED is on, the USB bug detector draws 3 mA.
|
||||
When the LED is off, the USB bug detector draws 64 nA.
|
||||
This results in a idle battery life of 62 years (for a typical 35 mAh CR1220 battery).
|
||||
This is on par with the self life of the battery (~ 1%/year).
|
||||
|
||||
mode of operation
|
||||
=================
|
||||
|
||||
An NOR-gate-based SR-latch is used.
|
||||
The RESET button triggers the R signal to reset the latch.
|
||||
When a USB cable is plugged, power is provided by the battery to the cable.
|
||||
If an integrated circuits is present, current will flow through.
|
||||
A 1 kOhm resistor on the low side (e.g. ground) will create a voltage.
|
||||
If the plug draws more than 1.6 mA, the resulting 1.6 V will trigger the S signal to set the latch.
|
||||
The BUG LED will indicate when the SR-latch is set.
|
||||
The latch remains set until the RESET button is present.
|
||||
Thus, even if the plug stops drawing power, the LED remains on.
|
||||
|
||||
This minimum 1.6 mA current draw is often caused by the decoupling/bypass capacitor required by integrated circuit, or accompanying voltage regulator.
|
||||
When charging, the capacitor acts as a short for a small time, allowing current to flow.
|
||||
On USB plugs with just resistors, or LEDs, the resulting current flow is not large enough.
|
||||
|
||||
The SIMULATE circuit simulates an integrated circuit by putting a 100 nF capacitor across the USB receptacle.
|
||||
|
||||
Because of the 1 kOhm inline resistor, and limited 3.3 V provided by the battery, a maximum of 3.3 mA can be drawn by the USB plug.
|
||||
This is often not enough to power up integrated circuit properly, particularly if they use a radio interface.
|
||||
Thus it is safe to use the USB bug detector on bugs, without activating it.
|
||||
|
108
bom.ini
108
bom.ini
@ -1,108 +0,0 @@
|
||||
[BOM_OPTIONS]
|
||||
; General BoM options here
|
||||
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
|
||||
ignore_dnf = 0
|
||||
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
|
||||
html_generate_dnf = 1
|
||||
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
|
||||
use_alt = 0
|
||||
; If 'alt_wrap' option is set to and integer N, the references field will wrap after N entries are printed
|
||||
alt_wrap = 0
|
||||
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
|
||||
number_rows = 1
|
||||
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
|
||||
group_connectors = 1
|
||||
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
|
||||
test_regex = 1
|
||||
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
|
||||
merge_blank_fields = 1
|
||||
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
|
||||
output_file_name = %O%V
|
||||
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
|
||||
variant_file_name_format = _(%V)
|
||||
; Field name used to determine if a particular part is to be fitted
|
||||
fit_field = Config
|
||||
; Make a backup of the bom before generating the new one, using the following template
|
||||
;make_backup = %O.tmp
|
||||
; Default number of boards to produce if none given on CLI with -n
|
||||
number_boards = 1
|
||||
; Default PCB variant if none given on CLI with -r
|
||||
board_variant = ['default']
|
||||
; Whether to hide headers from output file
|
||||
hide_headers = False
|
||||
; Whether to hide PCB info from output file
|
||||
hide_pcb_info = False
|
||||
|
||||
[IGNORE_COLUMNS]
|
||||
; Any column heading that appears here will be excluded from the Generated BoM
|
||||
; Titles are case-insensitive
|
||||
Part
|
||||
Part Lib
|
||||
Footprint
|
||||
Footprint Lib
|
||||
Build Quantity
|
||||
sheetpath
|
||||
qeda_part
|
||||
qeda_variant
|
||||
name
|
||||
JLCPCB_CORRECTION
|
||||
Rating
|
||||
|
||||
[COLUMN_ORDER]
|
||||
; Columns will appear in the order they are listed here
|
||||
; Titles are case-insensitive
|
||||
References
|
||||
Value
|
||||
Quantity Per PCB
|
||||
Description
|
||||
Part
|
||||
Part Lib
|
||||
Footprint
|
||||
Footprint Lib
|
||||
Build Quantity
|
||||
Manufacturer
|
||||
MPN
|
||||
DigiKey
|
||||
LCSC
|
||||
JLCPCB
|
||||
Datasheet
|
||||
|
||||
[GROUP_FIELDS]
|
||||
; List of fields used for sorting individual components into groups
|
||||
; Components which match (comparing *all* fields) will be grouped together
|
||||
; Field names are case-insensitive
|
||||
Value
|
||||
Footprint
|
||||
Footprint Lib
|
||||
|
||||
[COMPONENT_ALIASES]
|
||||
; A series of values which are considered to be equivalent for the part name
|
||||
; Each line represents a list of equivalent component name values separated by white space
|
||||
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
|
||||
; Aliases are case-insensitive
|
||||
c c_small cap capacitor
|
||||
r r_small res resistor
|
||||
sw switch
|
||||
l l_small inductor
|
||||
zener zenersmall
|
||||
d diode d_small
|
||||
|
||||
[REGEX_INCLUDE]
|
||||
; A series of regular expressions used to include parts in the BoM
|
||||
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
|
||||
; Column names are case-insensitive
|
||||
; Format is: "[ColumName] [Regex]" (white-space separated)
|
||||
|
||||
[REGEX_EXCLUDE]
|
||||
; A series of regular expressions used to exclude parts from the BoM
|
||||
; If a component matches ANY of these, it will be excluded from the BoM
|
||||
; Column names are case-insensitive
|
||||
; Format is: "[ColumName] [Regex]" (white-space separated)
|
||||
References ^TP[0-9]*
|
||||
References ^FID
|
||||
Part mount.*hole
|
||||
Part solder.*bridge
|
||||
Part test.*point
|
||||
Footprint test.*point
|
||||
Footprint mount.*hole
|
||||
Footprint fiducial
|
@ -1,6 +0,0 @@
|
||||
(fp_lib_table
|
||||
(version 7)
|
||||
(lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.pretty")(options "")(descr ""))
|
||||
(lib (name "kikit")(type "KiCad")(uri "${KIPRJMOD}/kicad/kikit.pretty")(options "")(descr ""))
|
||||
(lib (name "logo")(type "KiCad")(uri "${KIPRJMOD}/kicad/logo.pretty")(options "")(descr ""))
|
||||
)
|
@ -1,14 +0,0 @@
|
||||
(module Board (layer F.Cu) (tedit 605A21C1)
|
||||
(descr "Mark board for extraction")
|
||||
(attr virtual)
|
||||
(fp_text reference REF** (at -4.5 -5) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify left))
|
||||
)
|
||||
(fp_text value Board (at -7.25 -5) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 0 0) (end -1.25 -4) (layer Dwgs.User) (width 0.2))
|
||||
(fp_line (start -1.25 -4) (end -9.25 -4) (layer Dwgs.User) (width 0.2))
|
||||
(fp_line (start 0 0) (end 0.5 -1) (layer Dwgs.User) (width 0.2))
|
||||
(fp_line (start 0 0) (end -1 -0.5) (layer Dwgs.User) (width 0.2))
|
||||
)
|
@ -1,13 +0,0 @@
|
||||
(module Fiducial:Fiducial (layer F.Cu) (tedit 5EA93A7C)
|
||||
(descr "Circular Fiducial")
|
||||
(tags fiducial)
|
||||
(attr smd)
|
||||
(fp_text reference REF** (at 0 -1.5) (layer F.SilkS) hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Fiducial (at 0 1.5) (layer F.Fab) hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(pad "" smd circle (at 0 0) (size 0.5 0.5) (layers F.Cu F.Mask)
|
||||
(solder_mask_margin 0.25) (clearance 0.25))
|
||||
)
|
@ -1,9 +0,0 @@
|
||||
(module NPTH (layer F.Cu) (tedit 618E7E16)
|
||||
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value NPTH (at 0 -0.5) (layer F.Fab) hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 1) (layers *.Cu *.Mask))
|
||||
)
|
@ -1,17 +0,0 @@
|
||||
(module Tab (layer F.Cu) (tedit 60708B1A)
|
||||
(descr "A symbol representing annotation for tab placement")
|
||||
(attr virtual)
|
||||
(fp_text reference REF** (at 0 -2) (layer F.SilkS) hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Tab (at -2.75 -1) (layer Dwgs.User)
|
||||
(effects (font (size 1.2 1.2) (thickness 0.2)))
|
||||
)
|
||||
(fp_line (start 0.25 0) (end -0.75 1) (layer Dwgs.User) (width 0.3))
|
||||
(fp_line (start 0.25 0) (end -0.75 -1) (layer Dwgs.User) (width 0.3))
|
||||
(fp_line (start 0.25 0) (end -2.75 0) (layer Dwgs.User) (width 0.3))
|
||||
(fp_line (start 0.25 1) (end 0.25 -1) (layer Dwgs.User) (width 0.3))
|
||||
(fp_text user "KIKIT: width: 3mm" (at -5.5 0 90) (layer Dwgs.User)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
)
|
@ -1,950 +0,0 @@
|
||||
(footprint "CuVoodoo_copper" (version 20221018) (generator pcbnew)
|
||||
(layer "F.Cu")
|
||||
(descr "CuVoodoo logo")
|
||||
(attr smd board_only exclude_from_pos_files exclude_from_bom allow_missing_courtyard)
|
||||
(fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide
|
||||
(effects (font (size 1 1) (thickness 0.1)))
|
||||
(tstamp f846a54a-9ddc-4bbc-be16-9ad293284767)
|
||||
)
|
||||
(fp_text value "CuVoodoo_copper" (at 0 1 unlocked) (layer "F.Fab") hide
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp a2d5c5b6-08b2-4c1d-af6a-961acdb63b34)
|
||||
)
|
||||
(fp_line (start 6 5) (end 6 4)
|
||||
(stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp db907c8a-7c13-47f0-8576-f8342c6fc43f))
|
||||
(fp_line (start 8.75 3.75) (end 6.25 3.75)
|
||||
(stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 375d8ca2-9b58-471f-b2aa-d5a472f93281))
|
||||
(fp_arc (start 6 4) (mid 6.073223 3.823223) (end 6.25 3.75)
|
||||
(stroke (width 0.25) (type solid)) (layer "F.Cu") (tstamp 0af9ea9b-3856-4e16-89c4-11bf31d4c0f6))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 1.25 3.999999)
|
||||
(xy 0.5 3.999999)
|
||||
(xy 0.5 3.499999)
|
||||
(xy 1.25 3.499999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp d164f9a4-dbe2-44e7-8ad8-2d914a8f7a6c))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 3.749999 9.499998)
|
||||
(xy 3.499999 9.499998)
|
||||
(xy 3.499999 8.999998)
|
||||
(xy 3.749999 8.999998)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 028a1ea9-a14e-4d86-884a-794e4e371399))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 6.249999 9.499998)
|
||||
(xy 5.999999 9.499998)
|
||||
(xy 5.999999 8.999998)
|
||||
(xy 6.249999 8.999998)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 6183cedd-1b0c-488e-b67c-11b1d2d2911f))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 9.499998 3.999999)
|
||||
(xy 8.749998 3.999999)
|
||||
(xy 8.749998 3.499999)
|
||||
(xy 9.499998 3.499999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 9f335a7b-79ff-4f78-b12d-8e0ae29f952f))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 4.499999 4.749999)
|
||||
(xy 3.999999 4.749999)
|
||||
(xy 3.999999 5.749999)
|
||||
(xy 4.749999 5.749999)
|
||||
(xy 4.749999 6.249999)
|
||||
(xy 3.499999 6.249999)
|
||||
(xy 3.499999 4.249999)
|
||||
(xy 4.499999 4.249999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp b5fef6d2-7e7e-4965-bcdc-f4722e8267a7))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 6.249999 6.249999)
|
||||
(xy 4.999999 6.249999)
|
||||
(xy 4.999999 5.499999)
|
||||
(xy 5.499999 5.499999)
|
||||
(xy 5.499999 5.749999)
|
||||
(xy 5.749999 5.749999)
|
||||
(xy 5.749999 4.999999)
|
||||
(xy 6.249999 4.999999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 8bb02f0d-c4a1-49c9-a185-6c1be76e4313))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 4.750097 1.749764)
|
||||
(xy 3.999755 1.749764)
|
||||
(xy 3.999755 1.250053)
|
||||
(xy 4.249869 1.250053)
|
||||
(xy 4.249869 1.500167)
|
||||
(xy 4.499983 1.500167)
|
||||
(xy 4.499983 1.250053)
|
||||
(xy 4.249869 1.250053)
|
||||
(xy 3.999755 1.250053)
|
||||
(xy 3.999755 0.999939)
|
||||
(xy 4.750097 0.999939)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 3d4db89c-b5bd-4689-87d8-3730cf8df8f4))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 4.499999 6.499999)
|
||||
(xy 4.249999 6.749999)
|
||||
(xy 3.849999 6.749999)
|
||||
(xy 3.749999 6.849998)
|
||||
(xy 3.749999 8.999998)
|
||||
(xy 3.499999 8.999998)
|
||||
(xy 3.499999 6.749999)
|
||||
(xy 3.749999 6.499999)
|
||||
(xy 4.149999 6.499999)
|
||||
(xy 4.249999 6.399999)
|
||||
(xy 4.249999 6.249999)
|
||||
(xy 4.499999 6.249999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp f8a10a30-88d4-4521-a785-068b4a34a6b4))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 5.099999 3.949999)
|
||||
(xy 5.099999 4.299999)
|
||||
(xy 4.799999 4.599999)
|
||||
(xy 4.499999 4.599999)
|
||||
(xy 4.499999 4.399999)
|
||||
(xy 4.749999 4.399999)
|
||||
(xy 4.899999 4.249999)
|
||||
(xy 4.899999 3.999999)
|
||||
(xy 4.749999 3.849999)
|
||||
(xy 1.25 3.849999)
|
||||
(xy 1.25 3.649999)
|
||||
(xy 4.799999 3.649999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp fafbca33-bd8b-4e58-9b6e-99199a1e20ef))
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy 5.499999 6.499999)
|
||||
(xy 5.999999 6.499999)
|
||||
(xy 6.013914 6.50029)
|
||||
(xy 6.027526 6.501159)
|
||||
(xy 6.040827 6.502595)
|
||||
(xy 6.053808 6.504589)
|
||||
(xy 6.066459 6.507133)
|
||||
(xy 6.078771 6.510216)
|
||||
(xy 6.090735 6.513831)
|
||||
(xy 6.102343 6.517968)
|
||||
(xy 6.113584 6.522617)
|
||||
(xy 6.12445 6.52777)
|
||||
(xy 6.134931 6.533417)
|
||||
(xy 6.145019 6.53955)
|
||||
(xy 6.154703 6.546158)
|
||||
(xy 6.163976 6.553234)
|
||||
(xy 6.172828 6.560767)
|
||||
(xy 6.181249 6.568749)
|
||||
(xy 6.189231 6.57717)
|
||||
(xy 6.196764 6.586022)
|
||||
(xy 6.20384 6.595295)
|
||||
(xy 6.210448 6.604979)
|
||||
(xy 6.216581 6.615067)
|
||||
(xy 6.222228 6.625548)
|
||||
(xy 6.227381 6.636414)
|
||||
(xy 6.23203 6.647655)
|
||||
(xy 6.236167 6.659262)
|
||||
(xy 6.239782 6.671227)
|
||||
(xy 6.242866 6.683539)
|
||||
(xy 6.245409 6.69619)
|
||||
(xy 6.247404 6.709171)
|
||||
(xy 6.248839 6.722472)
|
||||
(xy 6.249708 6.736084)
|
||||
(xy 6.249999 6.749999)
|
||||
(xy 6.249999 8.999998)
|
||||
(xy 5.999999 8.999998)
|
||||
(xy 5.999999 6.749999)
|
||||
(xy 5.499999 6.749999)
|
||||
(xy 5.486085 6.749707)
|
||||
(xy 5.472472 6.748839)
|
||||
(xy 5.459171 6.747403)
|
||||
(xy 5.446191 6.745409)
|
||||
(xy 5.43354 6.742865)
|
||||
(xy 5.421227 6.739781)
|
||||
(xy 5.409263 6.736167)
|
||||
(xy 5.397655 6.73203)
|
||||
(xy 5.386414 6.727381)
|
||||
(xy 5.375549 6.722228)
|
||||
(xy 5.365067 6.71658)
|
||||
(xy 5.35498 6.710448)
|
||||
(xy 5.345295 6.703839)
|
||||
(xy 5.336022 6.696764)
|
||||
(xy 5.327171 6.689231)
|
||||
(xy 5.318749 6.681249)
|
||||
(xy 5.310767 6.672828)
|
||||
(xy 5.303234 6.663976)
|
||||
(xy 5.296159 6.654703)
|
||||
(xy 5.28955 6.645018)
|
||||
(xy 5.283417 6.634931)
|
||||
(xy 5.27777 6.62445)
|
||||
(xy 5.272617 6.613584)
|
||||
(xy 5.267968 6.602343)
|
||||
(xy 5.263831 6.590735)
|
||||
(xy 5.260216 6.578771)
|
||||
(xy 5.257133 6.566459)
|
||||
(xy 5.254589 6.553808)
|
||||
(xy 5.252595 6.540827)
|
||||
(xy 5.251159 6.527526)
|
||||
(xy 5.25029 6.513914)
|
||||
(xy 5.249999 6.499999)
|
||||
(xy 5.249999 6.249999)
|
||||
(xy 5.499999 6.249999)
|
||||
)
|
||||
|
||||
(stroke (width 0) (type solid)) (fill solid) (layer "F.Cu") (tstamp 2e49765d-7fab-447c-af5f-c96b846f80fb))
|
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(fp_poly
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(pts
|
||||
(xy 5.39343 1.00039)
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(xy 5.430234 1.004022)
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(xy 5.448371 1.007178)
|
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(xy 5.466289 1.01121)
|
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(xy 5.483958 1.016105)
|
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(xy 5.501347 1.021851)
|
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(xy 5.518425 1.028435)
|
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(xy 5.535162 1.035845)
|
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(xy 5.551527 1.044066)
|
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(xy 5.567488 1.053088)
|
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(xy 5.583016 1.062896)
|
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(xy 5.598079 1.073479)
|
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(xy 5.612646 1.084823)
|
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(xy 5.626688 1.096916)
|
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(xy 5.640172 1.109744)
|
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(xy 5.653004 1.123226)
|
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(xy 5.6651 1.137264)
|
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(xy 5.676447 1.15183)
|
||||
(xy 5.687033 1.166891)
|
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(xy 5.696845 1.182417)
|
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(xy 5.70587 1.198377)
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(xy 5.721508 1.231478)
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(xy 5.750036 1.37511)
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(xy 5.749531 1.3944)
|
||||
(xy 5.748066 1.413437)
|
||||
(xy 5.745665 1.432196)
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