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54 Commits

Author SHA1 Message Date
King Kévin f57ff3efbf doc: define aka 2022-08-03 19:28:11 +02:00
King Kévin 42c66d8e8d doc: add LED picture 2022-08-03 19:22:49 +02:00
King Kévin c612d14f28 doc: add pictures 2022-08-03 19:17:14 +02:00
King Kévin 78ecab5ddb doc: document v1 changes 2022-08-03 18:24:35 +02:00
King Kévin dab8953f24 lib: update repo 2022-08-03 18:21:43 +02:00
King Kévin 8316ebf0a6 dox: minor, fix typo 2022-08-03 18:20:40 +02:00
King Kévin fbafd1be95 doc: fix some part position 2022-08-03 18:20:18 +02:00
King Kévin 4fc91d84c5 sch: add position correction 2022-07-12 13:05:30 +02:00
King Kévin c79b4ab42f add position correction 2022-07-12 13:05:16 +02:00
King Kévin 3dea8bc9e9 make: make panel fab first 2022-07-12 13:04:44 +02:00
King Kévin 7c2fe380a0 brd: fix text width 2022-07-12 11:41:24 +02:00
King Kévin 446ef18cdb brd: improve version position 2022-07-12 11:38:30 +02:00
King Kévin 546b488a96 brd: improve back text position 2022-07-12 11:37:01 +02:00
King Kévin 73402d026d make: replace Rakefile with Makefile 2022-07-12 11:36:31 +02:00
King Kévin bd1c7192bb sch/brd: fix ground pad 2022-07-12 11:15:58 +02:00
King Kévin b78607e24d brd: fix exceeding silk outline 2022-06-20 10:13:14 +02:00
King Kévin 13ea982cd3 brd: add project silk 2022-06-19 19:22:46 +02:00
King Kévin 251b559d8c lib: add QR code 2022-06-19 19:22:18 +02:00
King Kévin 925563c205 brd: fix paste and mask 2022-06-19 18:45:46 +02:00
King Kévin 17269abf1a brd: set 3d models 2022-06-19 18:28:50 +02:00
King Kévin bc3e43678d lib: add manufacturer 3d model 2022-06-19 18:28:19 +02:00
King Kévin 810700b8d1 rake: add clean temporary files 2022-06-19 17:44:30 +02:00
King Kévin 7808946e18 rake: add BoM configuration 2022-06-19 17:44:03 +02:00
King Kévin 0a65e91714 rake: fix cleaning 2022-06-19 17:36:02 +02:00
King Kévin 9ec8c983ca rake: fix panel rule 2022-06-19 17:34:10 +02:00
King Kévin a0f08f9990 sch: complete bom 2022-06-19 17:10:19 +02:00
King Kévin 192acbbc6c brd: prepare for panelization 2022-06-19 17:09:56 +02:00
King Kévin 5842c7490e brd: route simplified shield test 2022-06-19 15:30:05 +02:00
King Kévin 210e9e87c0 sch: minor, improve routing 2022-06-19 15:29:39 +02:00
King Kévin 08e6e8d3b5 sch: simplify shield test 2022-06-19 15:17:18 +02:00
King Kévin 5c51182ee9 lib: add kikit footprints 2022-06-18 14:17:25 +02:00
King Kévin 9f50a52588 add script to move refdes to fab layer 2022-06-18 14:17:05 +02:00
King Kévin 88810ccf08 brd: complete first layout 2022-06-18 14:16:32 +02:00
King Kévin 0ed3579c68 sch: complete first schematic 2022-06-18 14:15:55 +02:00
King Kévin 4c1005707f lib: add custom footprint 2022-06-18 14:15:23 +02:00
King Kévin 21cf9c74bd lib: add used parts 2022-06-18 14:14:50 +02:00
King Kévin 540f27afdb restart with KiCAD 2022-06-17 19:41:42 +02:00
King Kévin aad492c792 switch to v1 to improve design 2022-06-17 19:33:58 +02:00
King Kévin 33b088383f doc: document v0 results 2022-06-17 19:13:55 +02:00
King Kévin cd4c29b84e README: document purpose and usage 2022-05-28 12:33:12 +02:00
King Kévin 0ab779a7bd lib: update parts 2022-05-28 11:37:31 +02:00
King Kévin 830da6b035 brd: minor, fix solder paste 2022-05-18 18:04:48 +02:00
King Kévin f6ed534754 brd: minor, improve text position 2022-05-18 17:56:15 +02:00
King Kévin c4d6214036 sch: minor, fix bom 2022-05-18 17:50:55 +02:00
King Kévin d2d73c2e35 brd: fix NPTH 2022-05-18 17:43:55 +02:00
King Kévin faebf25036 brd: more compact re-design 2022-05-18 17:43:55 +02:00
King Kévin b4dcd69a7d sch: change for more compact routing 2022-05-18 17:43:55 +02:00
King Kévin 97c8d478c1 brd: first completed routing 2022-05-18 17:43:55 +02:00
King Kévin 29c8154bf1 sch: minor, change for routing 2022-05-18 17:43:55 +02:00
King Kévin d53d1c8352 sch: first finished draft 2022-05-18 17:43:55 +02:00
King Kévin 829a3a0ed6 lib: add exported footprints 2022-05-18 17:43:55 +02:00
King Kévin bdc290f380 lib: add used symbols 2022-05-18 17:43:55 +02:00
King Kévin b513cdae95 lib: add used parts 2022-05-18 17:43:55 +02:00
King Kévin 5b4ef20513 name project 2022-05-18 17:43:55 +02:00
58 changed files with 87465 additions and 3515 deletions

46
.gitignore vendored
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@ -1,31 +1,35 @@
# schematic lepton-EDA
*.sch
# board layout pcb-rnd
*.lht
*.lht.*
*.versioned.lht
# KiCAD
*.kicad_prl
*.kicad_pro-bak
*.xml
fp-info-cache
# temporary files
*~
*.versioned.sch
\#*\#
# outputs
*.svg
*.png
*.pdf
*.ps
*.zip
*.brd.*
*.ast
*.g2l
*.g3l
*.gbl
*.gbo
*.gbp
*.gbs
*.gko
*.gtl
*.gto
*.gtp
*.gts
*.xln
*.tdx
\#*\#
*.notes.txt
*.bom.csv
*.cost.csv
*.cpl.csv
*.versioned.*
fabrication
# scripts and utilities
*.json
*.rb
geda/footprints/
# panel files
panel.*
panel

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@ -1,5 +1,6 @@
config:
output: coraleda
nodate: true
output: kicad
pattern:
densityLevel: 'N'
lineWidth:
@ -8,3 +9,10 @@ config:
preferManufacturer: false
smoothPadCorners: false
library:
- resistor/r0603
- diode/led0805
- connector/battery_my-1220-03
- transistor/nmos_bss138
- transistor/pmos_nxp_bss84
- connector/usb-c_xkb_u262-24xn-4bv64
- connector/usb-a-3.0_xkb_u231-09xn-4blra00

17
CHANGELOG.md Normal file
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@ -0,0 +1,17 @@
v1
==
fixes v0 short comings:
- shield LED is on when both shell are interconnected and connected to ground (the cable could cheat by just connecting both shells directly to ground)
- all GND and VBUS pins of USB-C are used
v0
==
first prototype build.
it works, but almost only on specification compliant cables:
- some cables don't have all 4 GND and VBUS pins in the C plug
- normally the shield should connect both shells AND be tied to ground on BOTH ends, but I've seen ALL possible combinations thereof

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@ -1,19 +1,23 @@
this will describe how to generate the output file form the sources.
this will describe how to generate the output files form the sources.
requirements
============
to be able to generate the outputs you need following software:
to be able to generate the outputs, you need following software:
- rake: the central script taking care of generating the output files (Makefile is too cumbersome to parse files)
- [QEDA](http://qeda.org/): to generate footprints for the parts
- [Lepton EDA](https://github.com/lepton-eda/lepton-eda): for the schematic capture
- [pcb-rnd](http://repo.hu/projects/pcb-rnd/): for the board layout
the output generation is automatized.
- [KiCad](https://www.kicad.org/): EDA software used for schematic capture and board layout
- [PcbDraw](https://github.com/yaqwsx/PcbDraw): to generate board layout rendering
- [KiKit](https://github.com/yaqwsx/KiKit): to generate fabrications files (Gerber, Excellon)
- [KiAuto](https://github.com/INTI-CMNB/KiAuto): to generate schematic printout (PDF)
- [KiBoM](https://github.com/SchrodingersGat/KiBoM): to generate Bill of Material (CSV)
compiling
=========
to generate schematic, BoM, board render, and fabrication output, run `rake`.
library
-------
@ -38,18 +42,15 @@ to generate the parts:
rake library
~~~
this will use the parts definition (.yaml files) in the `library` to generate [gEDA gschem](http://wiki.geda-project.org/geda:gaf)/[Lepton EDA](https://github.com/lepton-eda/lepton-eda) symbols (.sym files) in the `geda/symbols` folder, and [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/) footprints (.lht files) in the `coraleda/subc` folder.
only the QEDA parts in subfolders within `library` come from the [QEDA library](https://doc.qeda.org/library/), but the files are included in this project for simplicity and archiving purposes.
all other parts are custom and written for this project.
this will use the parts definition (.yaml files) in the `library` to generate the symbols (.sym files) and footprints used by KiCAD in the `kicad` folder.
schematic
---------
the `.sch` file is the schematic source file.
it has been drawn using [Lepton EDA](https://github.com/lepton-eda/lepton-eda).
the `.kicad_sch` file is the schematic source file.
it has been drawn using the [KiCAD eeschema](https://www.kicad.org/) schematic editor.
it uses standard symbols, and the ones in the `geda/symbols/` folder.
it uses standard symbols, and the ones in the `kicad/` folder.
most symbols are generated by QEDA as described above.
to export as pdf:
@ -68,15 +69,25 @@ rake bom
board
-----
the `.lht` file is the board layout source file.
it has been drawn using [coralEDA pcb-rnd](http://repo.hu/projects/pcb-rnd/).
the `.kicad_brd` file is the board layout source file.
it has been drawn using the [KiCAD pcbnew](https://docs.kicad.org/6.0/en/pcbnew/pcbnew.html) PCB editor.
it uses the symbols from the `coraleda/subc/` folder.
it uses the footprints from the `kicad/` folder.
most symbols are generated by QEDA as described above.
`oshw_logo.lht` is just the Open Source Hardware Logo.
it been generated from https://oshwlogo.cuvoodoo.info/.
to export gerber files for PCB manufacturer (and photo preview + overview document):
~~~
rake fabrication
~~~
versioning
----------
the source schematic and board layout do not include version information.
when generating schematic or board fabrication output, a copy of the source files with date and version information is done as `.versioned.` files.
the date corresponds to the last changes (i.e. commit).
the version is formatted as `v.r hhhhhhh`:
- `v` corresponds to the major version information defined in `version`
- `r` corresponds to the total number of changes done to the source files
- `hhhhhhh` corresponds to the git hash of the commit used to generate the version information

7
JLCPCB_CORRECTION.csv Normal file
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package;x;y;rot
LEDC2012X80N;0;0;-90
UC1608X55N;0;0;90
SOT95P237X112-3N;0;0;180
CONNECTOR_MY-1220-03;0;-1.1;0
CONNECTOR_XKB_U262-24XN-4BV64;0;-1.3;180
CONNECTOR_U231-09XN-4BLRA00;0;-3.0;0
1 package x y rot
2 LEDC2012X80N 0 0 -90
3 UC1608X55N 0 0 90
4 SOT95P237X112-3N 0 0 180
5 CONNECTOR_MY-1220-03 0 -1.1 0
6 CONNECTOR_XKB_U262-24XN-4BV64 0 -1.3 180
7 CONNECTOR_U231-09XN-4BLRA00 0 -3.0 0

71
Makefile Normal file
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# project file name (use for schematic and board layout)
NAME ?= usb-ac_cable_tester
# path to qeda
QEDA := qeda
# read project version
VERSION := $(shell cat version)
# current date for stamping output
DATE = $(shell date +%Y-%m-%d)
# revision based on number of changes on schematic or board layout and current git commit
REVISION := $(shell git log --pretty=oneline "${NAME}.kicad_sch" "${NAME}.kicad_pcb" | wc -l)
# generate file with version information
VERSIONED_EXT = kicad_sch kicad_pcb kicad_pro json
define version_rule
%.versioned.$1: %.$1
cp $$< $$@
sed --in-place 's/\$$$$version\$$$$/${VERSION}/g' $$@
sed --in-place 's/\$$$$date\$$$$/${DATE}/g' $$@
sed --in-place 's/\$$$$revision\$$$$/${REVISION}/g' $$@
endef
$(foreach EXT,$(VERSIONED_EXT),$(eval $(call version_rule,$(EXT))))
all: print fabrication
print: ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.bom.csv
# generate fabrication files (gerbers/drill/BoM/PnP)
FABRICATION_DIR := fabrication
fabrication: ${NAME}.versioned.kicad_sch ${NAME}.versioned.kicad_pcb
kikit fab jlcpcb --drc --assembly --schematic $^ ${FABRICATION_DIR}
# generate symbols and footprints from parts
lib:
$(QEDA) generate qeda
# generate printable version (PDF) of schematic
%.sch.pdf: %.versioned.kicad_sch %.versioned.kicad_pro
eeschema_do export $< .
mv $*.versioned.pdf $@
# generate render from layout (top side)
%.brd-top.png: %.versioned.kicad_pcb
pcbdraw --silent $< --dpi 600 $@
# generate render from layout (bottom side)
%.brd-bot.png: %.versioned.kicad_pcb
pcbdraw --silent $< --dpi 600 --back $@
# export Bill of Material (as CSV)
%.bom.csv: %.versioned.kicad_sch %.versioned.kicad_pro
eeschema_do bom_xml $< .
kibom $*.versioned.xml $@
# generate panel
PANEL_DIR := panel
panel: panel.kicad_pcb
panel.kicad_pcb: ${NAME}.versioned.kicad_pcb ${NAME}.versioned.kicad_pro ${NAME}.versioned.kicad_sch ${NAME}.versioned.json
kikit panelize -p ${NAME}.versioned.json ${NAME}.versioned.kicad_pcb $@
sed --in-place 's/\"missing_courtyard\": \"warning\"/\"missing_courtyard\": \"ignore\"/g' $(patsubst %.kicad_pcb,%.kicad_pro,$@) # the mouse bites don't have a courtyard
kikit fab jlcpcb --drc --assembly --missingError --schematic ${NAME}.versioned.kicad_sch $@ ${PANEL_DIR}
pcbdraw --silent $@ --dpi 600 panel.brd-top.png
pcbdraw --silent $@ --dpi 600 --back panel.brd-bot.png
clean:
rm -f $(foreach EXT,$(VERSIONED_EXT),${NAME}.versioned.$(EXT))
rm -f ${NAME}.sch.pdf ${NAME}.brd-top.png ${NAME}.brd-bot.png ${NAME}.versioned.xml ${NAME}.bom.csv
rm -f ${NAME}.versioned.kicad_prl ${NAME}.versioned.kicad_pro-bak ${NAME}.versioned.xml ${NAME}.versioned.csv
rm -rf ${FABRICATION_DIR}
rm -f panel.kicad_pcb panel.kicad_pro
rm -rf ${PANEL_DIR}

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@ -1,7 +1,30 @@
these are the hardware design files for **insert project name here**.
The USB-A to USB-C (aka. USB-AC) cable tester shows which features a USB-A to USB-C cable supports.
<img src="picture/front_v1.webp" title="front" height="250"/>
<img src="picture/back_v1.webp" title="back" height="250"/>
<img src="picture/leds_v1.webp" title="LEDs" height="250"/>
purpose
=======
Devices using the USB-C connector become more common, but most computer hosts still use USB Type-A (aka. USB-A) connectors.
Thus USB-A to USB-C cable get widespread.
But there is no indication on the cable about its intended usage: just power or charge the device, also allow data transfer, or even support fast data transfer.
The USB-AC cable tester identifies the capabilities of USB-A to USB-C cables.
usage
=====
The USB-AC cable tester is powered by a CR1220 coin cell battery.
Plug both ends of the USB-A to USB-C cable in the USB-AC cable tester and read the lights:
- POWER: can be use to power a device (the VBUS and GND wires are present).
- USB 2.0: can be use for USB 2.0 data transfer (the D+ and D- wires are present).
- SHIELD: the cable is shielded, important for USB 3.0 Super Speed data transfer.
- USB 3.x: can be used for USB 3.0 Super Speed (SS) data transfer (the 2 differential pairs are present).
- Rp: the Rp pull-up resistor is present, required for USB-C orientation detection. Without Rp, the device might not turn on, or data transfer to normal or super speed might not be possible.
Fast charging: when connecting two USB-C devices, Rp is used by the source (e.g. host) to indicate to the sink (e.g. device) how much power it can draw (up to 0.5, 0.9, 1.5, or 3.0A).
This capability is not supported by USB-A to USB-C cables, which restrict to the default USB power capabilities (0.5A for USB 2.0, 0.9A for USB 3.x).
USB-C Power Delivery is also not possible using such cables.
USB Battery Charging (BC) and other proprietary charging standards using the USB data lines might still be possible, but depend on the charger, and is outside the scope of this tester.

181
Rakefile
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@ -1,181 +0,0 @@
# encoding: utf-8
# ruby: 2.1.0
=begin
Rakefile to manage hardware projects
uses Lepton EDA for schematic and pcb-rnd for board layouts.
Rakefile instead of Makefile for better text file parsing capabilities.
=end
require 'rake/clean'
require 'csv' # to export BOM and costs
# =================
# project variables
# =================
# common name used for file names
name = "template"
# project version, read from "version" file
raise "define project version in 'version' file" unless File.exist? "version"
version = IO.read("version").split("\n")[0]
# current date for stamping output
date = Time.now.strftime("%Y-%m-%d")
# revision based on number of changes on schematic or board layout and current git commit
changes = `git log --pretty=oneline "#{name}.sch" "#{name}.lht" | wc -l`.chomp.to_i
commit = `git rev-parse --short HEAD`.chomp
revision = "#{changes} (#{commit})"
# path to qeda"
qeda = "qeda"
# ==========
# main tasks
# ==========
desc "main building task"
task :default => [:print, :fabrication, :bom, :pnp]
desc "print schematic and layout (as pdf)"
prints = [ "#{name}.sch.pdf", "#{name}.brd.pdf", "#{name}.brd-top.svg", "#{name}.brd-bottom.svg" ]
task :print => prints
CLEAN.include([ "#{name}.versioned.sch", "#{name}.versioned.lht" ])
CLOBBER.include(prints)
desc "generate fabrication gerbers (as archive)"
gerbers = [ "#{name}.brd.asb", "#{name}.brd.ast", "#{name}.brd.gbl", "#{name}.brd.gbo", "#{name}.brd.gbp", "#{name}.brd.gbs", "#{name}.brd.gko", "#{name}.brd.gtl", "#{name}.brd.gto", "#{name}.brd.gtp", "#{name}.brd.gts", "#{name}.brd.xln", "#{name}.brd.g2l", "#{name}.brd.g3l" ]
fab = [ "#{name}.brd.zip" ]
task :fabrication => fab
CLEAN.include(gerbers)
CLOBBER.include(fab)
desc "generate symbols and footprints from parts"
task :library do
sh "#{qeda} config output geda"
sh "#{qeda} generate ."
sh "#{qeda} config output coraleda"
sh "#{qeda} generate ."
end
desc "export BOMs from schematic"
boms = [ "#{name}.bom.csv" ]
task :bom => boms
CLOBBER.include(boms)
desc "export PnP placement"
pnps = [ "#{name}.cpl.csv" ]
task :pnp => pnps
CLOBBER.include(pnps)
# ===============
# file generation
# ===============
desc "generate schematic with version information all symbols embedded"
rule ".versioned.sch" => ".sch" do |t|
sh "cp #{t.source} #{t.name}"
sh "lepton-embed --embed #{t.name} 2> /dev/null"
sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
end
desc "generate board layout with version information"
rule ".versioned.lht" => ".lht" do |t|
sh "cp #{t.source} #{t.name}"
sh "sed --in-place 's/\\$version\\$/#{version}/' #{t.name}"
sh "sed --in-place 's/\\$date\\$/#{date}/' #{t.name}"
sh "sed --in-place 's/\\$revision\\$/#{revision}/' #{t.name}"
end
desc "generate printable version (PDF) of schematic"
rule ".sch.pdf" => ".versioned.sch" do |t|
sh "lepton-cli export --color --paper=iso_a4 --layout=landscape --output=#{t.name} #{t.source} 2> /dev/null"
end
desc "generate printable version (PostScript) of board layout"
rule ".brd.ps" => ".versioned.lht" do |t|
sh "pcb-rnd -x ps --ps-color --media A4 --psfile #{t.name} #{t.source} 2> /dev/null"
end
desc "generate printable version (PDF) of board layout"
rule ".brd.pdf" => ".brd.ps" do |t|
sh "ps2pdf -sPAPERSIZE=a4 -dEPSCrop #{t.source} #{t.name}"
end
desc "generate photo realistic picture from layout (top side)"
rule ".brd-top.svg" => ".versioned.lht" do |t|
sh "pcb-rnd -x svg --photo-mode --outfile #{t.name} #{t.source} 1> /dev/null"
end
desc "generate photo realistic picture from layout (bottom side)"
rule ".brd-bottom.svg" => ".versioned.lht" do |t|
sh "pcb-rnd -x svg --photo-mode --flip --outfile #{t.name} #{t.source} 1> /dev/null"
end
desc "archive gerbers"
rule ".brd.zip" => ".versioned.lht" do |t|
base = File.basename(t.source, ".versioned.lht")
dir = "fabrication"
sh "mkdir #{dir}" unless File.directory?(dir)
sh "pcb-rnd -x cam gerber:JLC_PCB --outfile #{dir}/#{base}.brd #{t.source} 2> /dev/null"
sh "zip --quiet #{t.name} #{dir}/*"
end
desc "generate BOM file from schematic"
rule ".bom.csv" => ".sch" do |t|
attributes = ["device", "value", "description", "footprint", "manufacturer", "mpn", "datasheet", "lcsc", "digikey"]
bom_data = bom2(t.prerequisites[0], attributes)
CSV.open(t.name, "wb") do |csv|
all_attributes = ["refdes","qty"] + attributes
csv << all_attributes
bom_data.each do |line|
csv << all_attributes.collect{|attribute| line[attribute]}
end
end
end
desc "generate pick-and-place file from board"
rule ".cpl.csv" => [".versioned.lht", "mass_prop.sh", "pnp_fab.tab"] do |t|
sh "./mass_prop.sh #{t.prerequisites[0]} pnp_fab.tab" # add fab placement offsets
sh "pcb-rnd -x XY --xyfile #{t.name} --xy-unit mm --format 'JLCPCB' --vendor jlcpcb #{t.prerequisites[0]}" # export XY file in JLCPCB format
end
# ================
# helper functions
# ================
# generate gnetlist bom2 and parse them
# arguments: schematic=schematic to use, attributes=attributes to use for generating bom2
# returns an array of hash. key is the attribute name, value is the attribute value
def bom2(schematic, attributes)
to_return = []
# force attributes to be an array
attributes = case attributes
when String
[attributes]
when Array
attributes
else
[attributes.to_s]
end
# generate bom2
list = `lepton-netlist --backend bom2 --backend-option attribs=#{attributes*','} --quiet --output - #{schematic} 2> /dev/null`
list = list.each_line {|l| '"' + l + '"' + '\n' }
list.gsub!(/^(.+)/, '"\1')
list.gsub!(/(.+)$/, '\1"')
list.gsub!(/(?!http):(?!\/\/)/, '\1":"\2') # protect the values between ':' (such as URLs)
# parse bom2
csv = CSV.parse(list, col_sep: ":", quote_char: '"')
if csv.empty? then
$stderr.puts "no parts found for BOM"
return []
end
csv[1..-1].each do |row|
line = {}
row.each_index do |col|
line[csv[0][col]] = row[col] unless row[col] == "unknown"
end
to_return << line
end
return to_return
end

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bom.ini Normal file
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[BOM_OPTIONS]
; General BoM options here
; If 'ignore_dnf' option is set to 1, rows that are not to be fitted on the PCB will not be written to the BoM file
ignore_dnf = 1
; If 'html_generate_dnf' option is set to 1, also generate a list of components not fitted on the PCB (HTML only)
html_generate_dnf = 1
; If 'use_alt' option is set to 1, grouped references will be printed in the alternate compressed style eg: R1-R7,R18
use_alt = 0
; If 'number_rows' option is set to 1, each row in the BoM will be prepended with an incrementing row number
number_rows = 1
; If 'group_connectors' option is set to 1, connectors with the same footprints will be grouped together, independent of the name of the connector
group_connectors = 1
; If 'test_regex' option is set to 1, each component group will be tested against a number of regular-expressions (specified, per column, below). If any matches are found, the row is ignored in the output file
test_regex = 1
; If 'merge_blank_fields' option is set to 1, component groups with blank fields will be merged into the most compatible group, where possible
merge_blank_fields = 1
; Specify output file name format, %O is the defined output name, %v is the version, %V is the variant name which will be ammended according to 'variant_file_name_format'.
output_file_name = %O
; Specify the variant file name format, this is a unique field as the variant is not always used/specified. When it is unused you will want to strip all of this.
variant_file_name_format = _(%V)
; Field name used to determine if a particular part is to be fitted
fit_field = Config
; Complex variant processing (disabled by default)
complex_variant = 0
; Character used to separate reference designators in output
ref_separator = ' '
; Make a backup of the bom before generating the new one, using the following template
make_backup = %O.tmp
; Put the datasheet as a link for the following field
datasheet_as_link =
; Default number of boards to produce if none given on CLI with -n
number_boards = 1
; Default PCB variant if none given on CLI with -r
board_variant = default
; If 'complex_variant' option is set to 1, the complex variant field processing is enabled
; If 'hide_headers' option is set to 1, column headers aren't included in the output file
hide_headers = 0
; If 'hide_pcb_info' option is set to 1, PCB info isn't included in the output file
hide_pcb_info = 0
; Interpret as a Digikey P/N and link the following field
digikey_link =
[IGNORE_COLUMNS]
; Any column heading that appears here will be excluded from the Generated BoM
; Titles are case-insensitive
part lib
footprint lib
sheetpath
JLCPCB_CORRECTION
[COLUMN_ORDER]
; Columns will appear in the order they are listed here
; Titles are case-insensitive
Description
Part
Part Lib
References
Value
Footprint
Footprint Lib
Quantity Per PCB
Build Quantity
Datasheet
[GROUP_FIELDS]
; List of fields used for sorting individual components into groups
; Components which match (comparing *all* fields) will be grouped together
; Field names are case-insensitive
Part
Part Lib
Value
Footprint
Footprint Lib
[COMPONENT_ALIASES]
; A series of values which are considered to be equivalent for the part name
; Each line represents a list of equivalent component name values separated by a tab
; e.g. 'c c_small cap' will ensure the equivalent capacitor symbols can be grouped together
; Aliases are case-insensitive
c c_small cap capacitor
r r_small res resistor
sw switch
l l_small inductor
zener zenersmall
d diode d_small
[JOIN]
; A list of rules to join the content of fields
; Each line is a rule, the first name is the field that will receive the data
; from the other fields
; Use tab (ASCII 9) as separator
; Field names are case sensitive
[REGEX_INCLUDE]
; A series of regular expressions used to include parts in the BoM
; If there are any regex defined here, only components that match against ANY of them will be included in the BOM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (separated by a tab)
[COLUMN_RENAME]
; A list of columns to be renamed
; Format is: "[ColumName] [NewName]" (separated by a tab)
[REGEX_EXCLUDE]
; A series of regular expressions used to exclude parts from the BoM
; If a component matches ANY of these, it will be excluded from the BoM
; Column names are case-insensitive
; Format is: "[ColumName] [Regex]" (separated by a tab)
References ^TP[0-9]*
References ^FID
Part mount.*hole
Part solder.*bridge
Part test.*point
Footprint test.*point
Footprint mount.*hole
Footprint fiducial

View File

@ -1,421 +0,0 @@
# footprint generated from CuVoodoo Land Pattern
# author: King Kévin
# version: 1
# date: 2019-05-13
li:pcb-rnd-subcircuit-v6 {
ha:subc.1 {
uid = any_24_ASCII_characters_
ha:attributes {
footprint = open source hardware logo
}
ha:data {
li:padstack_prototypes {
}
li:objects {
}
li:layers {
ha:top-silkscreen {
lid = 1
ha:type {
top = 1
silk = 1
}
li:objects {
ha:line.2{
clearance = 0
x1 = 0.15mm
y1 = 1.8mm
x2 = 0.75mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.3{
clearance = 0
x1 = 1.8mm
y1 = 5.8500000000000005mm
x2 = 1.8mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.4{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 1.8mm
x2 = 6.45mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.5{
clearance = 0
x1 = 1.8mm
y1 = 0.15mm
x2 = 1.8mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.6{
clearance = 0
x1 = 0.15mm
y1 = 2.4mm
x2 = 0.75mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.7{
clearance = 0
x1 = 2.4mm
y1 = 5.8500000000000005mm
x2 = 2.4mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.8{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 2.4mm
x2 = 6.45mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.9{
clearance = 0
x1 = 2.4mm
y1 = 0.15mm
x2 = 2.4mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.10{
clearance = 0
x1 = 0.15mm
y1 = 3mm
x2 = 0.75mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.11{
clearance = 0
x1 = 3mm
y1 = 5.8500000000000005mm
x2 = 3mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.12{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 3mm
x2 = 6.45mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.13{
clearance = 0
x1 = 3mm
y1 = 0.15mm
x2 = 3mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.14{
clearance = 0
x1 = 0.15mm
y1 = 3.5999999999999996mm
x2 = 0.75mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
ha:line.15{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 5.8500000000000005mm
x2 = 3.5999999999999996mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.16{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 3.5999999999999996mm
x2 = 6.45mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
ha:line.17{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 0.15mm
x2 = 3.5999999999999996mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.18{
clearance = 0
x1 = 0.15mm
y1 = 4.2mm
x2 = 0.75mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.19{
clearance = 0
x1 = 4.2mm
y1 = 5.8500000000000005mm
x2 = 4.2mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.20{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 4.2mm
x2 = 6.45mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.21{
clearance = 0
x1 = 4.2mm
y1 = 0.15mm
x2 = 4.2mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.22{
clearance = 0
x1 = 0.15mm
y1 = 4.8mm
x2 = 0.75mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.23{
clearance = 0
x1 = 4.8mm
y1 = 5.8500000000000005mm
x2 = 4.8mm
y2 = 6.45mm
thickness = 0.3mm
}
ha:line.24{
clearance = 0
x1 = 5.8500000000000005mm
y1 = 4.8mm
x2 = 6.45mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.25{
clearance = 0
x1 = 4.8mm
y1 = 0.15mm
x2 = 4.8mm
y2 = 0.75mm
thickness = 0.3mm
}
ha:line.26{
clearance = 0
x1 = 1.8mm
y1 = 1.35mm
x2 = 4.8mm
y2 = 1.35mm
thickness = 0.3mm
}
ha:line.27{
clearance = 0
x1 = 5.25mm
y1 = 1.8mm
x2 = 5.25mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.28{
clearance = 0
x1 = 4.8mm
y1 = 5.25mm
x2 = 1.8mm
y2 = 5.25mm
thickness = 0.3mm
}
ha:line.29{
clearance = 0
x1 = 1.35mm
y1 = 4.8mm
x2 = 1.35mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:arc.30{
clearance = 0
x = 1.8mm
y = 1.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 0
adelta = -90
}
ha:arc.31{
clearance = 0
x = 4.8mm
y = 1.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = -90
adelta = -90
}
ha:arc.32{
clearance = 0
x = 4.8mm
y = 4.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 180
adelta = -90
}
ha:arc.33{
clearance = 0
x = 1.8mm
y = 4.8mm
width = 0.45mm
height = 0.45mm
thickness = 0.3mm
astart = 90
adelta = -90
}
ha:line.34{
clearance = 0
x1 = 1.8mm
y1 = 1.8mm
x2 = 3mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.35{
clearance = 0
x1 = 3mm
y1 = 1.8mm
x2 = 3mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.36{
clearance = 0
x1 = 3mm
y1 = 3mm
x2 = 1.8mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.37{
clearance = 0
x1 = 1.8mm
y1 = 3mm
x2 = 1.8mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.38{
clearance = 0
x1 = 4.8mm
y1 = 1.8mm
x2 = 3.5999999999999996mm
y2 = 1.8mm
thickness = 0.3mm
}
ha:line.39{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 1.8mm
x2 = 3.5999999999999996mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.40{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 2.4mm
x2 = 4.8mm
y2 = 2.4mm
thickness = 0.3mm
}
ha:line.41{
clearance = 0
x1 = 4.8mm
y1 = 2.4mm
x2 = 4.8mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.42{
clearance = 0
x1 = 4.8mm
y1 = 3mm
x2 = 3.5999999999999996mm
y2 = 3mm
thickness = 0.3mm
}
ha:line.43{
clearance = 0
x1 = 1.8mm
y1 = 3.5999999999999996mm
x2 = 1.8mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.44{
clearance = 0
x1 = 1.8mm
y1 = 4.199999999999999mm
x2 = 3mm
y2 = 4.199999999999999mm
thickness = 0.3mm
}
ha:line.45{
clearance = 0
x1 = 3mm
y1 = 3.5999999999999996mm
x2 = 3mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.46{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 3.5999999999999996mm
x2 = 3.5999999999999996mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.47{
clearance = 0
x1 = 3.5999999999999996mm
y1 = 4.8mm
x2 = 4.199999999999999mm
y2 = 4.2mm
thickness = 0.3mm
}
ha:line.48{
clearance = 0
x1 = 4.199999999999999mm
y1 = 4.2mm
x2 = 4.799999999999999mm
y2 = 4.8mm
thickness = 0.3mm
}
ha:line.49{
clearance = 0
x1 = 4.799999999999999mm
y1 = 4.8mm
x2 = 4.799999999999999mm
y2 = 3.5999999999999996mm
thickness = 0.3mm
}
}
}
}
}
}
}

View File

@ -1,39 +0,0 @@
#!/bin/sh
#@@example qr(hello world, 1mm)
#@@purpose Generate QR code on silk
#@@desc Generate the specified QR code as silk lines
#@@params text,pixel_size,level
#@@thumbsize 2
#@@param:text ASCII text to encode
#@@param:pixel_size width and height of each pixel
#@@dim:pixel_size
#@@param:level error correction level
#@@optional:level
#@@enum:level:L low
#@@enum:level:H high
#@@default:L
libdir=""
for n in $PCB_RND_PCBLIB/parametric `dirname $0` /usr/local/share/pcb-rnd/pcblib/parametric /usr/share/pcb-rnd/pcblib/parametric
do
if test -f "$n/common.awk"
then
libdir="$n"
break
fi
done
if test -z "$libdir"
then
echo "pcblib/parametric/common.awk not found." >&2
exit 1
fi
awk -f $libdir/common.awk -f `dirname $0`/qr.awk -v "args=$*" -v gen=`basename $0` -v "genfull=$0"

View File

@ -1,62 +0,0 @@
function flush_line(x1, x2, y, w ,n,yy)
{
x1/=2
x2/=2
for(n = 0; n < 3; n++) {
yy = y*w + w/6 + w/3 * n
element_line(x1*w + w/6, yy, x2*w - w/6, yy, w/3)
}
element_line(x1*w + w/6, y*w + w/6, x1*w + w/6, (y+1)*w - w/6, w/3)
element_line(x2*w - w/6, y*w + w/6, x2*w - w/6, (y+1)*w - w/6, w/3)
}
BEGIN {
help_auto()
set_arg(P, "?pixel_size", "1mm")
proc_args(P, "text,pixel_size,level", "text")
pixel_size = parse_dim(P["pixel_size"])
element_begin("", "QR1", "qr(" P["text"] "," P["pixel_size"] "," P["level"] ")" ,0,0, 0,-mil(50))
print "# text=" P["text"]
cmd = "echo '" P["text"] "' | qrencode -t ASCII"
if (P["level"] != "") {
if (tolower(P["level"]) == "h")
cmd = cmd " -l H"
else if (tolower(P["level"]) == "l")
cmd = cmd " -l L"
}
y = 0;
while((cmd | getline line) > 0) {
line = line "-"
# print line
len = length(line)
start = ""
for(x = 1; x < len; x++) {
if (substr(line, x, 1) == "#") {
if (start == "")
start = x;
}
else {
if (start != "") {
flush_line(start, x, y, pixel_size)
start = ""
}
}
}
if (start != "")
flush_line(start, x, y, pixel_size)
y++;
}
# dimension(+spacing/aspect, -dia, +spacing/aspect, dia, "@" spacing*1.2 ";0", "dia")
element_end()
}

5
fp-lib-table Normal file
View File

@ -0,0 +1,5 @@
(fp_lib_table
(lib (name "qeda")(type "KiCad")(uri "${KIPRJMOD}/kicad/qeda.pretty")(options "")(descr ""))
(lib (name "kikit")(type "KiCad")(uri "${KIPRJMOD}/kicad/kikit.pretty")(options "")(descr ""))
(lib (name "custom")(type "KiCad")(uri "${KIPRJMOD}/kicad/custom.pretty")(options "")(descr ""))
)

2
gafrc
View File

@ -1,2 +0,0 @@
(source-library ".")
(component-library "./geda/symbols/")

View File

@ -1,18 +0,0 @@
v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
1V8
T 300 0 8 8 0 0 0 0 1
net=1V8:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

View File

@ -1,18 +0,0 @@
v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
3V3
T 300 0 8 8 0 0 0 0 1
net=3V3:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

View File

@ -1,18 +0,0 @@
v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
5V
T 300 0 8 8 0 0 0 0 1
net=5V:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

View File

@ -1,17 +0,0 @@
v 20210407 2
P 100 100 100 200 1 0 1
{
T 158 161 5 4 0 1 0 0 1
pinnumber=1
T 158 161 5 4 0 0 0 0 1
pinseq=1
T 158 161 5 4 0 1 0 0 1
pinlabel=1
T 158 161 5 4 0 1 0 0 1
pintype=pwr
}
L 0 100 200 100 3 0 0 0 -1 -1
T 300 50 8 10 0 0 0 0 1
net=GND:1
L 0 100 100 0 3 0 1 0 -1 -1
L 200 100 100 0 3 0 1 0 -1 -1

View File

@ -1,18 +0,0 @@
v 20210626 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
VCC
T 300 0 8 8 0 0 0 0 1
net=VCC:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

View File

@ -1,18 +0,0 @@
v 20210407 2
P 200 0 200 200 1 0 0
{
T 250 50 5 6 0 1 0 0 1
pinnumber=1
T 250 50 5 6 0 0 0 0 1
pinseq=1
T 250 50 5 6 0 1 0 0 1
pinlabel=1
T 250 50 5 6 0 1 0 0 1
pintype=pwr
}
T 200 250 9 8 1 0 0 3 1
VTRG
T 300 0 8 8 0 0 0 0 1
net=VTRG:1
L 150 100 200 200 3 10 1 0 -1 -1
L 200 200 250 100 3 10 1 0 -1 -1

View File

@ -1,40 +0,0 @@
v 20210626 2
L 3000 900 3000 0 15 0 0 0 -1 -1
B 0 0 6000 1500 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 0 900 6000 900 15 0 0 0 -1 -1
T 1000 700 9 10 1 1 0 0 1
date=$date$
T 4300 700 9 10 1 1 0 0 1
org=$organisation$
T 4300 400 9 10 1 1 0 0 1
authors=$authors$
T 3000 1200 9 14 1 1 0 4 1
title=TITLE
T 3100 400 15 8 1 0 0 0 1
AUTHORS:
T 3100 100 15 8 1 0 0 0 1
LICENCE:
T 100 100 15 8 1 0 0 0 1
REVISION:
T 100 1100 15 8 1 0 0 0 1
TITLE:
T 100 400 15 8 1 0 0 0 1
VERSION:
T 0 1600 8 10 0 0 0 0 1
graphical=1
T 3100 700 15 8 1 0 0 0 1
ORGANISATION:
T 100 700 15 8 1 0 0 0 1
DATE:
T 1000 400 9 10 1 1 0 0 1
version=$version$
T 1000 100 9 10 1 1 0 0 1
revision=$revision$
T 4300 100 9 10 1 1 0 0 1
licence=$licence$
T 0 1800 8 10 0 0 0 0 1
device=none
T 0 2000 8 10 0 0 0 0 1
footprint=none
T 0 2200 8 10 0 0 0 0 1
refdes=none

View File

@ -0,0 +1,551 @@
(footprint "QR" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 0)
(fp_text reference "QR*****" (at 0 8.875) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 16a64ac1-ccd2-45c5-8762-6fb2be5912ef)
)
(fp_text value "QR" (at 0 -8.875) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 6bb3f59c-4710-4a40-9b5d-9ea931db02ed)
)
(fp_rect (start -2.475 -5.625) (end -2.025 -5.175) (layer "F.SilkS") (width 0) (fill solid) (tstamp 000be738-f05f-44bd-9548-ec458452f492))
(fp_rect (start 3.375 -0.225) (end 3.825 0.225) (layer "F.SilkS") (width 0) (fill solid) (tstamp 00bfa9f4-8bb1-4eed-a348-58e42b4ac00d))
(fp_rect (start -0.225 -3.825) (end 0.225 -3.375) (layer "F.SilkS") (width 0) (fill solid) (tstamp 010d1905-0740-46b9-892f-4c7ea9b0f379))
(fp_rect (start -6.975 2.025) (end -6.525 2.475) (layer "F.SilkS") (width 0) (fill solid) (tstamp 014e3ca2-506b-4797-90d4-9bee40f9dcb5))
(fp_rect (start -7.425 4.725) (end -6.975 5.175) (layer "F.SilkS") (width 0) (fill solid) (tstamp 01c1cbd4-0a49-4aaa-8c1c-4f3cffd0da34))
(fp_rect (start 6.525 -3.375) (end 6.975 -2.925) (layer "F.SilkS") (width 0) (fill solid) (tstamp 01d2dc82-57e5-4ff7-bed5-8543607adfc7))
(fp_rect (start -3.825 5.625) (end -3.375 6.075) (layer "F.SilkS") (width 0) (fill solid) (tstamp 01edc007-3f11-4fe5-aa38-efe885653630))
(fp_rect (start 3.375 -3.825) (end 3.825 -3.375) (layer "F.SilkS") (width 0) (fill solid) (tstamp 026a68be-be59-4753-87f9-48b31ae298f7))
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