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stm8s/stm8s.h

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initial firmware template
2020-09-30 16:59:31 +02:00
/* STM8S103 register definition
* the register names and content are from STM8S reference manual (Revision 17, October 2017)
* the register base addresses (search for _BASE) and some offsets (search PRODUCT) are from STM8S103 datasheet (February 2017) and specific to this device
* the SWIM register is described in STM8 SWIM communication protocol and debug module (UM0470, August 2016)
* using the macro definitions saves space, while using the structures is safer
*/
#include <stdint.h>
// I/O port hardware register map
typedef union {
struct {
uint8_t ODR0:1; /*!< bit 0: Output data register bit */
uint8_t ODR1:1; /*!< bit 1: Output data register bit */
uint8_t ODR2:1; /*!< bit 2: Output data register bit */
uint8_t ODR3:1; /*!< bit 3: Output data register bit */
uint8_t ODR4:1; /*!< bit 4: Output data register bit */
uint8_t ODR5:1; /*!< bit 5: Output data register bit */
uint8_t ODR6:1; /*!< bit 6: Output data register bit */
uint8_t ODR7:1; /*!< bit 7: Output data register bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} GPIO_Px_ODR_type; /*!< Port x output data register (Px_ODR) */
typedef union {
struct {
uint8_t IDR0:1; /*!< bit 0: Pin input value */
uint8_t IDR1:1; /*!< bit 1: Pin input value */
uint8_t IDR2:1; /*!< bit 2: Pin input value */
uint8_t IDR3:1; /*!< bit 3: Pin input value */
uint8_t IDR4:1; /*!< bit 4: Pin input value */
uint8_t IDR5:1; /*!< bit 5: Pin input value */
uint8_t IDR6:1; /*!< bit 6: Pin input value */
uint8_t IDR7:1; /*!< bit 7: Pin input value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} GPIO_Px_IDR_type; /*!< Port x pin input data register (Px_IDR) */
typedef union {
struct {
uint8_t DDR0:1; /*!< bit 0: Data direction bit */
uint8_t DDR1:1; /*!< bit 1: Data direction bit */
uint8_t DDR2:1; /*!< bit 2: Data direction bit */
uint8_t DDR3:1; /*!< bit 3: Data direction bit */
uint8_t DDR4:1; /*!< bit 4: Data direction bit */
uint8_t DDR5:1; /*!< bit 5: Data direction bit */
uint8_t DDR6:1; /*!< bit 6: Data direction bit */
uint8_t DDR7:1; /*!< bit 7: Data direction bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} GPIO_Px_DDR_type; /*!< Port x data direction register */
typedef union {
struct {
uint8_t C10:1; /*!< bit 0: Control bit */
uint8_t C11:1; /*!< bit 1: Control bit */
uint8_t C12:1; /*!< bit 2: Control bit */
uint8_t C13:1; /*!< bit 3: Control bit */
uint8_t C14:1; /*!< bit 4: Control bit */
uint8_t C15:1; /*!< bit 5: Control bit */
uint8_t C16:1; /*!< bit 6: Control bit */
uint8_t C17:1; /*!< bit 7: Control bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} GPIO_Px_CR1_type; /*!< Port x control register 1 (Px_CR1) */
typedef union {
struct {
uint8_t C20:1; /*!< bit 0: Control bit */
uint8_t C21:1; /*!< bit 1: Control bit */
uint8_t C22:1; /*!< bit 2: Control bit */
uint8_t C23:1; /*!< bit 3: Control bit */
uint8_t C24:1; /*!< bit 4: Control bit */
uint8_t C25:1; /*!< bit 5: Control bit */
uint8_t C26:1; /*!< bit 6: Control bit */
uint8_t C27:1; /*!< bit 7: Control bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} GPIO_Px_CR2_type; /*!< Port x control register 2 (Px_CR2) */
typedef struct {
volatile GPIO_Px_ODR_type ODR;
volatile GPIO_Px_IDR_type IDR;
volatile GPIO_Px_DDR_type DDR;
volatile GPIO_Px_CR1_type CR1;
volatile GPIO_Px_CR2_type CR2;
} GPIO_type;
// I/O port hardware register map
// Block: Port A
#define PA_BASE 0x5000
#define GPIO_PA ((GPIO_type*)PA_BASE)
#define PA_ODR (*(volatile uint8_t *)(PA_BASE + 0x00))
#define PA_IDR (*(volatile uint8_t *)(PA_BASE + 0x01))
#define PA_DDR (*(volatile uint8_t *)(PA_BASE + 0x02))
#define PA_CR1 (*(volatile uint8_t *)(PA_BASE + 0x03))
#define PA_CR2 (*(volatile uint8_t *)(PA_BASE + 0x04))
#define PA0 (1 << 0)
#define PA1 (1 << 1)
#define PA2 (1 << 2)
#define PA3 (1 << 3)
#define PA4 (1 << 4)
#define PA5 (1 << 5)
#define PA6 (1 << 6)
#define PA7 ((uint8_t)(1 << 7))
// Block: Port B
#define PB_BASE 0x5005
#define GPIO_PB ((GPIO_type*)PB_BASE)
#define PB_ODR (*(volatile uint8_t *)(PB_BASE + 0x00))
#define PB_IDR (*(volatile uint8_t *)(PB_BASE + 0x01))
#define PB_DDR (*(volatile uint8_t *)(PB_BASE + 0x02))
#define PB_CR1 (*(volatile uint8_t *)(PB_BASE + 0x03))
#define PB_CR2 (*(volatile uint8_t *)(PB_BASE + 0x04))
#define PB0 (1 << 0)
#define PB1 (1 << 1)
#define PB2 (1 << 2)
#define PB3 (1 << 3)
#define PB4 (1 << 4)
#define PB5 (1 << 5)
#define PB6 (1 << 6)
#define PB7 ((uint8_t)(1 << 7))
// Block: Port C
#define PC_BASE 0x500A
#define GPIO_PC ((GPIO_type*)PC_BASE)
#define PC_ODR (*(volatile uint8_t *)(PC_BASE + 0x00))
#define PC_IDR (*(volatile uint8_t *)(PC_BASE + 0x01))
#define PC_DDR (*(volatile uint8_t *)(PC_BASE + 0x02))
#define PC_CR1 (*(volatile uint8_t *)(PC_BASE + 0x03))
#define PC_CR2 (*(volatile uint8_t *)(PC_BASE + 0x04))
#define PC0 (1 << 0)
#define PC1 (1 << 1)
#define PC2 (1 << 2)
#define PC3 (1 << 3)
#define PC4 (1 << 4)
#define PC5 (1 << 5)
#define PC6 (1 << 6)
#define PC7 ((uint8_t)(1 << 7))
// Block: Port D
#define PD_BASE 0x500F
#define GPIO_PD ((GPIO_type*)PD_BASE)
#define PD_ODR (*(volatile uint8_t *)(PD_BASE + 0x00))
#define PD_IDR (*(volatile uint8_t *)(PD_BASE + 0x01))
#define PD_DDR (*(volatile uint8_t *)(PD_BASE + 0x02))
#define PD_CR1 (*(volatile uint8_t *)(PD_BASE + 0x03))
#define PD_CR2 (*(volatile uint8_t *)(PD_BASE + 0x04))
#define PD0 (1 << 0)
#define PD1 (1 << 1)
#define PD2 (1 << 2)
#define PD3 (1 << 3)
#define PD4 (1 << 4)
#define PD5 (1 << 5)
#define PD6 (1 << 6)
#define PD7 ((uint8_t)(1 << 7))
// Block: Port E
#define PE_BASE 0x5014
#define GPIO_PE ((GPIO_type*)PE_BASE)
#define PE_ODR (*(volatile uint8_t *)(PE_BASE + 0x00))
#define PE_IDR (*(volatile uint8_t *)(PE_BASE + 0x01))
#define PE_DDR (*(volatile uint8_t *)(PE_BASE + 0x02))
#define PE_CR1 (*(volatile uint8_t *)(PE_BASE + 0x03))
#define PE_CR2 (*(volatile uint8_t *)(PE_BASE + 0x04))
#define PE0 (1 << 0)
#define PE1 (1 << 1)
#define PE2 (1 << 2)
#define PE3 (1 << 3)
#define PE4 (1 << 4)
#define PE5 (1 << 5)
#define PE6 (1 << 6)
#define PE7 ((uint8_t)(1 << 7))
// Block: Port F
#define PF_BASE 0x5019
#define GPIO_PF ((GPIO_type*)PF_BASE)
#define PF_ODR (*(volatile uint8_t *)(PF_BASE + 0x00))
#define PF_IDR (*(volatile uint8_t *)(PF_BASE + 0x01))
#define PF_DDR (*(volatile uint8_t *)(PF_BASE + 0x02))
#define PF_CR1 (*(volatile uint8_t *)(PF_BASE + 0x03))
#define PF_CR2 (*(volatile uint8_t *)(PF_BASE + 0x04))
#define PF0 (1 << 0)
#define PF1 (1 << 1)
#define PF2 (1 << 2)
#define PF3 (1 << 3)
#define PF4 (1 << 4)
#define PF5 (1 << 5)
#define PF6 (1 << 6)
#define PF7 ((uint8_t)(1 << 7))
// General hardware register map
// Block: Flash
typedef union {
struct {
uint8_t FIX:1; /*!< bit 0: Fixed Byte programming time */
uint8_t IE:1; /*!< bit 1: Flash Interrupt enable */
uint8_t AHALT:1; /*!< bit 2: Power-down in Active-halt mode */
uint8_t HALT:1; /*!< bit 3: Power-down in Halt mode */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_CR1_type; /*!< Flash control register 1 (FLASH_CR1) */
typedef union {
struct {
uint8_t PRG:1; /*!< bit 0: Standard block programming */
const uint8_t :3; /*!< bit 3..1: Reserved */
uint8_t FPRG:1; /*!< bit 4: Fast block programming */
uint8_t ERASE:1; /*!< bit 5: Block erasing */
uint8_t WPRG:1; /*!< bit 6: Word programming */
uint8_t OPT:1; /*!< bit 7: Write option bytes */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_CR2_type; /*!< Flash control register 2 (FLASH_CR2) */
typedef union {
struct {
uint8_t NPRG:1; /*!< bit 0: Standard block programming */
uint8_t :3; /*!< bit 1..3: Reserved */
uint8_t NFPRG:1; /*!< bit 4: Fast block programming */
uint8_t NERASE:1; /*!< bit 5: Block erasing */
uint8_t NWPRG:1; /*!< bit 6: Word programming */
uint8_t NOPT:1; /*!< bit 7: Write option bytes */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_NCR2_type; /*!< Flash complementary control register 2 (FLASH_NCR2) */
typedef union {
struct {
const uint8_t WPB0:1; /*!< bit 0: User boot code area protection bit */
const uint8_t WPB1:1; /*!< bit 1: User boot code area protection bit */
const uint8_t WPB2:1; /*!< bit 2: User boot code area protection bit */
const uint8_t WPB3:1; /*!< bit 3: User boot code area protection bit */
const uint8_t WPB4:1; /*!< bit 4: User boot code area protection bit */
const uint8_t WPB5:1; /*!< bit 5: User boot code area protection bit */
} fields; /*!< structure used for bit access */
const uint8_t reg; /*!< type used for register access */
} FLASH_FPR_type; /*!< Flash protection register (FLASH_FPR) */
typedef union {
struct {
const uint8_t NWPB0:1; /*!< bit 0: User boot code area protection bit */
const uint8_t NWPB1:1; /*!< bit 1: User boot code area protection bit */
const uint8_t NWPB2:1; /*!< bit 2: User boot code area protection bit */
const uint8_t NWPB3:1; /*!< bit 3: User boot code area protection bit */
const uint8_t NWPB4:1; /*!< bit 4: User boot code area protection bit */
const uint8_t NWPB5:1; /*!< bit 5: User boot code area protection bit */
} fields; /*!< structure used for bit access */
const uint8_t reg; /*!< type used for register access */
} FLASH_NFPR_type; /*!< Flash protection register (FLASH_NFPR) */
typedef union {
struct {
uint8_t PUK:8; /*!< bit 0..7: Main program memory unlock keys */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_PUKR_type; /*!< Flash program memory unprotecting key register (FLASH_PUKR) */
typedef union {
struct {
uint8_t DUK:8; /*!< bit 0..7: Data EEPROM write unlock keys */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_DUKR_type; /*!< Data EEPROM unprotection key register (FLASH_DUKR) */
typedef union {
struct {
uint8_t WR_PG_DIS:1; /*!< bit 0: Write attempted to protected page flag */
uint8_t PUL:1; /*!< bit 1: Flash Program memory unlocked flag */
uint8_t EOP:1; /*!< bit 2: End of programming (write or erase operation) flag */
uint8_t DUL:1; /*!< bit 3: Data EEPROM area unlocked flag */
const uint8_t :2; /*!< bit 4..5: Reserved, forced by hardware to 0 */
const uint8_t HVOFF:1; /*!< bit 6: End of high voltage flag */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} FLASH_IAPSR_type; /*!< Flash status register (FLASH_IAPSR) */
typedef struct {
volatile FLASH_CR1_type CR1;
volatile FLASH_CR2_type CR2;
volatile FLASH_NCR2_type NCR2;
volatile FLASH_FPR_type FPR;
volatile FLASH_NFPR_type NFPR;
volatile FLASH_IAPSR_type IAPSR;
const uint8_t reserved0[2];
volatile FLASH_PUKR_type PUKR;
const uint8_t reserved1[1];
volatile FLASH_DUKR_type DUKR;
} FLASH_type;
#define FLASH_BASE 0x505A
#define FLASH ((FLASH_type*)FLASH_BASE)
#define FLASH_CR1 (*(volatile uint8_t *)(FLASH_BASE + 0x00))
#define FLASH_CR1_FIX (1 << 0)
#define FLASH_CR1_IE (1 << 1)
#define FLASH_CR1_AHALT (1 << 2)
#define FLASH_CR1_HALT (1 << 3)
#define FLASH_CR2 (*(volatile uint8_t *)(FLASH_BASE + 0x01))
#define FLASH_CR2_PRG (1 << 0)
#define FLASH_CR2_FPRG (1 << 4)
#define FLASH_CR2_ERASE (1 << 5)
#define FLASH_CR2_WPRG (1 << 6)
#define FLASH_CR2_OPT (1 << 7)
#define FLASH_NCR2 (*(volatile uint8_t *)(FLASH_BASE + 0x02))
#define FLASH_NCR2_NPRG (1 << 0)
#define FLASH_NCR2_NFPRG (1 << 4)
#define FLASH_NCR2_NERASE (1 << 5)
#define FLASH_NCR2_NWPRG (1 << 6)
#define FLASH_NCR2_NOPT (1 << 7)
#define FLASH_FPR (*(volatile uint8_t *)(FLASH_BASE + 0x03))
#define FLASH_FPR_WPB0 (1 << 0)
#define FLASH_FPR_WPB1 (1 << 1)
#define FLASH_FPR_WPB2 (1 << 2)
#define FLASH_FPR_WPB3 (1 << 3)
#define FLASH_FPR_WPB4 (1 << 4)
#define FLASH_FPR_WPB5 (1 << 5)
#define FLASH_NFPR (*(volatile uint8_t *)(FLASH_BASE + 0x04))
#define FLASH_NFPR_NWPB0 (1 << 0)
#define FLASH_NFPR_NWPB1 (1 << 1)
#define FLASH_NFPR_NWPB2 (1 << 2)
#define FLASH_NFPR_NWPB3 (1 << 3)
#define FLASH_NFPR_NWPB4 (1 << 4)
#define FLASH_NFPR_NWPB5 (1 << 5)
#define FLASH_IAPSR (*(volatile uint8_t *)(FLASH_BASE + 0x05))
#define FLASH_IAPSR_WR_PG_DIS (1 << 0)
#define FLASH_IAPSR_PUL (1 << 1)
#define FLASH_IAPSR_EOP (1 << 2)
#define FLASH_IAPSR_DUL (1 << 3)
#define FLASH_IAPSR_HVOFF (1 << 6)
#define FLASH_PUKR (*(volatile uint8_t *)(FLASH_BASE + 0x08))
#define FLASH_PUKR_KEY1 0x56
#define FLASH_PUKR_KEY2 0xAE
#define FLASH_DUKR (*(volatile uint8_t *)(FLASH_BASE + 0x0A))
#define FLASH_DUKR_KEY1 0x56
#define FLASH_DUKR_KEY2 0xAE
// Block: ITC
typedef union {
struct {
uint8_t PAIS:2; /*!< bit 0..1: Port A external interrupt sensitivity bits */
uint8_t PBIS:2; /*!< bit 2..3: Port B external interrupt sensitivity bits */
uint8_t PCIS:2; /*!< bit 4..5: Port C external interrupt sensitivity bits */
uint8_t PDIS:2; /*!< bit 6..7: Port D external interrupt sensitivity bits */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} EXTI_CR1_type; /*!< External interrupt control register 1 (EXTI_CR1) */
typedef union {
struct {
uint8_t PEIS:2; /*!< bit 0..1: Port E external interrupt sensitivity bits */
uint8_t TLIS:1; /*!< bit 2: Top level interrupt sensitivity */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} EXTI_CR2_type; /*!< External interrupt control register 2 (EXTI_CR2) */
typedef struct {
volatile EXTI_CR1_type CR1;
volatile EXTI_CR2_type CR2;
} EXTI_type;
#define EXTI_BASE 0x50A0
#define EXTI ((EXTI_type*)EXTI_BASE)
#define EXTI_CR1 (*(volatile uint8_t *)(EXTI_BASE + 0x00))
#define EXTI_CR1_PAIS_OFFSET 0
#define EXTI_CR1_PAIS_MASK 0x3
#define EXTI_CR1_PBIS_OFFSET 2
#define EXTI_CR1_PBIS_MASK 0x3
#define EXTI_CR1_PCIS_OFFSET 4
#define EXTI_CR1_PCIS_MASK 0x3
#define EXTI_CR1_PDIS_OFFSET 6
#define EXTI_CR1_PDIS_MASK 0x3
#define EXTI_CR2 (*(volatile uint8_t *)(EXTI_BASE + 0x01))
#define EXTI_CR2_PEIS_OFFSET 0
#define EXTI_CR2_PEIS_MASK 0x3
#define EXTI_CR2_TLIS (1 << 2)
#define EXTI_FALLING_EDGE_LOW_LEVEL 0
#define EXTI_RISING_EDGE 1
#define EXTI_FALLING_EDGE 2
#define EXTI_RISING_FALLING_EDGE 3
// Block: RST
typedef union {
struct {
uint8_t WWDGF:1; /*!< bit 0: Window Watchdog reset flag */
uint8_t IWDGF:1; /*!< bit 1: Independent Watchdog reset flag */
uint8_t ILLOPF:1; /*!< bit 2: Illegal opcode reset flag */
uint8_t SWIMF:1; /*!< bit 3: SWIM reset flag */
uint8_t EMCF:1; /*!< bit 4: EMC reset flag */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} RST_SR_type; /*!< Reset status register (RST_SR) */
typedef struct {
volatile RST_SR_type SR;
} RST_type;
#define RST_BASE 0x50B3
#define RST ((RST_type*)RST_BASE)
#define RST_SR (*(volatile uint8_t *)(RST_BASE + 0x00))
#define RST_SR_WWDGF (1 << 0)
#define RST_SR_IWDGF (1 << 1)
#define RST_SR_ILLOPF (1 << 2)
#define RST_SR_SWIMF (1 << 3)
#define RST_SR_EMCF (1 << 4)
// Block: CLK
typedef union {
struct {
uint8_t HSIEN:1; /*!< bit 0: High speed internal RC oscillator enable */
const uint8_t HSIRDY:1; /*!< bit 1: High speed internal oscillator ready */
uint8_t FHWU:1; /*!< bit 2: Fast wakeup from Halt/Active-halt modes */
uint8_t LSIEN:1; /*!< bit 3: Low speed internal RC oscillator enable */
const uint8_t LSIRDY:1; /*!< bit 4: Low speed internal oscillator ready */
uint8_t REGAH:1; /*!< bit 5: Regulator power off in Active-halt mode */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_ICKR_type; /*!< Internal clock register (CLK_ICKR) */
typedef union {
struct {
uint8_t HSEEN:1; /*!< bit 0: High speed external crystal oscillator enable */
const uint8_t HSERDY:1; /*!< bit 1: High speed external crystal oscillator ready */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_ECKR_type; /*!< External clock register (CLK_ECKR) */
typedef union {
struct {
const uint8_t CKM:8; /*!< bit 0..7: Clock master status register (CLK_CMSR) */
} fields; /*!< structure used for bit access */
const uint8_t reg; /*!< type used for register access */
} CLK_CMSR_type; /*!< Clock master status register (CLK_CMSR) */
typedef union {
struct {
uint8_t SWI:8; /*!< bit 0..7: Clock master selection bits */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_SWR_type; /*!< Clock master switch register (CLK_SWR) */
typedef union {
struct {
uint8_t SWBSY:1; /*!< bit 0: Switch busy */
uint8_t SWEN:1; /*!< bit 1: Switch start/stop */
uint8_t SWIEN:1; /*!< bit 2: Clock switch interrupt enable */
uint8_t SWIF:1; /*!< bit 3: Clock switch interrupt flag */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_SWCR_type; /*!< Switch control register (CLK_SWCR) */
typedef union {
struct {
uint8_t CPUDIV:3; /*!< bit 0..2: CPU clock prescaler */
uint8_t HSIDIV:2; /*!< bit 3..4: High speed internal clock prescaler */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_CKDIVR_type; /*!< */
typedef union {
struct {
uint8_t PCKEN10:1; /*!< bit 0: Peripheral clock gating bit */
uint8_t PCKEN11:1; /*!< bit 1: Peripheral clock gating bit */
uint8_t PCKEN12:1; /*!< bit 2: Peripheral clock gating bit */
uint8_t PCKEN13:1; /*!< bit 3: Peripheral clock gating bit */
uint8_t PCKEN14:1; /*!< bit 4: Peripheral clock gating bit */
uint8_t PCKEN15:1; /*!< bit 5: Peripheral clock gating bit */
uint8_t PCKEN16:1; /*!< bit 6: Peripheral clock gating bit */
uint8_t PCKEN17:1; /*!< bit 7: Peripheral clock gating bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_PCKENR1_type; /*!< Peripheral clock gating register 2 (CLK_PCKENR1) */
typedef union {
struct {
uint8_t PCKEN20:1; /*!< bit 0: Peripheral clock gating bit */
uint8_t PCKEN21:1; /*!< bit 1: Peripheral clock gating bit */
uint8_t PCKEN22:1; /*!< bit 2: Peripheral clock gating bit */
uint8_t PCKEN23:1; /*!< bit 3: Peripheral clock gating bit */
uint8_t PCKEN24:1; /*!< bit 4: Peripheral clock gating bit */
uint8_t PCKEN25:1; /*!< bit 5: Peripheral clock gating bit */
uint8_t PCKEN26:1; /*!< bit 6: Peripheral clock gating bit */
uint8_t PCKEN27:1; /*!< bit 7: Peripheral clock gating bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_PCKENR2_type; /*!< Peripheral clock gating register 2 (CLK_PCKENR2) */
typedef union {
struct {
uint8_t CSSEN:1; /*!< bit 0: Clock security system enable */
const uint8_t AUX:1; /*!< bit 1: Auxiliary oscillator connected to master clock */
uint8_t CSSDIE:1; /*!< bit 2: Clock security system detection interrupt enable */
uint8_t CSSD:1; /*!< bit 3: Clock security system detection */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_CSSR_type; /*!< Clock security system register (CLK_CSSR) */
typedef union {
struct {
uint8_t CCOEN:1; /*!< bit 0: Configurable clock output enable */
uint8_t CCOSEL:4; /*!< bit 1..4: Configurable clock output selection */
const uint8_t CCORDY:1; /*!< bit 5: Configurable clock output ready */
const uint8_t CCOBSY:1; /*!< bit 6: Configurable clock output busy */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_CCOR_type; /*!< Configurable clock output register (CLK_CCOR) */
typedef union {
struct {
uint8_t HSITRIM:4; /*!< bit 0..3: HSI trimming value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_HSITRIMR_type; /*!< HSI clock calibration trimming register (CLK_HSITRIMR) */
typedef union {
struct {
uint8_t SWIMCLK:1; /*!< bit 0: SWIM clock divider */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} CLK_SWIMCCR_type; /*!< SWIM clock control register (CLK_SWIMCCR) */
typedef struct {
volatile CLK_ICKR_type ICKR;
volatile CLK_ECKR_type ECKR;
const uint8_t reserved0[1];
volatile CLK_CMSR_type CMSR;
volatile CLK_SWR_type SWR;
volatile CLK_SWCR_type SWCR;
volatile CLK_CKDIVR_type CKDIVR;
volatile CLK_PCKENR1_type PCKENR1;
volatile CLK_CSSR_type CSSR;
volatile CLK_CCOR_type CCOR;
volatile CLK_PCKENR2_type PCKENR2;
const uint8_t reserved1[1];
volatile CLK_HSITRIMR_type HSITRIMR;
volatile CLK_SWIMCCR_type SWIMCCR;
} CLK_type;
#define CLK_BASE 0x50C0
#define CLK ((CLK_type*)CLK_BASE)
#define CLK_ICKR (*(volatile uint8_t *)(CLK_BASE + 0x00))
#define CLK_ICKR_HSIEN (1 << 0)
#define CLK_ICKR_HSIRDY (1 << 1)
#define CLK_ICKR_FHW (1 << 2)
#define CLK_ICKR_LSIEN (1 << 3)
#define CLK_ICKR_LSIRDY (1 << 4)
#define CLK_ICKR_REGAH (1 << 5)
#define CLK_ECKR (*(volatile uint8_t *)(CLK_BASE + 0x01))
#define CLK_ECKR_HSEEN (1 << 0)
#define CLK_ECKR_HSERDY (1 << 1)
#define CLK_CMSR (*(volatile uint8_t *)(CLK_BASE + 0x03))
#define CLK_CMSR_CKM_OFFSET 0
#define CLK_CMSR_CKM_MASK 0xff
#define CLK_CMSR_CKM_HSI 0xe1
#define CLK_CMSR_CKM_LSI 0xd2
#define CLK_CMSR_CKM_HSE 0xb4
#define CLK_SWR (*(volatile uint8_t *)(CLK_BASE + 0x04))
#define CLK_SWR_SWI_OFFSET 0
#define CLK_SWR_SWI_MASK 0xff
#define CLK_SWCR (*(volatile uint8_t *)(CLK_BASE + 0x05))
#define CLK_SWCR_SWBSY (1 << 0)
#define CLK_SWCR_SWEN (1 << 1)
#define CLK_SWCR_SWIEN (1 << 2)
#define CLK_SWCR_SWIF (1 << 3)
#define CLK_CKDIVR (*(volatile uint8_t *)(CLK_BASE + 0x06))
#define CLK_CKDIVR_CPUDIV_OFFSET 0
#define CLK_CKDIVR_CPUDIV_MASK 0x7
#define CLK_CKDIVR_CPUDIV_DIV0 0
#define CLK_CKDIVR_CPUDIV_DIV2 1
#define CLK_CKDIVR_CPUDIV_DIV4 2
#define CLK_CKDIVR_CPUDIV_DIV8 3
#define CLK_CKDIVR_CPUDIV_DIV16 4
#define CLK_CKDIVR_CPUDIV_DIV32 5
#define CLK_CKDIVR_CPUDIV_DIV64 6
#define CLK_CKDIVR_CPUDIV_DIV128 7
#define CLK_CKDIVR_HSIDIV_OFFSET 3
#define CLK_CKDIVR_HSIDIV_MASK 0x3
#define CLK_CKDIVR_HSIDIV_DIV0 0
#define CLK_CKDIVR_HSIDIV_DIV2 1
#define CLK_CKDIVR_HSIDIV_DIV4 2
#define CLK_CKDIVR_HSIDIV_DIV8 3
#define CLK_PCKENR1 (*(volatile uint8_t *)(CLK_BASE + 0x07))
#define CLK_PCKENR1_I2C (1 << 0)
#define CLK_PCKENR1_SPI (1 << 1)
#define CLK_PCKENR1_UART1234 (3 << 2)
#define CLK_PCKENR1_TIM46 (1 << 4)
#define CLK_PCKENR1_TIM25 (1 << 5)
#define CLK_PCKENR1_TIM3 (1 << 6)
#define CLK_PCKENR1_TIM1 (1 << 7)
#define CLK_CSSR (*(volatile uint8_t *)(CLK_BASE + 0x08))
#define CLK_CSSR_CSSEN (1 << 0)
#define CLK_CSSR_AUX (1 << 1)
#define CLK_CSSR_CSSDIE (1 << 2)
#define CLK_CSSR_CSSD (1 << 3)
#define CLK_CCOR (*(volatile uint8_t *)(CLK_BASE + 0x09))
#define CLK_CCOR_CCOEN (1 << 0)
#define CLK_CCOR_CCOSEL_OFFSET 1
#define CLK_CCOR_CCOSEL_MASK 0xf
#define CLK_CCOR_CCOSEL_HSIDIV 0
#define CLK_CCOR_CCOSEL_LSI 1
#define CLK_CCOR_CCOSEL_HSE 2
#define CLK_CCOR_CCOSEL_CPU 4
#define CLK_CCOR_CCOSEL_CPU_DIV2 5
#define CLK_CCOR_CCOSEL_CPU_DIV4 6
#define CLK_CCOR_CCOSEL_CPU_DIV8 7
#define CLK_CCOR_CCOSEL_CPU_DIV16 8
#define CLK_CCOR_CCOSEL_CPU_DIV32 9
#define CLK_CCOR_CCOSEL_CPU_DIV64 10
#define CLK_CCOR_CCOSEL_HSI 11
#define CLK_CCOR_CCOSEL_MASTER 12
#define CLK_CCOR_CCORDY (1 << 5)
#define CLK_CCOR_CCOBSY (1 << 6)
#define CLK_PCKENR2 (*(volatile uint8_t *)(CLK_BASE + 0x0A))
#define CLK_PCKENR2_AWU (1 << 2)
#define CLK_PCKENR2_ADC (1 << 3)
#define CLK_PCKENR2_CAN (1 << 7)
#define CLK_HSITRIMR (*(volatile uint8_t *)(CLK_BASE + 0x0C))
#define CLK_HSITRIMR_OFFSET 0
#define CLK_HSITRIMR_MASK 0xf
#define CLK_SWIMCCR (*(volatile uint8_t *)(CLK_BASE + 0x0D))
#define CLK_SWIMCCR_SWIMCLK (1 << 0)
// Block: WWDG
typedef union {
struct {
uint8_t T0:1; /*!< bit 0: 7-bit counter (MSB to LSB) */
uint8_t T1:1; /*!< bit 1: 7-bit counter (MSB to LSB) */
uint8_t T2:1; /*!< bit 2: 7-bit counter (MSB to LSB) */
uint8_t T3:1; /*!< bit 3: 7-bit counter (MSB to LSB) */
uint8_t T4:1; /*!< bit 4: 7-bit counter (MSB to LSB) */
uint8_t T5:1; /*!< bit 5: 7-bit counter (MSB to LSB) */
uint8_t T6:1; /*!< bit 6: 7-bit counter (MSB to LSB) */
uint8_t WDGA:1; /*!< bit 7: Activation bit */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} WWDG_CR_type; /*!< */
typedef union {
struct {
uint8_t W0:1; /*!< bit 0: 7-bit window value */
uint8_t W1:1; /*!< bit 1: 7-bit window value */
uint8_t W2:1; /*!< bit 2: 7-bit window value */
uint8_t W3:1; /*!< bit 3: 7-bit window value */
uint8_t W4:1; /*!< bit 4: 7-bit window value */
uint8_t W5:1; /*!< bit 5: 7-bit window value */
uint8_t W6:1; /*!< bit 6: 7-bit window value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} WWDG_WR_type; /*!< Window register (WWDG_WR) */
typedef struct {
volatile WWDG_CR_type CR;
volatile WWDG_WR_type WR;
} WWDG_type;
#define WWDG_BASE 0x50D1
#define WWDG ((WWDG_type*)WWDG_BASE)
#define WWDG_CR (*(volatile uint8_t *)(WWDG_BASE + 0x00))
#define WWDG_CR_T_OFFSET 0
#define WWDG_CR_T_MASK 0x7f
#define WWDG_CR_T0 (1 << 0)
#define WWDG_CR_T1 (1 << 1)
#define WWDG_CR_T2 (1 << 2)
#define WWDG_CR_T3 (1 << 3)
#define WWDG_CR_T4 (1 << 4)
#define WWDG_CR_T5 (1 << 5)
#define WWDG_CR_T6 (1 << 6)
#define WWDG_CR_WDGA (1 << 7)
#define WWDG_WR (*(volatile uint8_t *)(WWDG_BASE + 0x01))
#define WWDG_WR_W_OFFSET 0
#define WWDG_WR_W_MASK 0x7f
// Block: IWDG
typedef union {
struct {
uint8_t KEY:8; /*!< bit 0..7: Key value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} IWDG_KR_type; /*!< Key register (IWDG_KR) */
typedef union {
struct {
uint8_t PR:3; /*!< bit 0..2: Prescaler divider */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} IWDG_PR_type; /*!< Prescaler register (IWDG_PR) */
typedef union {
struct {
uint8_t RL:8; /*!< bit 0..7: Watchdog counter reload value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} IWDG_RLR_type; /*!< Reload register (IWDG_RLR) */
typedef struct {
volatile IWDG_KR_type KR;
volatile IWDG_PR_type PR;
volatile IWDG_RLR_type RLR;
} IWDG_type;
#define IWDG_BASE 0x50E0
#define IWDG ((IWDG_type*)IWDG_BASE)
#define IWDG_KR (*(volatile uint8_t *)(IWDG_BASE + 0x00))
#define IWDG_KR_KEY_ENABLE 0xCC
#define IWDG_KR_KEY_REFRESH 0xAA
#define IWDG_KR_KEY_ACCESS 0x55
#define IWDG_PR (*(volatile uint8_t *)(IWDG_BASE + 0x01))
#define IWDG_PR_DIV4 0
#define IWDG_PR_DIV8 1
#define IWDG_PR_DIV16 2
#define IWDG_PR_DIV32 3
#define IWDG_PR_DIV64 4
#define IWDG_PR_DIV128 5
#define IWDG_PR_DIV256 6
#define IWDG_RLR (*(volatile uint8_t *)(IWDG_BASE + 0x02))
// Block: AWU
typedef union {
struct {
uint8_t MSR:1; /*!< bit 0: Measurement enable */
uint8_t :3; /*!< bit 1..3: Reserved */
uint8_t AWUEN:1; /*!< bit 4: Auto-wakeup enable */
uint8_t AWUF:1; /*!< bit 5: Auto-wakeup flag */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} AWU_CSR_type; /*!< Control/status register (AWU_CSR) */
typedef union {
struct {
uint8_t APR:6; /*!< bit 0..5: Asynchronous prescaler divider */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} AWU_APR_type; /*!< Asynchronous prescaler register (AWU_APR) */
typedef union {
struct {
uint8_t AWUTB:4; /*!< bit 0..3: Auto-wakeup timebase selection */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} AWU_TBR_type; /*!< Timebase selection register (AWU_TBR) */
typedef struct {
volatile AWU_CSR_type CSR;
volatile AWU_APR_type APR;
volatile AWU_TBR_type TBR;
} AWU_type;
#define AWU_BASE 0x50F0
#define AWU ((AWU_type*)AWU_BASE)
#define AWU_CSR (*(volatile uint8_t *)(AWU_BASE + 0x00))
#define AWU_CSR_MSR (1 << 0)
#define AWU_CSR_AWUEN (1 << 4)
#define AWU_CSR_AWUF (1 << 5)
#define AWU_APR (*(volatile uint8_t *)(AWU_BASE + 0x01))
#define AWU_TBR (*(volatile uint8_t *)(AWU_BASE + 0x02))
// Block: BEEP
typedef union {
struct {
uint8_t BEEPDIV:5; /*!< bit 0..4: Beep prescaler divider */
uint8_t BEEPEN:1; /*!< bit 5: Beep enable */
uint8_t BEEPSEL:2; /*!< bit 6..7: Beep selection */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} BEEP_CSR_type; /*!< Beeper control/status register (BEEP_CSR) */
typedef struct {
volatile BEEP_CSR_type CSR;
} BEEP_type;
#define BEEP_BASE 0x50F3
#define BEEP ((BEEP_type*)BEEP_BASE)
#define BEEP_CSR (*(volatile uint8_t *)(BEEP_BASE + 0x00))
// Block: SPI
typedef union {
struct {
uint8_t CPHA:1; /*!< bit 0: Clock phase */
uint8_t CPOL:1; /*!< bit 1: Clock polarity */
uint8_t MSTR:1; /*!< bit 2: Master selection */
uint8_t BR:3; /*!< bit 3..5: Baud rate control */
uint8_t SPE:1; /*!< bit 6: SPI enable */
uint8_t LSBFIRST:1; /*!< bit 7: Frame format */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_CR1_type; /*!< SPI control register 1 (SPI_CR1) */
typedef union {
struct {
uint8_t SSI:1; /*!< bit 0: Internal slave select */
uint8_t SSM:1; /*!< bit 1: Software slave management */
uint8_t RXONLY:1; /*!< bit 2: Receive only */
uint8_t :1; /*!< bit 3: Reserved */
uint8_t CRCNEXT:1; /*!< bit 4: Transmit CRC next */
uint8_t CRCEN:1; /*!< bit 5: Hardware CRC calculation enable */
uint8_t BDOE:1; /*!< bit 6: Input/Output enable in bidirectional mode */
uint8_t BDM:1; /*!< bit 7: Bidirectional data mode enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_CR2_type; /*!< SPI control register 2 (SPI_CR2) */
typedef union {
struct {
uint8_t :4; /*!< bit 0..3: Reserved */
uint8_t WKIE:1; /*!< bit 4: Wakeup interrupt enable */
uint8_t ERRIE:1; /*!< bit 5: Error interrupt enable */
uint8_t RXIE:1; /*!< bit 6: RX buffer not empty interrupt enable */
uint8_t TXIE:1; /*!< bit 7: Tx buffer empty interrupt enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_ICR_type; /*!< SPI interrupt control register (SPI_ICR) */
typedef union {
struct {
uint8_t RXNE:1; /*!< bit 0: Receive buffer not empty */
uint8_t TXE:1; /*!< bit 1: Transmit buffer empty */
uint8_t :1; /*!< bit 2: Reserved */
uint8_t WKUP:1; /*!< bit 3: Wakeup flag */
uint8_t CRCERR:1; /*!< bit 4: CRC error flag */
uint8_t MODF:1; /*!< bit 5: Mode fault */
uint8_t OVR:1; /*!< bit 6: Overrun flag */
uint8_t BSY:1; /*!< bit 7: Busy flag */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_SR_type; /*!< SPI status register (SPI_SR) */
typedef union {
struct {
uint8_t DR:8; /*!< bit 0..7: Data register */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_DR_type; /*!< SPI data register (SPI_DR) */
typedef union {
struct {
uint8_t CRCPOLY:8; /*!< bit 0..7: CRC polynomial register */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_CRCPR_type; /*!< SPI CRC polynomial register (SPI_CRCPR) */
typedef union {
struct {
uint8_t RXCRC:8; /*!< bit 0..7: Rx CRC Register */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_RXCRCR_type; /*!< SPI Rx CRC register (SPI_RXCRCR) */
typedef union {
struct {
uint8_t TXCRC:8; /*!< bit 0..7: Tx CRC register */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} SPI_TXCRCR_type; /*!< SPI Tx CRC register (SPI_TXCRCR) */
typedef struct {
volatile SPI_CR1_type CR1;
volatile SPI_CR2_type CR2;
volatile SPI_ICR_type ICR;
volatile SPI_SR_type SR;
volatile SPI_DR_type DR;
volatile SPI_CRCPR_type CRCPR;
volatile SPI_RXCRCR_type RXCRCR;
volatile SPI_TXCRCR_type TXCRCR;
} SPI_type;
#define SPI_BASE 0x5200
#define SPI ((SPI_type*)SPI_BASE)
#define SPI_CR1 (*(volatile uint8_t *)(SPI_BASE + 0x00))
#define SPI_CR2 (*(volatile uint8_t *)(SPI_BASE + 0x01))
#define SPI_ICR (*(volatile uint8_t *)(SPI_BASE + 0x02))
#define SPI_SR (*(volatile uint8_t *)(SPI_BASE + 0x03))
#define SPI_DR (*(volatile uint8_t *)(SPI_BASE + 0x04))
#define SPI_CRCPR (*(volatile uint8_t *)(SPI_BASE + 0x05))
#define SPI_RXCRCR (*(volatile uint8_t *)(SPI_BASE + 0x06))
#define SPI_TXCRCR (*(volatile uint8_t *)(SPI_BASE + 0x07))
// Block: I2C
typedef union {
struct {
uint8_t PE:1; /*!< bit 0: Peripheral enable */
uint8_t :5; /*!< bit 1..5: Reserved */
uint8_t ENGC:1; /*!< bit 6: General call enable */
uint8_t NOSTRETCH:1; /*!< bit 7: Clock stretching disable (Slave mode) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_CR1_type; /*!< Control register 1 (I2C_CR1) */
typedef union {
struct {
uint8_t START:1; /*!< bit 0: Start generation */
uint8_t STOP:1; /*!< bit 1: Stop generation */
uint8_t ACK:1; /*!< bit 2: Acknowledge enable */
uint8_t POS:1; /*!< bit 3: Acknowledge position (for data reception) */
uint8_t :3; /*!< bit 4..6: Reserved */
uint8_t SWRST:1; /*!< bit 7: Software reset */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_CR2_type; /*!< Control register 2 (I2C_CR2) */
typedef union {
struct {
uint8_t FREQ:6; /*!< bit 0..5: Peripheral clock frequency */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_FREQR_type; /*!< Frequency register (I2C_FREQR) */
typedef union {
struct {
uint8_t ADD0:1; /*!< bit 0: Interface address */
uint8_t ADD:7; /*!< bit 1..7: Interface address */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_OARL_type; /*!< Own address register LSB (I2C_OARL) */
typedef union {
struct {
uint8_t :1; /*!< bit 0: Reserved */
uint8_t ADD:2; /*!< bit 1..2: Interface address */
uint8_t :3; /*!< bit 3..5: Reserved */
uint8_t ADDCONF:1; /*!< bit 6: Address mode configuration */
uint8_t ADDMODE:1; /*!< bit 7: Addressing mode (Slave mode) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_OARH_type; /*!< Own address register MSB (I2C_OARH) */
typedef union {
struct {
uint8_t DR:8; /*!< bit 0..7: Data register */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_DR_type; /*!< Data register (I2C_DR) */
typedef union {
struct {
uint8_t SB:1; /*!< bit 0: Start bit (Master mode) */
uint8_t ADDR:1; /*!< bit 1: Address sent (master mode)/matched (slave mode) */
uint8_t BTF:1; /*!< bit 2: Byte transfer finished */
uint8_t ADD10:1; /*!< bit 3: 10-bit header sent (Master mode) */
uint8_t STOPF:1; /*!< bit 4: Stop detection (Slave mode) */
uint8_t :1; /*!< bit 5: Reserved */
uint8_t RXNE:1; /*!< bit 6: Data register not empty (receivers) */
uint8_t TXE:1; /*!< bit 7: Data register empty (transmitters) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_SR1_type; /*!< Status register 1 (I2C_SR1) */
typedef union {
struct {
uint8_t BERR:1; /*!< bit 0: Bus error */
uint8_t ARLO:1; /*!< bit 1: Arbitration lost (master mode) */
uint8_t AF:1; /*!< bit 2: Acknowledge failure */
uint8_t OVR:1; /*!< bit 3: Overrun/underrun */
uint8_t :1; /*!< bit 4: Reserved */
uint8_t WUFH:1; /*!< bit 5: Wakeup from Halt */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_SR2_type; /*!< Status register 2 (I2C_SR2) */
typedef union {
struct {
uint8_t MSL:1; /*!< bit 0: Master/Slave */
uint8_t BUSY:1; /*!< bit 1: Bus busy */
uint8_t TRA:1; /*!< bit 2: Transmitter/Receiver */
uint8_t :1; /*!< bit 3: Reserved */
uint8_t GENCALL:1; /*!< bit 4: General call header (Slave mode) */
uint8_t :2; /*!< bit 5..6: Reserved */
uint8_t DUALF:1; /*!< bit 7: Dual flag (Slave mode) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_SR3_type; /*!< Status register 3 (I2C_SR3) */
typedef union {
struct {
uint8_t ITERREN:1; /*!< bit 0: Error interrupt enable */
uint8_t ITEVTEN:1; /*!< bit 1: Event interrupt enable */
uint8_t ITBUFEN:1; /*!< bit 2: Buffer interrupt enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_ITR_type; /*!< Interrupt register (I2C_ITR) */
typedef union {
struct {
uint8_t CCR7_0:8; /*!< bit 0..7: Clock control register (Master mode) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_CCRL_type; /*!< Clock control register low (I2C_CCRL) */
typedef union {
struct {
uint8_t CCR11_8:4; /*!< bit 0..3: Clock control register in Fast/Standard mode (Master mode) */
uint8_t :2; /*!< bit 4..5: Reserved */
uint8_t DUTY:1; /*!< bit 6: Fast mode duty cycle */
uint8_t FS:1; /*!< bit 7: I2C master mode selection */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_CCRH_type; /*!< Clock control register high (I2C_CCRH) */
typedef union {
struct {
uint8_t TRISE:6; /*!< bit 0..5: Maximum rise time in Fast/Standard mode (Master mode) */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} I2C_TRISER_type; /*!< TRISE register (I2C_TRISER) */
typedef struct {
volatile I2C_CR1_type CR1;
volatile I2C_CR2_type CR2;
volatile I2C_FREQR_type FREQR;
volatile I2C_OARL_type OARL;
volatile I2C_OARH_type OARH;
const uint8_t reserved[1];
volatile I2C_DR_type DR;
volatile I2C_SR1_type SR1;
volatile I2C_SR2_type SR2;
volatile I2C_SR3_type SR3;
volatile I2C_ITR_type ITR;
volatile I2C_CCRL_type CCRL;
volatile I2C_CCRH_type CCRH;
volatile I2C_TRISER_type TRISER;
} I2C_type;
#define I2C_BASE 0x5210
#define I2C ((I2C_type*)I2C_BASE)
#define I2C_CR1 (*(volatile uint8_t *)(I2C_BASE + 0x00))
#define I2C_CR1_PE (1 << 0)
#define I2C_CR1_ENGC (1 << 6)
#define I2C_CR1_NOSTRETCH (1 << 7)
#define I2C_CR2 (*(volatile uint8_t *)(I2C_BASE + 0x01))
#define I2C_CR2_START (1 << 0)
#define I2C_CR2_STOP (1 << 1)
#define I2C_CR2_ACK (1 << 2)
#define I2C_CR2_POS (1 << 3)
#define I2C_CR2_SWRST (1 << 7)
#define I2C_FREQR (*(volatile uint8_t *)(I2C_BASE + 0x02))
#define I2C_OARL (*(volatile uint8_t *)(I2C_BASE + 0x03))
#define I2C_OARL_ARR0 (1 << 0)
#define I2C_OARH (*(volatile uint8_t *)(I2C_BASE + 0x04))
#define I2C_OARH_ADDCONF (1 << 6)
#define I2C_OARH_ADDMODE (1 << 7)
#define I2C_DR (*(volatile uint8_t *)(I2C_BASE + 0x06))
#define I2C_SR1 (*(volatile uint8_t *)(I2C_BASE + 0x07))
#define I2C_SR1_SB (1 << 0)
#define I2C_SR1_ADDR (1 << 1)
#define I2C_SR1_BTF (1 << 2)
#define I2C_SR1_ADD10 (1 << 3)
#define I2C_SR1_STOPF (1 << 4)
#define I2C_SR1_RXNE (1 << 6)
#define I2C_SR1_TXE (1 << 7)
#define I2C_SR2 (*(volatile uint8_t *)(I2C_BASE + 0x08))
#define I2C_SR2_BERR (1 << 0)
#define I2C_SR2_ARLO (1 << 1)
#define I2C_SR2_AF (1 << 2)
#define I2C_SR2_OVR (1 << 3)
#define I2C_SR2_WUFH (1 << 5)
#define I2C_SR3 (*(volatile uint8_t *)(I2C_BASE + 0x09))
#define I2C_SR3_MSL (1 << 0)
#define I2C_SR3_BUSY (1 << 1)
#define I2C_SR3_TRA (1 << 2)
#define I2C_SR3_GENCALL (1 << 4)
#define I2C_SR3_DUALF (1 << 7)
#define I2C_ITR (*(volatile uint8_t *)(I2C_BASE + 0x0A))
#define I2C_ITR_ITERREN (1 << 0)
#define I2C_ITR_ITEVTEN (1 << 1)
#define I2C_ITR_ITBUFEN (1 << 2)
#define I2C_CCRL (*(volatile uint8_t *)(I2C_BASE + 0x0B))
#define I2C_CCRH (*(volatile uint8_t *)(I2C_BASE + 0x0C))
#define I2C_TRISER (*(volatile uint8_t *)(I2C_BASE + 0x0D))
#define I2C_PECR (*(volatile uint8_t *)(I2C_BASE + 0x0E))
// Block: UART
typedef union {
struct {
uint8_t PE:1; /*!< bit 0: Parity error */
uint8_t FE:1; /*!< bit 1: Framing error */
uint8_t NF:1; /*!< bit 2: Noise flag */
uint8_t LHE_OR:1; /*!< bit 3: LIN Header Error (LIN slave mode)/Overrun error */
uint8_t IDLE:1; /*!< bit 4: IDLE line detected */
uint8_t RXNE:1; /*!< bit 5: Read data register not empty */
uint8_t TC:1; /*!< bit 6: Transmission complete */
uint8_t TXE:1; /*!< bit 7: Transmit data register empty */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_SR_type; /*!< Status register (UART_SR) */
typedef union {
struct {
uint8_t DR:8; /*!< bit 0..7: Data value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_DR_type; /*!< Data register (UART_DR) */
typedef union {
struct {
uint8_t UART_DIV:8; /*!< bit 0..7: UART_DIV bits */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_BRR1_type; /*!< Baud rate register 1 (UART_BRR1) */
typedef union {
struct {
uint8_t UART_DIV_LSB:4; /*!< bit 0..3: LSB of UART_DIV */
uint8_t UART_DIV_MSB:4; /*!< bit 4..7: MSB of UART_DIV */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_BRR2_type; /*!< Baud rate register 2 (UART_BRR2) */
typedef union {
struct {
uint8_t PIEN:1; /*!< bit 0: Parity interrupt enable */
uint8_t PS:1; /*!< bit 1: Parity selection */
uint8_t PCEN:1; /*!< bit 2: Parity control enable */
uint8_t WAKE:1; /*!< bit 3: Wakeup method */
uint8_t M:1; /*!< bit 4: Word length */
uint8_t UARTD:1; /*!< bit 5: UART Disable (for low power consumption) */
uint8_t T8:1; /*!< bit 6: Transmit data bit 8 */
uint8_t R8:1; /*!< bit 7: Receive Data bit 8 */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR1_type; /*!< Control register 1 (UART_CR1) */
typedef union {
struct {
uint8_t SBK:1; /*!< bit 0: Send break */
uint8_t RWU:1; /*!< bit 1: Receiver wakeup */
uint8_t REN:1; /*!< bit 2: Receiver enable */
uint8_t TEN:1; /*!< bit 3: Transmitter enable */
uint8_t ILIEN:1; /*!< bit 4: IDLE Line interrupt enable */
uint8_t RIEN:1; /*!< bit 5: Receiver interrupt enable */
uint8_t TCIEN:1; /*!< bit 6: Transmission complete interrupt enable */
uint8_t TIEN:1; /*!< bit 7: Transmitter interrupt enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR2_type; /*!< Control register 2 (UART_CR2) */
typedef union {
struct {
uint8_t LBCL:1; /*!< bit 0: Last bit clock pulse */
uint8_t CPHA:1; /*!< bit 1: Clock phase */
uint8_t CPOL:1; /*!< bit 2: Clock polarity */
uint8_t CLKEN:1; /*!< bit 3: Clock enable */
uint8_t STOP:2; /*!< bit 4..5: STOP bits */
uint8_t LINEN:1; /*!< bit 6: LIN mode enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR3_type; /*!< Control register 3 (UART_CR3) */
typedef union {
struct {
uint8_t ADD:4; /*!< bit 0..3: Address of the UART node */
uint8_t LBDF:1; /*!< bit 4: LIN Break Detection Flag */
uint8_t LBDL:1; /*!< bit 5: LIN Break Detection Length */
uint8_t LBDIEN:1; /*!< bit 6: LIN Break Detection Interrupt Enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR4_type; /*!< Control register 4 (UART_CR4) */
typedef union {
struct {
uint8_t :1; /*!< bit 0: Reserved */
uint8_t IREN:1; /*!< bit 1: IrDA mode Enable */
uint8_t IRLP:1; /*!< bit 2: IrDA Low Power */
uint8_t HDSEL:1; /*!< bit 3: Half-Duplex Selection */
uint8_t NACK:1; /*!< bit 4: Smartcard NACK enable */
uint8_t SCEN:1; /*!< bit 5: Smartcard mode enable */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR5_type; /*!< Control register 5 (UART_CR5) */
typedef union {
struct {
uint8_t LSF:1; /*!< bit 0: LIN Sync Field */
uint8_t LHDF:1; /*!< bit 1: LIN Header Detection Flag */
uint8_t LHDIEN:1; /*!< bit 2: LIN Header Detection Interrupt Enable */
uint8_t :1; /*!< bit 3: Reserved */
uint8_t LASE:1; /*!< bit 4: LIN automatic resynchronisation enable */
uint8_t LSLV:1; /*!< bit 5: LIN Slave Enable */
uint8_t :1; /*!< bit 6: Reserved */
uint8_t LDUM:1; /*!< bit 7: LIN Divider Update Method */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_CR6_type; /*!< Control register 6 (UART_CR6) */
typedef union {
struct {
uint8_t GT:8; /*!< bit 0..7: Guard time value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_GTR_type; /*!< Guard time register (UART_GTR) */
typedef union {
struct {
uint8_t PSC:8; /*!< bit 0..7: Prescaler value */
} fields; /*!< structure used for bit access */
uint8_t reg; /*!< type used for register access */
} UART_PSCR_type; /*!< Prescaler register (UART_PSCR) */
// Block: UART1
typedef struct {
volatile UART_SR_type SR;
volatile UART_DR_type DR;
volatile UART_BRR1_type BRR1;
volatile UART_BRR2_type BRR2;
volatile UART_CR1_type CR1;
volatile UART_CR2_type CR2;
volatile UART_CR3_type CR3;
volatile UART_CR4_type CR4;
volatile UART_CR5_type CR5;
volatile UART_GTR_type GTR;
volatile UART_PSCR_type PSCR;
} UART1_type;
#define UART1_BASE 0x5230
#define UART1 ((UART1_type*)UART1_BASE)
#define UART1_SR (*(volatile uint8_t *)(UART1_BASE + 0x00))
#define UART1_DR (*(volatile uint8_t *)(UART1_BASE + 0x01))
#define UART1_BRR1 (*(volatile uint8_t *)(UART1_BASE + 0x02))
#define UART1_BRR2 (*(volatile uint8_t *)(UART1_BASE + 0x03))
#define UART1_CR1 (*(volatile uint8_t *)(UART1_BASE + 0x04))
#define UART1_CR2 (*(volatile uint8_t *)(UART1_BASE + 0x05))
#define UART1_CR3 (*(volatile uint8_t *)(UART1_BASE + 0x06))
#define UART1_CR4 (*(volatile uint8_t *)(UART1_BASE + 0x07))
#define UART1_CR5 (*(volatile uint8_t *)(UART1_BASE + 0x08))
#define UART1_GTR (*(volatile uint8_t *)(UART1_BASE + 0x09))
#define UART1_PSCR (*(volatile uint8_t *)(UART1_BASE + 0x0A))
// Block: UART2
typedef struct {
volatile UART_SR_type SR;
volatile UART_DR_type DR;
volatile UART_BRR1_type BRR1;
volatile UART_BRR2_type BRR2;