503 lines
23 KiB
C
503 lines
23 KiB
C
/** library to communicate using SMBus as master
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @copyright SPDX-License-Identifier: GPL-3.0-or-later
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* @date 2017-2020
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* @note peripherals used: I²C/SMBus @ref smbus_master_i2c
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*/
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/* standard libraries */
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#include <stdint.h> // standard integer types
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#include <stdlib.h> // general utilities
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/* STM32 (including CM3) libraries */
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#include <libopencm3/cm3/systick.h> // SysTick library
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#include <libopencm3/cm3/assert.h> // assert utilities
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#include <libopencm3/stm32/rcc.h> // real-time control clock library
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#include <libopencm3/stm32/gpio.h> // general purpose input output library
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#include <libopencm3/stm32/i2c.h> // SMBus library
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/* own libraries */
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#include "global.h" // global utilities
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#include "smbus_master.h" // SMBus header and definitions
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/** @defgroup smbus_master_i2c I²C/SMBus peripheral used for SMBus communication
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* @{
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*/
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#define SMBUS_MASTER_I2C 3 /**< I²C peripheral ID */
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#define SMBUS_MASTER_SCL PA8 /**< GPIO pin for SMBus SCL */
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#define SMBUS_MASTER_SCL_AF GPIO_AF4 /**< GPIO pin alternate funtion for SMBus SCL */
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#define SMBUS_MASTER_SDA PB4 /**< GPIO pin for SMBus SDA */
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#define SMBUS_MASTER_SDA_AF GPIO_AF9 /**< GPIO pin alternate funtion for SMBus SDA */
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/** @} */
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/** if Packet Error Code is used */
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static bool smbus_master_pec = false;
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void smbus_master_setup(uint8_t frequency, bool pec)
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{
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// configure SMBus peripheral
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rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SCL)); // enable clock for SMBus I/O peripheral
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gpio_set(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)); // already put signal high to avoid small pulse
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin to alternate function
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gpio_set_output_options(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin output as open-drain
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gpio_set_af(GPIO_PORT(SMBUS_MASTER_SCL), SMBUS_MASTER_SCL_AF, GPIO_PIN(SMBUS_MASTER_SCL)); // set alternate function to SMBus SCL pin
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rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SDA)); // enable clock for SMBus I/O peripheral
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gpio_set(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA)); // already put signal high to avoid small pulse
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin to alternate function
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gpio_set_output_options(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin output as open-drain
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gpio_set_af(GPIO_PORT(SMBUS_MASTER_SDA), SMBUS_MASTER_SDA_AF, GPIO_PIN(SMBUS_MASTER_SDA)); // set alternate function to SMBus SDA pin
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rcc_periph_clock_enable(RCC_I2C(SMBUS_MASTER_I2C)); // enable clock for SMBus peripheral
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i2c_reset(I2C(SMBUS_MASTER_I2C)); // reset peripheral domain
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i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // SMBus needs to be disable to be configured
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // reset peripheral
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // clear peripheral reset
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if (frequency < 10) { // enforce minimum SMBus frequency
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frequency = 10;
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} else if (frequency > 100) { // enforce maximum SMBus frequency
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frequency = 100;
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}
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i2c_set_clock_frequency(I2C(SMBUS_MASTER_I2C), rcc_apb1_frequency / 1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
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// use standard mode for frequencies below 100 kHz
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i2c_set_standard_mode(I2C(SMBUS_MASTER_I2C)); // set standard mode (Sm)
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i2c_set_ccr(I2C(SMBUS_MASTER_I2C), rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency of 100 kHz
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i2c_set_trise(I2C(SMBUS_MASTER_I2C), (1000 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SMBUS; // set I²C peripheral in SMBus mode (not host type, not using ARP)
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smbus_master_pec = pec; // remember if PEC is used
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if (smbus_master_pec) {
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_ENPEC; // enable PEC calculation
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}
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i2c_peripheral_enable(I2C(SMBUS_MASTER_I2C)); // enable SMBus after configuration completed
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}
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void smbus_master_release(void)
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{
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i2c_reset(I2C(SMBUS_MASTER_I2C)); // reset SMBus peripheral configuration
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i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // disable SMBus peripheral
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rcc_periph_clock_disable(RCC_I2C(SMBUS_MASTER_I2C)); // disable clock for SMBus peripheral
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL pin back to input
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA pin back to input
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}
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bool smbus_master_check_signals(void)
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{
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// enable GPIOs to read SDA and SCL
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rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SDA)); // enable clock for SMBus I/O peripheral
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rcc_periph_clock_enable(GPIO_RCC(SMBUS_MASTER_SCL)); // enable clock for SMBus I/O peripheral
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// pull SDA and SDC low to check if there are pull-up resistors
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const uint32_t sda_moder = GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SDA)); // backup port configuration
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const uint32_t sda_pupdr = GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SDA)); // backup port configuration
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const uint32_t scl_moder = GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SCL)); // backup port configuration
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const uint32_t scl_pupdr = GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SCL)); // backup port configuration
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(SMBUS_MASTER_SDA)); // set SDA to input and pull down (weak) to check if there is an external pull up (strong)
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gpio_mode_setup(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(SMBUS_MASTER_SCL)); // set SCL to input and pull down (weak) to check if there is an external pull up (strong)
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sleep_us(100); // let signal settle
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const bool to_return = (gpio_get(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)) && gpio_get(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA))); // check if the signals are still pulled high by external stronger pull-up resistors
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GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SDA)) = sda_moder; // restore port configuration
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GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SDA)) = sda_pupdr; // restore port configuration
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GPIO_MODER(GPIO_PORT(SMBUS_MASTER_SCL)) = scl_moder; // restore port configuration
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GPIO_PUPDR(GPIO_PORT(SMBUS_MASTER_SCL)) = scl_pupdr; // restore port configuration
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return to_return;
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}
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void smbus_master_reset(void)
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{
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i2c_peripheral_disable(I2C(SMBUS_MASTER_I2C)); // disable SMBus peripheral
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // reset device
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // reset device
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i2c_peripheral_enable(I2C(SMBUS_MASTER_I2C)); // re-enable device
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}
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enum smbus_master_rc smbus_master_start(void)
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{
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bool retry = true; // retry after reset if first try failed
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enum smbus_master_rc to_return; // return code
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uint16_t sr1; // read register once, since reading/writing other registers or other events clears some flags
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try:
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to_return = SMBUS_MASTER_RC_NONE; // return code
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// send (re-)start condition
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if (I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return SMBUS_MASTER_RC_START_STOP_IN_PROGESS;
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}
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// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of SMBus peripheral in master mode after a misplaced Stop)
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systick_counter_disable(); // disable SysTick to reconfigure it
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systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a start condition)
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systick_clear(); // reset SysTick (set to 0)
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systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag
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systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
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i2c_send_start(I2C(SMBUS_MASTER_I2C)); // send start condition to start transaction
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bool timeout = false; // remember if the timeout has been reached
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systick_counter_enable(); // start timer
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while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_START) && !((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // be sure to get the current value
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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}
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while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_SB | I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && SMBUS_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // be sure to get the current value
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if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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} else if (!(sr1 & I2C_SR1_SB)) { // the start bit has not been set although we the peripheral is not busy anymore
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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} else if (!(sr1 & I2C_SR2_MSL)) { // verify if in master mode
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to_return = SMBUS_MASTER_RC_NOT_MASTER;
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} else if (timeout) { // timeout has been reached, i.e. the peripheral hangs
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to_return = SMBUS_MASTER_RC_NOT_MASTER;
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}
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if (SMBUS_MASTER_RC_NOT_MASTER == to_return && retry) { // error happened
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retry = false; // don't retry a second time
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset
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goto try;
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}
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systick_counter_disable(); // we don't need to timer anymore
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return to_return;
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}
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/** wait until stop is sent and bus is released
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* @return SMBus return code
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*/
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static enum smbus_master_rc smbus_master_wait_stop(void)
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{
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enum smbus_master_rc to_return = SMBUS_MASTER_RC_NONE; // return code
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// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of SMBus peripheral in master mode after a misplaced Stop)
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systick_counter_disable(); // disable SysTick to reconfigure it
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systick_set_frequency(500, rcc_ahb_frequency); // set timer to 2 ms (that should be long enough to send a stop condition)
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systick_clear(); // reset SysTick (set to 0)
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systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag
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systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
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bool timeout = false; // remember if the timeout has been reached
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systick_counter_enable(); // start timer
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while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_STOP) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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}
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while ((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_MSL) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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}
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while ((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_BUSY) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR)) && !timeout) { // wait until peripheral is not busy anymore
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = SMBUS_MASTER_RC_BUS_ERROR;
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}
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while ((0 == gpio_get(GPIO_PORT(SMBUS_MASTER_SCL), GPIO_PIN(SMBUS_MASTER_SCL)) || 0 == gpio_get(GPIO_PORT(SMBUS_MASTER_SDA), GPIO_PIN(SMBUS_MASTER_SDA))) && !timeout) { // wait until lines are really high again
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (timeout) { // I2C_CR1_STOP could also be used to detect a timeout, but I'm not sure when
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if (SMBUS_MASTER_RC_NONE == to_return) {
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to_return = SMBUS_MASTER_RC_TIMEOUT; // indicate timeout only when no more specific error has occurred
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}
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset
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I2C_CR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset
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}
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systick_counter_disable(); // we don't need to timer anymore
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return to_return;
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}
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enum smbus_master_rc smbus_master_stop(void)
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{
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// sanity check
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if (!(I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_BUSY)) { // release if not busy
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return SMBUS_MASTER_RC_NONE; // bus has probably already been released
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}
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if (I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_START)) { // ensure start operation is not in progress
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return SMBUS_MASTER_RC_START_STOP_IN_PROGESS; // the stop is sent after a
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}
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if (!((I2C_SR2(I2C(SMBUS_MASTER_I2C)) & I2C_SR2_TRA))) { // if we are in receiver mode
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i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // disable ACK to be able to close the communication
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}
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if (!(I2C_CR1(I2C(SMBUS_MASTER_I2C)) & (I2C_CR1_STOP))) { // only send start if not already in progress
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i2c_send_stop(I2C(SMBUS_MASTER_I2C)); // send stop to release bus
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}
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return smbus_master_wait_stop();
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}
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enum smbus_master_rc smbus_master_select_slave(uint8_t slave, bool write)
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{
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enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes
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uint16_t sr1, sr2; // read register once, since reading/writing other registers or other events clears some flags
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if (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & I2C_SR1_SB)) { // start condition has not been sent
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rc = smbus_master_start(); // send start condition
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if (SMBUS_MASTER_RC_NONE != rc) {
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return rc;
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}
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}
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if (!((sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C))) & I2C_SR2_MSL)) { // SMBus device is not in master mode
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return SMBUS_MASTER_RC_NOT_MASTER;
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}
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// select slave
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I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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i2c_send_7bit_address(I2C(SMBUS_MASTER_I2C), slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
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while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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return SMBUS_MASTER_RC_BUS_ERROR;
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}
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if (sr1 & I2C_SR1_AF) { // address has not been acknowledged
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return SMBUS_MASTER_RC_NAK;
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}
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// do not check I2C_SR2_TRA to verify if we really are in transmit or receive mode since reading SR2 also clears ADDR and starting the read/write transaction
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return SMBUS_MASTER_RC_NONE;
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}
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enum smbus_master_rc smbus_master_read(uint8_t* data, size_t data_size)
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{
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// sanity check
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if (NULL == data || 0 == data_size) { // no data to read
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return SMBUS_MASTER_RC_NONE;
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}
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if (smbus_master_pec && SIZE_MAX - 1 < data_size) { // too much data to send (we need one more byte to send the PEC)
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return SMBUS_MASTER_RC_OTHER;
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}
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// SMBus start condition check
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uint16_t sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // read once
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if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
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return SMBUS_MASTER_RC_NOT_READY;
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}
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if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well
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return SMBUS_MASTER_RC_NOT_READY;
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}
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// prepare (N)ACK (EV6_3 in RM0008)
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if (1 == data_size) {
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i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK after first byte
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} else {
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i2c_enable_ack(I2C(SMBUS_MASTER_I2C)); // NAK after next byte
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}
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uint16_t sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction
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if (!(sr2 & I2C_SR2_MSL)) { // SMBus device is not master
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return SMBUS_MASTER_RC_NOT_MASTER;
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}
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if ((sr2 & I2C_SR2_TRA)) { // SMBus device not in receiver mode
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return SMBUS_MASTER_RC_NOT_RECEIVE;
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}
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// read data
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if (smbus_master_pec) { // we want to read the PEC
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data_size++; // add one byte to read the PEC
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I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~I2C_SR1_PECERR; // clear flag
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}
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for (size_t i = 0; i < data_size; i++) { // read bytes
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// set (N)ACK (EV6_3, EV6_1)
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if (1 == data_size - i) { // prepare to sent NACK for last byte
|
|
i2c_send_stop(I2C(SMBUS_MASTER_I2C)); // already indicate we will send a stop (required to not send an ACK, and this must happen before the byte is transferred, see errata)
|
|
if (smbus_master_pec) {
|
|
I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_PEC; // prepare to receive PEC
|
|
}
|
|
i2c_nack_current(I2C(SMBUS_MASTER_I2C)); // (N)ACK current byte
|
|
i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK received byte to stop slave transmission
|
|
} else if (2 == data_size - i) { // prepare to sent NACK for second last byte
|
|
i2c_nack_next(I2C(SMBUS_MASTER_I2C)); // NACK next byte
|
|
i2c_disable_ack(I2C(SMBUS_MASTER_I2C)); // NACK received byte to stop slave transmission
|
|
} else {
|
|
i2c_enable_ack(I2C(SMBUS_MASTER_I2C)); // ACK received byte to continue slave transmission
|
|
}
|
|
while (!((sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C))) & (I2C_SR1_RxNE | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
|
|
if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
|
return SMBUS_MASTER_RC_BUS_ERROR;
|
|
}
|
|
if (!smbus_master_pec || i < data_size - 1) { // don't save the PEC
|
|
data[i] = i2c_get_data(I2C(SMBUS_MASTER_I2C)); // read received byte
|
|
}
|
|
}
|
|
|
|
if (smbus_master_pec) { // check if the PEC is correct
|
|
if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_PECERR) {
|
|
return SMBUS_MASTER_RC_PECERR;
|
|
}
|
|
}
|
|
|
|
return smbus_master_stop();
|
|
}
|
|
|
|
enum smbus_master_rc smbus_master_write(const uint8_t* data, size_t data_size)
|
|
{
|
|
// sanity check
|
|
if (NULL == data || 0 == data_size) { // no data to write
|
|
return SMBUS_MASTER_RC_NONE;
|
|
}
|
|
|
|
// SMBus start condition check
|
|
uint16_t sr1 = I2C_SR1(I2C(SMBUS_MASTER_I2C)); // read once
|
|
if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
|
|
return SMBUS_MASTER_RC_NOT_READY;
|
|
}
|
|
if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well
|
|
return SMBUS_MASTER_RC_NOT_READY;
|
|
}
|
|
|
|
// master check
|
|
uint16_t sr2 = I2C_SR2(I2C(SMBUS_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction
|
|
if (!(sr2 & I2C_SR2_MSL)) { // SMBus device is not master
|
|
return SMBUS_MASTER_RC_NOT_MASTER;
|
|
}
|
|
if (!(sr2 & I2C_SR2_TRA)) { // SMBus device not in transmitter mode
|
|
return SMBUS_MASTER_RC_NOT_TRANSMIT;
|
|
}
|
|
|
|
// write data
|
|
for (size_t i = 0; i < data_size; i++) { // write bytes
|
|
I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
|
i2c_send_data(I2C(SMBUS_MASTER_I2C), data[i]); // send byte to be written in memory
|
|
while (!(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_TxE | I2C_SR1_AF)) && !(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been transmitted
|
|
if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
|
return SMBUS_MASTER_RC_BUS_ERROR;
|
|
}
|
|
if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_AF) { // data has not been acknowledged
|
|
return SMBUS_MASTER_RC_NAK;
|
|
}
|
|
}
|
|
|
|
return SMBUS_MASTER_RC_NONE;
|
|
}
|
|
|
|
enum smbus_master_rc smbus_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size)
|
|
{
|
|
enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes
|
|
rc = smbus_master_start(); // send (re-)start condition
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
return rc;
|
|
}
|
|
rc = smbus_master_select_slave(slave, false); // select slave to read
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
if (NULL != data && data_size > 0) { // only read data if needed
|
|
rc = smbus_master_read(data, data_size); // read data (includes stop)
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
} else {
|
|
smbus_master_stop(); // sent stop condition
|
|
}
|
|
|
|
rc = SMBUS_MASTER_RC_NONE; // all went well
|
|
error:
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
smbus_master_stop(); // sent stop condition
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
enum smbus_master_rc smbus_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size)
|
|
{
|
|
enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes
|
|
rc = smbus_master_start(); // send (re-)start condition
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
return rc;
|
|
}
|
|
|
|
// select slave to write
|
|
rc = smbus_master_select_slave(slave, true);
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
|
|
// write data only is some is available
|
|
if (NULL != data && data_size > 0) {
|
|
rc = smbus_master_write(data, data_size); // write data
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
// send optional PEC
|
|
if (smbus_master_pec) {
|
|
I2C_SR1(I2C(SMBUS_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
|
I2C_CR1(I2C(SMBUS_MASTER_I2C)) |= I2C_CR1_PEC; // start transmitting PEC
|
|
while ((I2C_CR1(I2C(SMBUS_MASTER_I2C)) & I2C_CR1_PEC) && // PEC is still being transmitted
|
|
!(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_AF)) && // no NAK received
|
|
!(I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // no bus error received
|
|
if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) { // bus error has been received
|
|
return SMBUS_MASTER_RC_BUS_ERROR;
|
|
}
|
|
if (I2C_SR1(I2C(SMBUS_MASTER_I2C)) & I2C_SR1_AF) { // no ACK received
|
|
return SMBUS_MASTER_RC_NAK;
|
|
}
|
|
}
|
|
|
|
rc = SMBUS_MASTER_RC_NONE; // all went well
|
|
error:
|
|
smbus_master_stop(); // sent stop condition
|
|
return rc;
|
|
}
|
|
|
|
enum smbus_master_rc smbus_master_command_read(uint8_t slave, uint8_t command, uint8_t* data, size_t data_size)
|
|
{
|
|
enum smbus_master_rc rc = SMBUS_MASTER_RC_NONE; // to store SMBus return codes
|
|
rc = smbus_master_start(); // send (re-)start condition
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
return rc;
|
|
}
|
|
rc = smbus_master_select_slave(slave, true); // select slave to write
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
|
|
// write command
|
|
rc = smbus_master_write(&command, 1); // send memory address
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
// read data
|
|
if (NULL != data && data_size > 0) {
|
|
rc = smbus_master_start(); // send re-start condition
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
return rc;
|
|
}
|
|
rc = smbus_master_select_slave(slave, false); // select slave to read
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
rc = smbus_master_read(data, data_size); // read memory (includes stop)
|
|
if (SMBUS_MASTER_RC_NONE != rc) {
|
|
goto error;
|
|
}
|
|
} else {
|
|
smbus_master_stop(); // sent stop condition
|
|
}
|
|
|
|
rc = SMBUS_MASTER_RC_NONE;
|
|
error:
|
|
if (SMBUS_MASTER_RC_NONE != rc) { // only send stop on error
|
|
smbus_master_stop(); // sent stop condition
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
enum smbus_master_rc smbus_master_command_write(uint8_t slave, uint8_t command, const uint8_t* data, size_t data_size)
|
|
{
|
|
if (SIZE_MAX - 1 < data_size) { // prevent integer overflow
|
|
return SMBUS_MASTER_RC_OTHER;
|
|
}
|
|
if (data_size > 0 && NULL == data) {
|
|
return SMBUS_MASTER_RC_OTHER;
|
|
}
|
|
uint8_t buffer[1 + data_size]; // single buffer to write command and all data
|
|
buffer[0] = command; // save command in buffer
|
|
if (data) {
|
|
for (size_t i = 0; i < data_size; i++) {
|
|
buffer[1 + i] = data[i];
|
|
}
|
|
}
|
|
return smbus_master_slave_write(slave, buffer, 1 + data_size); // send command and data
|
|
}
|