I2C: add 10 bits slave address support, improve reliability, and remove timer
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341
lib/i2c_master.c
341
lib/i2c_master.c
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@ -16,7 +16,7 @@
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* @file i2c_master.c
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017-2018
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* @note peripherals used: I2C, timer @ref i2c_master_timer
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* @note peripherals used: I2C
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*/
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/* standard libraries */
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@ -27,22 +27,11 @@
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#include <libopencm3/stm32/rcc.h> // real-time control clock library
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#include <libopencm3/stm32/gpio.h> // general purpose input output library
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#include <libopencm3/stm32/i2c.h> // I2C library
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#include <libopencm3/stm32/timer.h> // timer utilities
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/* own libraries */
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#include "global.h" // global utilities
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#include "i2c_master.h" // I2C header and definitions
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/** @defgroup i2c_master_timer timer peripheral used for timeouts
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* @{
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*/
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#define I2C_MASTER_TIMER 4 /**< timer peripheral */
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#define I2C_MASTER_TIMEOUT 4 /**< timeout factor (compared to expected time) */
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/** @} */
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/** if the I2C peripheral uses the timer */
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static bool i2c_master_timer_usage[] = {false, false};
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/** get RCC for I2C based on I2C identifier
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* @param[in] i2c I2C base address
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* @return RCC address for I2C peripheral
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@ -191,54 +180,32 @@ void i2c_master_setup(uint32_t i2c, uint16_t frequency)
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// configure I2C peripheral
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rcc_periph_clock_enable(RCC_GPIO_PORT_SCL(i2c)); // enable clock for I2C I/O peripheral
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gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // already put signal high to avoid small pulse
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // setup I2C I/O pins
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // setup I2C I/O pins
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rcc_periph_clock_enable(RCC_GPIO_PORT_SDA(i2c)); // enable clock for I2C I/O peripheral
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gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // already put signal high to avoid small pulse
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // setup I2C I/O pins
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // setup I2C I/O pins
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
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rcc_periph_clock_enable(RCC_I2C(i2c)); // enable clock for I2C peripheral
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i2c_reset(i2c); // reset configuration
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i2c_reset(i2c); // reset peripheral domain
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i2c_peripheral_disable(i2c); // I2C needs to be disable to be configured
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if (frequency>400) { // limit frequency to 400 kHz
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I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset peripheral
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I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // clear peripheral reset
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if (0==frequency) { // don't allow null frequency
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frequency = 1;
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} else if (frequency>400) { // limit frequency to 400 kHz
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frequency = 400;
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}
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i2c_set_clock_frequency(i2c, rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
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if (frequency>100) { // use fast mode for frequencies > 100 kHz
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i2c_set_fast_mode(i2c); // set fast mode
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if (frequency>100) { // use fast mode for frequencies over 100 kHz
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i2c_set_fast_mode(i2c); // set fast mode (Fm)
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i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency (fast duty not used)
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i2c_set_trise(i2c, (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Fm mode (< 400) kHz is 300 ns
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} else {
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i2c_set_standard_mode(i2c); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
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} else { // use fast mode for frequencies below 100 kHz
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i2c_set_standard_mode(i2c); // set standard mode (Sm)
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i2c_set_ccr(i2c, rcc_apb1_frequency/(frequency*1000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
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i2c_set_trise(i2c, (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
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}
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i2c_peripheral_enable(i2c); // enable I2C after configuration completed
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// configure time for timeouts
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if (!i2c_master_timer_usage[0] && !i2c_master_timer_usage[1]) {
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rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
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timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
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timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
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timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
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timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/(frequency*1000)-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
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timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
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timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
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// wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
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timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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}
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// remember the I2C peripheral uses the timer
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if (I2C1==i2c) {
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i2c_master_timer_usage[0]=true;
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} else if (I2C2==i2c) {
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i2c_master_timer_usage[1]=true;
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}
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}
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void i2c_master_release(uint32_t i2c)
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@ -253,17 +220,6 @@ void i2c_master_release(uint32_t i2c)
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rcc_periph_clock_disable(RCC_I2C(i2c)); // disable clock for I2C peripheral
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SCL(i2c)); // put I2C I/O pins back to floating
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SDA(i2c)); // put I2C I/O pins back to floating
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// remember the I2C peripheral doesn't use the timer anymore
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if (I2C1==i2c) {
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i2c_master_timer_usage[0]=false;
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} else if (I2C2==i2c) {
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i2c_master_timer_usage[1]=false;
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}
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if (!i2c_master_timer_usage[0] && !i2c_master_timer_usage[1]) {
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timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer configuration
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer
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rcc_periph_clock_disable(RCC_TIM(I2C_MASTER_TIMER)); // disable clock for timer block
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}
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}
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bool i2c_master_check_signals(uint32_t i2c)
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@ -276,6 +232,35 @@ bool i2c_master_check_signals(uint32_t i2c)
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return (0!=gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0!=gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)));
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}
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void i2c_master_reset(uint32_t i2c)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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// follow procedure described in STM32F10xxC/D/E Errata sheet, Section 2.14.7
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i2c_peripheral_disable(i2c); // disable i2c peripheral
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SCL(i2c)); // put I2C I/O pins to general output
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gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high
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while (!gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is high
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SDA(i2c)); // put I2C I/O pins to general output
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gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high
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while (!gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is high
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gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set low (try first transition)
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while (gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is low
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gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set low (try first transition)
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while (gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is low
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gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high (try second transition)
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while (!gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c))); // ensure it is high
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gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high (try second transition)
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while (!gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // ensure it is high
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // set I2C I/O pins back
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // set I2C I/O pins back
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I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset device
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I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // reset device
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i2c_peripheral_enable(i2c); // re-enable device
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}
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bool i2c_master_start(uint32_t i2c)
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{
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@ -285,16 +270,13 @@ bool i2c_master_start(uint32_t i2c)
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}
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// send (re-)start condition
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i2c_send_start(i2c); // send start condition to start transaction
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timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return false;
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}
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i2c_send_start(i2c); // send start condition to start transaction
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while (I2C_CR1(i2c) & I2C_CR1_START); // wait until start condition has been accepted and cleared
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while ((I2C_CR1(i2c) & I2C_CR1_START)); // wait until start condition is accepted and cleared
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while (!(I2C_SR1(i2c) & I2C_SR1_SB)); // wait until start condition is transmitted
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // verify if in master mode
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return false;
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}
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@ -302,32 +284,58 @@ bool i2c_master_start(uint32_t i2c)
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return true;
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}
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bool i2c_master_select_slave(uint32_t i2c, uint8_t slave, bool write)
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bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
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if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent
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if (!i2c_master_start(i2c)) { // send start condition
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return false; // could not send start condition
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return false;
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}
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}
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not in master mode
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return false;
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}
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// select slave
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i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
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timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(i2c) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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return false;
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if (!address_10bit) { // 7-bit address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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}
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} else { // 10-bit address
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// send first part of address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = 11110000 | (((slave>>8)&0x3)<<1); // send first header (11110xx0, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10|I2C_SR1_AF))); // wait until first part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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}
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// send second part of address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = (slave&0xff); // send remaining of address
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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}
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// go into receive mode if necessary
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if (!write) {
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if (!i2c_master_start(i2c)) { // send re-start condition
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return false; // could not send start condition
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}
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// send first part of address with receive flag
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = 11110001 | (((slave>>8)&0x3)<<1); // send header (11110xx1, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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}
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}
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}
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if (write) {
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if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
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@ -353,10 +361,10 @@ bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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if (data==NULL || data_size==0) { // no data to read
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return true;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
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return false; // address has probably also not been sent
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device not master mode
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
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return false;
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}
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if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in receiver mode
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return false;
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}
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@ -364,19 +372,10 @@ bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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for (size_t i=0; i<data_size; i++) { // read bytes
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if (i==data_size-1) { // prepare to sent NACK for last byte
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i2c_disable_ack(i2c); // NACK received to stop slave transmission
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i2c_send_stop(i2c); // send STOP after receiving byte
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} else {
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i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
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}
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timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
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while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
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timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
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if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
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timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
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return false;
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}
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while (!(I2C_SR1(i2c) & I2C_SR1_RxNE)); // wait until byte has been received
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data[i] = i2c_get_data(i2c); // read received byte
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||||
}
|
||||
|
||||
|
@ -394,23 +393,19 @@ bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
|
|||
if (data==NULL || data_size==0) { // no data to write
|
||||
return true;
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
return false; // address has probably also not been sent
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master mode
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
|
||||
return false;
|
||||
}
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in transmitter mode
|
||||
return false;
|
||||
}
|
||||
|
||||
// write data
|
||||
for (size_t i=0; i<data_size; i++) { // write bytes
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
i2c_send_data(i2c, data[i]); // send byte to be written in memory
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_TxE|I2C_SR1_AF))); // wait until byte has been transmitted
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
@ -418,7 +413,7 @@ bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
|
|||
return true;
|
||||
}
|
||||
|
||||
void i2c_master_stop(uint32_t i2c)
|
||||
bool i2c_master_stop(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
|
@ -427,142 +422,104 @@ void i2c_master_stop(uint32_t i2c)
|
|||
|
||||
// sanity check
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
|
||||
return; // bus has probably already been released
|
||||
return true; // bus has probably already been released
|
||||
}
|
||||
|
||||
// send stop condition
|
||||
if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
return false;
|
||||
}
|
||||
|
||||
i2c_send_stop(i2c); // send stop to release bus
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
}
|
||||
while ((I2C_CR1(i2c) & I2C_CR1_STOP)); // wait until stop condition is accepted and cleared
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_MSL)); // wait until bus released (non master mode)
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint8_t slave, uint8_t* data, size_t data_size)
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start(i2c)) {
|
||||
if (!i2c_master_start(i2c)) { // send (re-)start condition
|
||||
return false;
|
||||
}
|
||||
if (!i2c_master_select_slave(i2c, slave, address_10bit, false)) { // select slave to read
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// read data
|
||||
if (!i2c_master_read(i2c, data, data_size)) {
|
||||
if (NULL!=data && data_size>0) { // only read data if needed
|
||||
if (!i2c_master_read(i2c, data, data_size)) { // read data
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
success = true; // all went well
|
||||
error:
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint8_t slave, const uint8_t* data, size_t data_size)
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
bool success = false; // return if write succeeded
|
||||
|
||||
if (!i2c_master_start(i2c)) { // send (re-)start condition
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start(i2c)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) {
|
||||
if (NULL!=data && data_size>0) { // write data only is some is available
|
||||
if (!i2c_master_write(i2c, data, data_size)) { // write data
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
success = true; // all went well
|
||||
error:
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_address_read(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
bool i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
bool success = false; // return if read succeeded
|
||||
if (!i2c_master_start(i2c)) { // send (re-)start condition
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
|
||||
goto error;
|
||||
}
|
||||
|
||||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send start condition
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// send address
|
||||
if (!i2c_master_write(i2c, address, address_size)) {
|
||||
if (!i2c_master_write(i2c, address, address_size)) { // send memory address
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// send re-start condition
|
||||
if (!i2c_master_start(i2c)) {
|
||||
if (!i2c_master_start(i2c)) { // send (re-)start condition
|
||||
return false;
|
||||
}
|
||||
if (!i2c_master_select_slave(i2c, slave, address_10bit, false)) { // select slave to read
|
||||
goto error;
|
||||
}
|
||||
// select slave to read
|
||||
if (!i2c_master_select_slave(i2c, slave, false)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (!i2c_master_read(i2c, data, data_size)) {
|
||||
if (!i2c_master_read(i2c, data, data_size)) { // read memory
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
@ -573,41 +530,27 @@ error:
|
|||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_address_write(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
bool i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
bool success = false; // return if write succeeded
|
||||
if (!i2c_master_start(i2c)) { // send (re-)start condition
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start(i2c)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send address
|
||||
if (!i2c_master_write(i2c, address, address_size)) {
|
||||
if (!i2c_master_write(i2c, address, address_size)) { // send memory address to write
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// write data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) { // write data
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -16,8 +16,7 @@
|
|||
* @file i2c_master.h
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017-2018
|
||||
* @note peripherals used: I2C, timer @ref i2c_master_timer
|
||||
* @warning only 7-byte I2C slave addresses are supported
|
||||
* @note peripherals used: I2C
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
|
@ -31,6 +30,11 @@ void i2c_master_setup(uint32_t i2c, uint16_t frequency);
|
|||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_release(uint32_t i2c);
|
||||
/** reset I2C peripheral, fixing any locked state
|
||||
* @note to be used after failed start and stop
|
||||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_reset(uint32_t i2c);
|
||||
/** check if SDA and SCL signals are high
|
||||
* @param[in] i2c I2C base address
|
||||
* @return SDA and SCL signals are high
|
||||
|
@ -44,62 +48,76 @@ bool i2c_master_start(uint32_t i2c);
|
|||
/** select slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C address of slave device to select
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return if slave was selected successfully (true) or error occurred (false)
|
||||
*/
|
||||
bool i2c_master_select_slave(uint32_t i2c, uint8_t slave, bool write);
|
||||
bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write);
|
||||
/** read data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
*/
|
||||
bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
/** write data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
*/
|
||||
bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I2C base address
|
||||
* @return is stop condition has been sent successfully
|
||||
*/
|
||||
void i2c_master_stop(uint32_t i2c);
|
||||
bool i2c_master_stop(uint32_t i2c);
|
||||
/** read data from slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
*/
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
/** write data to slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
*/
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
/** read from date from an I2C slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
*/
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint8_t slave, uint8_t* data, size_t data_size);
|
||||
/** write data to an I2C slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
*/
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint8_t slave, const uint8_t* data, size_t data_size);
|
||||
/** read data at specific address from an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to read from
|
||||
* @param[in] address_size address size in bytes
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
*/
|
||||
bool i2c_master_address_read(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
bool i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
/** write data at specific address on an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to write to
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||||
* @param[in] address_size address size in bytes
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
*/
|
||||
bool i2c_master_address_write(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
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bool i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
|
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Loading…
Reference in New Issue